KR20100079175A - Semiconductor device and its fabrication method - Google Patents

Semiconductor device and its fabrication method Download PDF

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Publication number
KR20100079175A
KR20100079175A KR1020080137591A KR20080137591A KR20100079175A KR 20100079175 A KR20100079175 A KR 20100079175A KR 1020080137591 A KR1020080137591 A KR 1020080137591A KR 20080137591 A KR20080137591 A KR 20080137591A KR 20100079175 A KR20100079175 A KR 20100079175A
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KR
South Korea
Prior art keywords
gate electrode
semiconductor device
buffer oxide
forming
manufacturing
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KR1020080137591A
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Korean (ko)
Inventor
김정운
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주식회사 동부하이텍
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Priority to KR1020080137591A priority Critical patent/KR20100079175A/en
Publication of KR20100079175A publication Critical patent/KR20100079175A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76832—Multiple layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for manufacturing a semiconductor device. To this end, the present invention relates to a gate electrode, unlike the conventional method in which the device's package and short circuit are generated when a contact plug formed on the gate electrode is misaligned. After removing the upper buffer oxide film and the salicide preventing film, a liner insulating film is formed on the upper part, an interlayer insulating film is formed on the upper part, and after patterning, a contact plug is formed by burying a metal material to form a contact plug. Even when aligned, it is possible to prevent the leakage and short circuit of the device.

Description

Semiconductor device and manufacturing method therefor {SEMICONDUCTOR DEVICE AND ITS FABRICATION METHOD}

The present invention relates to a technique for manufacturing a semiconductor device, and more particularly, to a semiconductor device suitable for preventing the misalignment of the contact plug on the gate electrode and a method of manufacturing the same.

As is well known, as the semiconductor devices are highly integrated, the junction of the impurity diffusion layer of the transistor, that is, the source / drain regions, becomes increasingly shallow, and the shallow junction trend increases the resistance of the impurity diffusion layer to increase the operation of the high density device. Has a devastating effect on you. Accordingly, a salicide (Salicide: Self Aligned silicide) process for reducing the resistance of the impurity diffused layer by depositing a refractory metal material on the impurity diffused layer and silicideing it has been studied.

The salicide process reduces the contact resistance between the contact plug and the gate electrode, but is vulnerable to leakage, so that the pixel area and power management of the CMOS image sensor (CIS) is important. In terms of back, a non-silicide process is used.

1A to 1B are process flowcharts illustrating a process of manufacturing a semiconductor device including a gate electrode according to the related art.

Referring to FIG. 1A, after an isolation layer (not shown) is formed, a gate oxide layer 102 is deposited on a semiconductor substrate 100 in an active region, and a polysilicon layer 104 is deposited thereon, After patterning to form a gate electrode, a buffer oxide film 106 is formed on the semiconductor substrate 100 on which the gate electrode is formed, and an implant process is performed according to the buffer oxide film 106 to form an LDD region (not shown). After forming, spacers 108 are formed on the side of the gate electrode, and source / drain regions 110a and 110b are formed on the gate electrode through an implant process. Here, the source / drain regions 110a and 110b mean regions in which high concentrations of ions are implanted.

As shown in FIG. 1B, the salicide preventing layer 112 is formed on the entire upper surface of the semiconductor substrate 100 including the gate electrode and the source / drain regions 110a and 110b using, for example, an oxide film. After that, a liner insulating film 114 is formed thereon.

Thereafter, after forming the interlayer insulating film on the semiconductor substrate 100 on which the salicide blocking film 112 and the liner insulating film 114 are formed, a contact hole having a predetermined size for forming a contact plug in a specific region of the interlayer insulating film is first formed. After the formation, a metal material (eg, tungsten, copper, etc.) forming a contact plug is deposited on the interlayer insulating film including the contact hole, and chemical mechanical polishing (CMP :) is performed to expose the interlayer insulating film. Chemical plugs are formed through a chemical mechanical polishing process to form contact plugs.

However, in the process of manufacturing the semiconductor device as described above, as shown in FIG. 2, the contact plug 118 is frequently misaligned in the gate electrode 4, and in this case, the contact plug For example, tungsten (W), which is used to form 118, may come down to the semiconductor substrate 100 such as 'A' to act as a cause of leakage, or an electrical short may occur, resulting in a defective transistor. have.

Accordingly, according to the present invention, a liner insulating film is formed after removing the buffer oxide film and the salicide prevention film on the gate electrode formed in the non-silicide region, thereby forming a leakage and short phenomenon due to the misalignment of the contact plug formed on the gate electrode. To provide a semiconductor device and a method of manufacturing the same that can be prevented.

According to an aspect of the present invention, a gate electrode formed on an upper surface of a semiconductor substrate and an upper surface of the semiconductor substrate on which the gate electrode is formed are removed and are removed from the upper surface of the gate electrode to a predetermined depth in a gate electrode defining region. A buffer oxide film, a spacer formed on a side of the buffer oxide film, a salicide prevention film formed on an upper surface of the gate electrode, the buffer oxide film and the spacer, and removed to the predetermined depth from the gate electrode defining region, A semiconductor device includes a liner insulating layer formed on an upper portion of the gate electrode, a spacer, a buffer oxide layer, and a salicide prevention layer by filling a portion removed to a predetermined depth.

In another aspect, the present invention provides a method of forming a gate electrode on a semiconductor substrate, forming a buffer oxide film on an upper surface of the semiconductor substrate on which the gate electrode is formed, and forming a gate electrode on a side of the gate electrode of the formed buffer oxide film. Forming a spacer, forming a salicide barrier layer on the entire upper surface of the semiconductor substrate on which the spacer is formed, and setting the buffer oxide layer and the salicide barrier layer in the gate electrode formation region to a predetermined depth from an upper surface of the gate electrode. And forming a liner insulating layer on the upper surface of the semiconductor substrate by etching and filling the portion etched to the predetermined depth.

The present invention is different from the conventional method in which the leakage and short circuit of the device occurs when the contact plug formed on the gate electrode is misaligned. A liner insulating film is formed, and an interlayer insulating film is formed on the upper part, and after patterning, a contact plug is formed by burying a metal material, thereby preventing the formation and short circuit of the device even when the formed contact plug is misaligned. Can be prevented, and thus the device yield can be improved.

According to the present invention, after forming a gate electrode on a semiconductor substrate, forming a buffer oxide film on the upper surface of the semiconductor substrate on which the gate electrode is formed, and forming a spacer on the side of the gate electrode of the formed buffer oxide film, the semiconductor substrate having the spacer formed thereon A salicide barrier layer is formed on the entire upper surface of the semiconductor substrate, the buffer oxide layer and the salicide barrier layer in the gate electrode formation region are etched from the top surface of the gate electrode to a predetermined depth, and the portion etched to the predetermined depth is buried in the upper portion of the semiconductor substrate. It is to form a liner insulating film on the surface, through the technical means can solve the problems in the prior art.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a view illustrating a semiconductor device including a gate electrode according to an exemplary embodiment of the present invention. The semiconductor device according to the exemplary embodiment may include a gate oxide layer 302 formed on an upper portion of the semiconductor substrate 300. A buffer oxide layer 306 formed on the gate electrode including the polysilicon layer 304 and the upper surface of the semiconductor substrate 300 on which the gate electrode is formed, and removed to a predetermined depth from the upper surface of the gate electrode in the gate electrode defining region. ) And a spacer 308 formed on the side surface of the buffer oxide film 306.

In addition, the semiconductor device according to the exemplary embodiment of the present inventive concept is formed on the upper surfaces of the gate electrode, the buffer oxide layer 306, and the spacer 308, and is removed from the upper surface of the gate electrode to a predetermined depth in the gate electrode defining region. The salicide barrier layer 312 and the liner insulating layer 314 formed on the gate electrode, the spacer 308, the buffer oxide layer 306, and the salicide barrier layer 312 are buried by filling the portion removed to a predetermined depth. It may include.

Here, the predetermined depth removed from the buffer oxide film 306 and the salicide prevention film 312 may have a range of approximately 200 kPa to 300 kPa, and the liner insulating film 314 may be, for example, a PMD (pre metal). dielectric) and the like can be formed to a thickness of approximately 300 ~ 350 Å.

4A through 4C are flowcharts illustrating a process of manufacturing a semiconductor device including a gate electrode according to an embodiment of the present invention.

Referring to FIG. 4A, after the device isolation layer (not shown) is formed, a gate oxide layer 302 is deposited on the semiconductor substrate 300 in the active region, and a polysilicon layer 304 is deposited thereon. After patterning to form a gate electrode, a buffer oxide film 306 is formed on the semiconductor substrate 100 on which the gate electrode is formed, and an implant process is performed according to the buffer oxide film 106 to form an LDD region (not shown). After the formation, the spacer 308 is formed on the side of the gate electrode using, for example, a nitride film, and the source / drain regions 310a and 310b are formed on the gate electrode through an implant process. Here, the source / drain regions 310a and 310b mean regions in which high concentrations of ions are implanted.

Then, after forming the salicide barrier layer 312 using, for example, an oxide layer or the like on the entire upper surface of the semiconductor substrate 300 including the gate electrode and the source / drain regions 310a and 310b, the salicide barrier layer ( After the photoresist pattern 314 for removing the upper portion of the gate electrode in the gate electrode formation region is formed on the semiconductor substrate 300 on which the 312 is formed, the photoresist pattern 314 formed as shown in FIG. 4B is formed. Accordingly, for example, the buffer oxide layer 306 and the salicide barrier layer 312 are etched from the upper surface of the gate electrode to a predetermined depth in the gate electrode formation region through a dry etching process or the like. Through the dry etching process, the buffer oxide layer 306 and the salicide barrier layer 312 may be removed from the upper surface of the polysilicon layer 304 to a predetermined depth, for example, approximately 200 kPa to 300 kPa.

Subsequently, the photoresist pattern 314 is removed through a predetermined ashing process, and a liner insulating layer 316 is formed thereon. Here, the liner insulating layer 316 may be formed to have a thickness of about 300 kV to 350 kW, for example, using a pre metal dielectric (PMD) or the like, thus filling the removed depth.

Thereafter, after the interlayer insulating film is formed on the semiconductor substrate 300 on which the liner insulating film 316 is formed, a contact hole having a predetermined size for forming a contact plug is first formed in a specific region of the interlayer insulating film. A metal material (for example, tungsten, copper, etc.) forming a contact plug is deposited on the interlayer insulating layer including the interlayer insulating layer, and the upper surface of the upper insulating layer is exposed through a chemical mechanical polishing (CMP) process to expose the interlayer insulating layer. Planarize to form contact plugs.

Meanwhile, FIG. 5 is a diagram illustrating a misalignment of contact plugs formed on a gate electrode in a semiconductor device manufactured according to an exemplary embodiment of the present invention. The contact plug 320 formed on the interlayer insulating layer 318 may be In the case of misalignment, it can be seen that the liner insulating layer 316 is prevented from falling down to the semiconductor substrate 300. Accordingly, device defects such as a leakage and a short can be prevented in advance.

Therefore, by removing the buffer oxide layer and the salicide barrier layer on the gate electrode and forming a liner insulating layer thereon, even if the contact plug formed on the gate electrode is misaligned, it is possible to prevent device leakage and short circuit. Can be.

In the foregoing description, various embodiments of the present invention have been described and described. However, the present invention is not necessarily limited thereto, and a person having ordinary skill in the art to which the present invention pertains can make various changes without departing from the technical spirit of the present invention. It will be readily appreciated that branch substitutions, modifications and variations are possible.

1A to 1B are process flowcharts illustrating a process of manufacturing a semiconductor device including a gate electrode according to the related art;

2 is a view illustrating a misaligned contact plug formed on a gate electrode in a conventional semiconductor device;

3 illustrates a semiconductor device including a gate electrode according to an embodiment of the present invention;

4A to 4C are flowcharts illustrating a process of manufacturing a semiconductor device including a gate electrode according to an embodiment of the present invention;

5 is a view illustrating a misaligned contact plug formed on a gate electrode in a semiconductor device manufactured according to an embodiment of the present invention.

Claims (10)

A gate electrode formed on the semiconductor substrate, A buffer oxide layer formed on an upper surface of the semiconductor substrate on which the gate electrode is formed and removed to a predetermined depth from an upper surface of the gate electrode in a gate electrode defining region; A spacer formed on a side of the buffer oxide film; A salicide barrier layer formed on an upper surface of the gate electrode, the buffer oxide layer, and the spacer and removed to the predetermined depth from the gate electrode defining region; A liner insulating layer formed on the gate electrode, the spacer, the buffer oxide layer, and the salicide prevention layer by filling the portion removed to the predetermined depth. Semiconductor device comprising a. The method of claim 1, The predetermined depth is a semiconductor device in the range of 200 kW-300 kW. The method according to claim 1 or 2, The liner insulating film is a semiconductor device (PMD). The method of claim 3, wherein The liner insulating film is a semiconductor device having a thickness of 300 GPa-350 GPa. Forming a gate electrode on the semiconductor substrate, Forming a buffer oxide film on an upper surface of the semiconductor substrate on which the gate electrode is formed; Forming a spacer on a side of the gate electrode of the formed buffer oxide layer; Forming a salicide barrier layer on the entire upper surface of the semiconductor substrate on which the spacers are formed; Etching the buffer oxide layer and the salicide barrier layer in the gate electrode formation region from a top surface of the gate electrode to a predetermined depth; Filling a portion etched to the predetermined depth to form a liner insulating layer on an upper surface of the semiconductor substrate Method for manufacturing a semiconductor device comprising a. The method of claim 5, The manufacturing method, After the forming of the buffer oxide layer, forming an LDD region using the formed buffer oxide layer Method of manufacturing a semiconductor device further comprising. The method of claim 6, The manufacturing method, Forming a source / drain region using the formed spacers after forming the spacers Method of manufacturing a semiconductor device further comprising. The method according to any one of claims 5 to 7, The predetermined depth is a method of manufacturing a semiconductor device in the range of 200 kHz-300 kHz. The method according to any one of claims 5 to 7, The liner insulating film is a semiconductor device manufacturing method formed using a pre metal dielectric (PMD). The method according to any one of claims 5 to 7, The liner insulating film is a semiconductor device manufacturing method is formed to a thickness of 300 kPa-350 kPa.
KR1020080137591A 2008-12-30 2008-12-30 Semiconductor device and its fabrication method KR20100079175A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20220020529A (en) * 2020-08-12 2022-02-21 매그나칩 반도체 유한회사 Semiconductor device
US11430863B2 (en) 2020-04-02 2022-08-30 Magnachip Semiconductor, Ltd. Semiconductor device and manufacturing method of semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11430863B2 (en) 2020-04-02 2022-08-30 Magnachip Semiconductor, Ltd. Semiconductor device and manufacturing method of semiconductor device
US11996444B2 (en) 2020-04-02 2024-05-28 Magnachip Semiconductor, Ltd. Semiconductor device and manufacturing method of semiconductor device
KR20220020529A (en) * 2020-08-12 2022-02-21 매그나칩 반도체 유한회사 Semiconductor device

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