TWI231528B - Method of preventing photoresist residues - Google Patents

Method of preventing photoresist residues Download PDF

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Publication number
TWI231528B
TWI231528B TW93117517A TW93117517A TWI231528B TW I231528 B TWI231528 B TW I231528B TW 93117517 A TW93117517 A TW 93117517A TW 93117517 A TW93117517 A TW 93117517A TW I231528 B TWI231528 B TW I231528B
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Taiwan
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patent application
scope
item
process method
photoresist
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TW93117517A
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Chinese (zh)
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TW200522154A (en
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Shang-Wei Lin
Hong-Chang Hsieh
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Taiwan Semiconductor Mfg
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Abstract

A method to prevent photoresist residues formed in a contact or via hole is provided. The method includes using a halogen-containing plasma treatment before the contact or via hole is filled with a photoresist. Due to the halogen-containing plasma treatment, amine components on the sidewalls of a via or contact hole or trench opening can be efficiently removed. Accordingly, photoresist residues or via poison can be avoided.

Description

1231528 五、發明說明(1) 【發明所屬之技術領域】 本發明是有關於一種半導體積體電路的製造方法,且特別 是有關於一種在半導體積體電路形成雙鑲嵌結構的方法。 【先前技術】 在半導體晶片中使用金屬導線使許多元件互相連結在一 起。一般而言,利用接觸窗將金屬導線連接至各個半導體 電路元件,而金屬導線之間使用介層窗來連接。通常金屬 導線及介層/接觸窗的連接點利用不同的微影、蝕刻及薄 膜沉積製程來製作。隨著半導體元件尺寸持續地縮小,使 得半導體晶片越來越小,且元件的密度越來越高,因此在 不同圖案層之間無法對準(M i sa 1 i gnment )的情形經常發 生。習知技術中在半導體晶圓製程中使用一些方法來改善 Ί政影製程的解析度’例如深紫外線(j) e e p U 11 r a - v i ο 1 e t, DUV)及超紫外線(Extreme Ultra-violet, EUV)光钱刻 技術,以提高半導體製程的解析度,其係使用波長為 193nm或是157nm之光源,乃至於更短之波長。 由於金屬導線的電阻值以及導線之間的寄生電容,產生另 一個半導體電路中多層内連線之電阻一電容(Rc)延遲的問 題,這些是影響半導體電路操作速度的主要因素。其他方 式係使用各種材質來解決RC延遲的問題,例如在半導體產 業中經常使用低介電常數材質,因其具有較低的介電常 數,此外具有低電阻值的銅金屬亦可用於取代鋁銅 (A 1 -Cu)金屬,作為導電材料。由於低介電常數材質及低1231528 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly to a method for forming a dual-mosaic structure in a semiconductor integrated circuit. [Prior Art] Many elements are connected to each other using metal wires in a semiconductor wafer. Generally, a metal window is connected to each semiconductor circuit element using a contact window, and a metal window is used to connect the metal wires. The connection points of metal wires and vias / contacts are usually made using different lithography, etching, and film deposition processes. As the size of semiconductor elements continues to shrink, semiconductor wafers are getting smaller and smaller, and the density of elements is getting higher and higher, so misalignment between different pattern layers (M i sa 1 i gnment) often occurs. In the conventional technology, some methods are used in the semiconductor wafer process to improve the resolution of Gao Zhengying's processes, such as deep ultraviolet (j) eep U 11 ra-vi ο 1 et, DUV) and extreme ultra-violet, EUV) light engraving technology to improve the resolution of semiconductor processes, it uses a light source with a wavelength of 193nm or 157nm, or even shorter wavelengths. Due to the resistance value of the metal wire and the parasitic capacitance between the wires, the problem of the resistance-capacitance (Rc) delay of the multilayer interconnection in another semiconductor circuit is caused. These are the main factors affecting the operation speed of the semiconductor circuit. Other methods use various materials to solve the problem of RC delay. For example, in the semiconductor industry, low dielectric constant materials are often used because of their lower dielectric constant. In addition, copper metals with low resistance values can also be used instead of aluminum copper (A 1 -Cu) metal as a conductive material. Due to the low dielectric constant material and low

1231528 五、發明說明(2) 電阻值之銅金屬,故可有效降低在半導體電路結構中多層 内連線的RC延遲效應。然而卻不易以傳統的蝕刻製程來蝕 刻銅金屬,故使用雙鑲嵌製程來製造銅内連線,而非傳統 的圖案化製程。 一般而言,雙鑲欲製程分成先形成溝渠(trench)之鑲嵌 製程及先形成介層洞(via hole)之鑲嵌製程,在先形成 溝渠之鑲嵌製程的步驟中,於内連線金屬介電 (Inter-metal Layer’ IMD)層上形成一溝渠開口,接著 在具有溝渠開口的I MD層上形成一圖案化光阻層,以形成 一介層洞結構。通常,形成介層洞結構的圖案化光阻層係 位於溝渠開口之内。接著進行蝕刻製程,以形成介層洞於 IMD層中,最後在介層洞及溝渠開口中填入導電材質,例 如鋁-銅或是銅金屬,以分別形成介層及溝渠導線。 在先形成介層洞之鑲嵌製程的步驟中,在具有蝕刻終止層 的I MD層中蝕刻形成介層結構,然後在具有介層結構的晶 圓上沉積圖案化光阻層,以形成溝渠結構。接著利用蝕刻 製程形成溝渠結構,且蝕刻終止層用於移除一部份的IMD 層。此外,在先形成介層洞之鑲嵌製程之特點係為形成一 光阻高分子(Polymer)填塞於介層洞中,以保護位於介層 洞下方的金屬導電層,避免溝渠蝕刻製程所造成的損害' 最後在介層洞結構及溝渠開口中填入一金屬’例如銘一銅 或銅、銀、金、合金等各種金屬,以分別形成介層及溝渠 導線。 在先形成介層洞或是溝渠之鑲嵌製程中,使用一介電層作1231528 V. Description of the invention (2) Copper metal with resistance value, so it can effectively reduce the RC delay effect of multilayer interconnects in the semiconductor circuit structure. However, it is not easy to etch copper metal by the traditional etching process. Therefore, a dual damascene process is used to manufacture copper interconnects instead of the traditional patterning process. Generally speaking, the dual damascene process is divided into a damascene process that first forms a trench and a damascene process that first forms a via hole. In the step of the damascene process that first forms a trench, the metal dielectric is interconnected. A trench opening is formed on the (Inter-metal Layer 'IMD) layer, and then a patterned photoresist layer is formed on the I MD layer having the trench opening to form a via hole structure. Generally, a patterned photoresist layer forming a via structure is located within the trench opening. Then, an etching process is performed to form a via hole in the IMD layer. Finally, a conductive material such as aluminum-copper or copper metal is filled in the via hole and the trench opening to form the via layer and the trench wire, respectively. In the step of forming a via hole first, a via structure is etched in the IMD layer with an etch stop layer, and then a patterned photoresist layer is deposited on the wafer with the via structure to form a trench structure. . An etch process is then used to form a trench structure, and an etch stop layer is used to remove a portion of the IMD layer. In addition, the feature of the damascene process of forming a via hole first is to form a photoresist polymer (Polymer) to fill in the via hole to protect the metal conductive layer under the via hole and avoid the trench etching process Damage 'Finally, a metal is filled in the via hole structure and the trench opening', for example, a copper or copper, silver, gold, alloy and other metals to form a via and a trench wire, respectively. In a damascene process where a dielectric hole or trench is first formed, a dielectric layer is used as

第7頁 1231528 五、發明說明(3) 為抗反射層(Anti-reflection Coating, ARC),且於镳 鑲嵌製程使用蝕刻終止層或是化學機械研磨 & (Chemical -mechanical Pol ishing, CMP)終止層。使用 抗反射層(ARC)的原因係為避免或是消除在微影製程中反 射光所產生的干涉或疋繞射效應。此外,為了對半導體 路的多層結構表面進行平坦化,故需要使用CMp製程或麵 回製程。通常當具有強結合性之介電層對蝕回產生 應時,使用CMP製程。 几欢 根據微影製程及平坦化製程的需求,使用氮氧化矽作 反射層’然而抗反射層在半導體電路結構中亦合 二几 問題。 9!王昇他Page 7 1231528 V. Description of the invention (3) It is an anti-reflection coating (ARC), and it is terminated by an etching stop layer or chemical mechanical polishing (CMP) in the sacrificial damascene process. Floor. The reason for using the anti-reflection layer (ARC) is to avoid or eliminate the interference or diffraction effects caused by the reflected light during the lithography process. In addition, in order to planarize the surface of a multilayer structure of a semiconductor circuit, a CMP process or a surface return process is required. Generally, a CMP process is used when a strongly bonded dielectric layer responds to etchback. Ji Huan According to the requirements of the lithography process and the planarization process, silicon oxynitride is used as the reflective layer '. However, the anti-reflection layer also has several problems in the semiconductor circuit structure. 9! Wang Sheng him

微影製程的問題是含氮之介質與D 故,含氮之介質層與_光阻層之間的互相反由基之 之光酸,導致在顯影製程中一部份的光阻益;孝先: 在介層洞或是接觸洞出現殘=緣=構的側壁。當 ^ m m On ίΌ · ·、 戈W物時此現象稱為介屉/4立 觸阻礙物(P〇lslon),在習知技術中使用—此社Θ播|層/接 來解決這些製程上的問題❶ 二、、'。構及方法 一種用於減少雙鑲嵌結構之介層阻礙物 319,=號專利案所述,其 國第6, 圖:先在基材上形成一金屬層i 1 〇及第?伴〜技=剖面 在第一保護層115上依序形成 常數二^15,接著 …止層125、第二低介電常數介電及第义匕 1231528 五、發明說明(4) 1 3 5。接著利用微影融刻製程在多層結構中形成介層/接觸 洞,移除光阻之後,利用紫外光輻射步驟來清除介層/接 觸洞上的殘留光阻。 第2圖顯示減低介層/接觸洞電阻值及移除光阻的方法,如 美國第2001/003674 0號專利申請案,先在基材2〇〇上形成 金屬層210,接著在基材20 0上依序形成一内介電層 (Inter-layer Dielectric, I LD ) 2 2 0及光阻層 2 3 0,然後 在ILD層220及光阻層230中形成接觸洞或是介層洞24〇 ,接 著利用CF及H A電漿2 5 0移除光阻殘餘物2 6 0及光阻層2 3 0 , 其中光阻殘餘物260係於介層/接觸洞的蝕刻製程中所形 成。 因此必須避免在開孔中形成光阻殘餘物,其中開孔為介 層、接觸洞或是溝渠。 【發明内容】 ^月長1么、種避免在開孔中形成光阻殘留的製程方法, t矛方去係於開孔填入光阻之前,先利用含_素的電衆 ,阻的,的係用於形成溝渠圖案。光阻例如可為DUV光 ΐ常ί : 或是電子束光阻。含氮材質或是低介 _光阻)生的來源,由於胺之故’光阻(特別是 因此、> '、…、法於曝光步驟之後完全轉移為酸性物質, 孔的側i阻ΐ餘物會附著在圖案化的特徵形狀邊緣或是開 "V。在使用光阻形成溝渠圖案於基材上之前,進行The problem of the lithography process is the nitrogen-containing medium and D. Therefore, the mutual reciprocity between the nitrogen-containing medium layer and the photoresist layer is based on the photoacid, which leads to a part of the photoresistance in the development process; First: Residual = edge = structural sidewalls appear in the via hole or contact hole. When ^ mm On, the phenomenon is called the drawer / 4 vertical contact obstruction (Pollslon), and it is used in the conventional technology—the company ’s Θ seed | layer / connection to solve these processes. The question ❶ II., '. Structure and method A method for reducing the interlayer obstruction of the dual damascene structure, as described in Patent No. 319, No. 6, Figure: First, a metal layer i 1 0 and No. 1 are formed on a substrate. Companion technology = Sequentially formed a constant two ^ 15 on the first protective layer 115, and then ... stop layer 125, the second low dielectric constant dielectric and the first meaning 1231528 V. Description of the invention (4) 1 3 5 . Then, a photolithography process is used to form a via / contact hole in the multilayer structure. After the photoresist is removed, a UV radiation step is used to remove the residual photoresist on the via / contact hole. FIG. 2 shows a method for reducing the resistance of the interlayer / contact hole and removing the photoresist. For example, US Patent Application No. 2001/003674 0, a metal layer 210 is first formed on a substrate 200, and then a substrate 20 is formed. An inter-layer dielectric (IL) 2 2 0 and a photoresist layer 2 3 0 are sequentially formed on 0, and then a contact hole or a via hole 24 is formed in the ILD layer 220 and the photoresist layer 230. 〇, and then use CF and HA plasma 250 to remove the photoresist residue 26 and the photoresist layer 230, wherein the photoresist residue 260 is formed in the interlayer / contact hole etching process. It is therefore necessary to avoid the formation of photoresist residues in the openings, which are vias, contact holes or trenches. [Summary of the Invention] ^ 1 month long, a manufacturing method for avoiding the formation of photoresist residues in the openings. Before the photoresist is filled in the openings, firstly use the electric element containing The system is used to form a trench pattern. The photoresist may be, for example, DUV light, or an electron beam photoresist. Nitrogen-containing materials or sources of low-resistance photoresistance, due to amines, 'photoresistance (especially, >', ...) is completely transferred to an acidic substance after the exposure step, and the side of the hole is blocked The residue will adhere to the edge of the patterned feature shape or open " V. Before using the photoresist to form a trench pattern on the substrate, perform

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1231528 五、發明說明(5) 電裂處理步驟’以減低位於覆蓋層表面及開孔侧壁之含氮 成分或是胺成分。 因為電衆處理可與胺反應,形成酸性環境,藉著消除或是 減低驗性成分’使得用於形成溝渠圖案的光阻不會與介層 材質之驗性物質產生反應,有效避免產生光阻殘留物或是 有害介層洞的殘留物。 【實施方式】 第3A-3D圖係繪示依據本發明在半導體電路中先形成介層 雙鑲嵌結構之製程的剖面圖。 第3A圖係繪示依據本發明在基材3〇〇形成多層材質結構之 剖面圖。 首先提供具有導線310之基材300,其中基材300為具有各 種不同元件之半導體,基材300例如可為半導體之矽基 材、矽鍺基材、絕緣矽基材(SOI)或是III—V族合成物基 材。導線3 1 0由導電材料組成,例如銅—銘或是銅金屬,此 外導線3 1 0可利用微影蝕刻法或是化學機械研磨法形成。 接著在基材3 0 0上形成多層材質結構,亦即在基材3 〇 〇上依 序形成保護層315、第一介電層320、餘刻終止層330、第 二介電層34 0及覆蓋層350。 保濩層3 1 5用於保護基材3 〇 〇上的元件,以隔離第一介電層 3 2 0所產生的雜質。保護層315例如可為氮化矽層、氮氧化 石夕層、碳化石夕或是任何與保護層31 5具有相同功能之材 貝。在一實施例中’使用氮化石夕層作為保護層3 1 $,厚度1231528 V. Description of the invention (5) Electrocracking treatment step 'to reduce the nitrogen-containing component or amine component on the surface of the cover layer and the side wall of the opening. Because the electric treatment can react with amine to form an acidic environment, the photoresist used to form the trench pattern will not react with the test material of the interlayer material by eliminating or reducing the photoreceptive components, effectively avoiding photoresist. Residues or residues of harmful vias. [Embodiment] Figures 3A-3D are cross-sectional views showing a process of forming a interlayer dual damascene structure in a semiconductor circuit according to the present invention. FIG. 3A is a cross-sectional view showing a multilayer material structure formed on a substrate 300 according to the present invention. First, a substrate 300 having a wire 310 is provided. The substrate 300 is a semiconductor with various components. The substrate 300 may be, for example, a silicon substrate of a semiconductor, a silicon germanium substrate, an insulating silicon substrate (SOI), or III— Group V composite substrate. The conductive wire 3 1 0 is composed of a conductive material, such as copper-metal or copper metal. In addition, the conductive wire 3 1 0 can be formed by a lithographic etching method or a chemical mechanical polishing method. Next, a multi-layer material structure is formed on the substrate 300, that is, a protective layer 315, a first dielectric layer 320, an epitaxial termination layer 330, a second dielectric layer 3400, and a protective layer 315 are sequentially formed on the substrate 300. Cover layer 350. The protective layer 3 15 is used to protect the components on the substrate 300 to isolate impurities generated by the first dielectric layer 3 2 0. The protective layer 315 may be, for example, a silicon nitride layer, a oxynitride layer, a carbide stone layer, or any material having the same function as the protective layer 315. In an embodiment ’using a nitrided layer as a protective layer 3 1 $, thickness

第10頁 1231528 五、發明說明(6) ===埃蔽之間,且利用常壓化學氣相沉積法 積法(_形成之。當進行介層洞/接:洞敍 '王時,蝕刻終止層3 3 0用於避免底層受到損害,以 成雙鑲嵌結構。一般而f ’蝕刻製程對第二介電層34〇丄 2餘刻終止層3 3 0具有更高的餘刻率。當使用氮化\夕層作 為蝕刻終止層330時,氮化矽層的厚度介於〇至1〇〇〇埃曰之 間、,且利用常壓化學氣相沉積法(ApcvD)或是低壓化學氣 相沉積法(LPCVD),或電漿辅助化學氣相沉積法(pEcvD) 形成之。覆蓋層3 50作為後續微影製程之抗反射層(arc)。 此外,覆蓋層3 5 0亦可作為蝕刻終止層、保護層或是其組 合之一。覆蓋層35 0例如可為氮化矽層、氮氧化矽層^是 任何與覆蓋層3 5 0具有相同功能之材質。在一實施例中, 使用氮化矽層作為覆蓋層3 5 0,厚度介於5 0 0至7 0 〇埃之 間,且利用常壓化學氣相沉積法(APCVD)或是低壓化學氣 相沉積法(LPCVD),或電漿辅助化學氣相沉積法(PECV 形成之。 第一介電層320及第二介電層340可為相同或是不同低介電 常數之材質,介電常數小於4.0,例如SiLK (Poly-arylene Ether)、 FLARE (Fluorinated Poly-arylene Ether)或是 HSQ (Hydrogen Silsesquioxane)。在一實施例中,第一介電層32 0及第二 介電層340的厚度介於20 〇〇至6 0 00埃之間,且可利用旋塗 法或是化學氣相沉積法形成。在另一實施例中,第一介電Page 10, 1231528 V. Description of the invention (6) === Angstrom, and using atmospheric pressure chemical vapor deposition method (_ to form it. When the interstitial hole / connection: hole description 'Wang Shi, etching The termination layer 3 3 0 is used to prevent the bottom layer from being damaged to form a dual damascene structure. Generally, the f ′ etching process has a higher residual rate for the second dielectric layer 34.02 and the termination layer 3 3 0. When When a nitrided layer is used as the etch stop layer 330, the thickness of the silicon nitride layer is between 0 and 1,000 Angstroms, and the atmospheric pressure chemical vapor deposition method (ApcvD) or low-pressure chemical gas is used. Formed by phase deposition (LPCVD) or plasma-assisted chemical vapor deposition (pEcvD). The cover layer 3 50 is used as the anti-reflection layer (arc) in the subsequent lithography process. In addition, the cover layer 3 50 can also be used as an etching The termination layer, the protective layer, or a combination thereof. The cover layer 350 may be, for example, a silicon nitride layer or a silicon oxynitride layer ^ is any material having the same function as the cover layer 350. In one embodiment, The silicon nitride layer is used as the cover layer 3 50, and the thickness is between 500 and 700 angstroms. Method (APCVD) or low pressure chemical vapor deposition (LPCVD) or plasma-assisted chemical vapor deposition (PECV). The first dielectric layer 320 and the second dielectric layer 340 may be the same or different. The material of the dielectric constant, the dielectric constant is less than 4.0, for example, SiLK (Poly-arylene Ether), FLARE (Fluorinated Poly-arylene Ether), or HSQ (Hydrogen Silsesquioxane). In one embodiment, the first dielectric layer 320 The thickness of the second dielectric layer 340 is between 2000 and 6000 angstroms, and can be formed by a spin coating method or a chemical vapor deposition method. In another embodiment, the first dielectric layer

第11頁 1231528 五、發明說明(7) _ 層 32 0及第二介電層34 0可為低介雷a 大於3.0。 ㊉數材質,其介電常數 熟習此項技術者應瞭解上述之多屉 路的製程技術及製程所使用的新^ =質結構係依據積體電 基材300上形成所有的介電層。才4而定,且並不需要在 材皙屛外,客®+ 像地’除了第3圖所示之 材貝曆外’夕層材質結構亦可包含 厂丁之 第3B圖顯示本發明第3A圖之多層;;的材質層。 構刮面圖。 口义夕盾材質結構中形成開孔的結 在覆蓋層3 5 0上形成朵p且厣f去厫— 蝕刻製程,在Λ ΛΛ )’係利用傳統的微影 =i 2 i ΐ 成一開口。接著利用圖案化的光 阻層作為餘刻罩幕,以移降一立 雷展wn、篇*丨,Γ op知的覆蓋層350、第二介 成G孔mo二:止層330、介電層320及保護層315,以形 形成介層雙鑲嵌結構之製程中,開孔_ ί二S i 。此外利用持續的非等向性蝕刻移除- Μ的多層材質結冑,此蝕刻製程可於單一反應室或是不 同的反應室進行。 第3C圖顯示在介層洞36〇中形成高分子插塞37〇後,利用電 漿處理380之結構剖面圖。接著敘述形成插塞37〇的製程及 電漿處理製程。 形成開孔36 0之後,將填充材質(未圖示)填入開孔36〇,並 ^平坦化其表面’其中填充材質例如可為樹脂等高分子材 質。然後進行蝕回步驟,以移除一部份的填充層並且形成 高分子填充物370於第3C圖之開孔36〇中,其中高分子填充 物3 7 0的目的係保護導線3丨〇,免於後續蝕刻製程的損害。Page 11 1231528 V. Description of the invention (7) _ The layer 32 0 and the second dielectric layer 3 40 may be low dielectric lightning a greater than 3.0. Number material, its dielectric constant. Those familiar with this technology should understand the above-mentioned multi-drawer process technology and the new ^ = quality structure used to form all dielectric layers on the integrated electrical substrate 300. Only 4 and it doesn't need to be in the wood material, the customer ® + like the ground 'in addition to the material shell calendar shown in Figure 3' evening layer material structure can also include the factory's 3B figure showing the first 3A picture of multiple layers ;; material layers. Structure scraping surface. A knot that forms an opening in the material structure of the mouth Yixi shield forms a p on the cover layer 3 50 and 厣 f to 厫 —etching process, using the traditional lithography = i 2 i ΐ to make an opening. Then, a patterned photoresist layer is used as a mask to remove a cover layer 350, which is known by Γ op, and a second interposer G hole Mo 2: stop layer 330, dielectric In the process of forming the layer 320 and the protective layer 315 in the shape of the interlayer double-mosaic structure, holes are formed. In addition, continuous multi-layer etching of -M is performed using continuous anisotropic etching. This etching process can be performed in a single reaction chamber or in different reaction chambers. FIG. 3C shows a cross-sectional view of the structure of the plasma treatment 380 after the polymer plug 37 is formed in the via 36 36. Next, a process for forming the plug 37 and a plasma treatment process will be described. After the openings 360 are formed, a filling material (not shown) is filled in the openings 360 and the surface thereof is flattened. The filling material may be, for example, a polymer material such as a resin. Then, an etch-back step is performed to remove a part of the filling layer and form a polymer filler 370 in the opening 36 of FIG. 3C. The purpose of the polymer filler 370 is to protect the conductor 3 丨 〇, Free from damage in subsequent etching processes.

第12頁 1231528 五、發明說明(8) 然而,亦可不需要在開孔360中形成高分子填充物370’但 是使用高分子填充物3 7 0將更有效保護基材3 0 0免於後續蝕 刻製程的損害。 接著進行電漿處理製程380,電漿處理製程38 0係使用含鹵 素之電漿,鹵素包含氟、氯、漠或是銦。假如製程中使用 含氯之電漿來處理基材,則含氯的氣體可作為氣體源,氣 體源係為C 1 2、HC卜C XC 1 y、C XH yC 1威是其組合之一,以產 生含氣的電漿。在一實施例中,電漿處理380包含氮成分 及惰性氣體,氮成分可由含氮氣體產生,例如N威是N 20, 十月性氣體可為氦、氣 '氬或是氤。較佳實施例中,以氣 (eh)作為電漿來源,其流率介於5至4〇〇sccm之間 流率介於1〇至4〇〇 SCcm之間。此外N2/0亦可用於所述之實 施例中。在另一實施例中,電漿處理380可以使用雙電源 系、、充,藉由施加介於2 〇 〇至2 〇 〇 〇 wa 11 s之上電極電源,以及 介於/0至40 0watts之下電極電源。熟習此項項技術者應知 =,微调上述實施例,而達到移除位於開孔3 6 〇中含 分或是胺之目的。 人 頁Π成一圖案化光阻層390之結構剖面®。在形 成::Ϊ嵌結構之製程中’光阻層390的目的係用於形 = 層39°例如可為DUV光阻層,或是任何光 阻如上所述,含氮材質或 ^先 源,由於胺之鹼性,井p且¥常數材貝疋胺產生的來 曝光步驟之後完全轉變為是二案, 附著在圖案化的特徵形狀邊緣或是開孔的側Page 121231528 V. Description of the invention (8) However, it is not necessary to form a polymer filler 370 'in the opening 360, but using the polymer filler 3 7 0 will more effectively protect the substrate 3 0 0 from subsequent etching Process damage. Next, a plasma treatment process 380 is performed. The plasma treatment process 380 uses a halogen-containing plasma. The halogen contains fluorine, chlorine, molybdenum, or indium. If a plasma containing chlorine is used to process the substrate in the manufacturing process, a gas containing chlorine can be used as a gas source. The gas source is C 1 2, HC, C XC 1 y, C XH yC 1 Wei is one of the combinations, To produce a gas-containing plasma. In one embodiment, the plasma treatment 380 includes a nitrogen component and an inert gas. The nitrogen component may be generated from a nitrogen-containing gas, such as N 20 is N 20, and the October gas may be helium, gas, argon, or krypton. In a preferred embodiment, gas (eh) is used as the plasma source, and the flow rate is between 5 and 400 sccm, and the flow rate is between 10 and 400 SCcm. In addition, N2 / 0 can be used in the described embodiments. In another embodiment, the plasma treatment 380 may use a dual power supply system, a charger, by applying an electrode power source between 2000 and 2000 wa 11 s, and a voltage between / 0 and 400 watts. Lower electrode power. Those skilled in the art should know that the above-mentioned embodiment is fine-tuned to achieve the purpose of removing the content or amine located in the opening 360. The human page Π forms a structural cross-section of the patterned photoresist layer 390. In the process of forming the :: embedded structure, the purpose of the photoresist layer 390 is to shape the layer 39 °. For example, it can be a DUV photoresist layer, or any photoresist, as described above, a nitrogen-containing material or a source. Due to the basicity of the amine, it is completely converted into two cases after the exposure step, which is generated by the benzylamine, and is attached to the edge of the patterned feature shape or the side of the opening.

第13頁 1231528 五、發明說明(9) 阻層39 0形成溝渠圖案於基材上之前,進行電漿處理380步 驟,以移除位於覆蓋層3 5 0表面及開孔3 6 0側壁之含氮成分 或是胺成分。因為電漿處理380可與胺反應,中和鹼基, 形成一個中性或偏酸之環境,使得用於形成溝渠圖案的光 阻層39 0不會與多層材質結構產生反應。 第4A_4C圖係繪示依據本發明在半導體電路中先形成溝渠 雙鑲嵌結構之製程的剖面圖。第4A —4C與第3A-3_同的元 件之編號增加1 0 0。這些元件包括基材4 〇 〇、導線4丨〇、保 護層415、第一介電層420、蝕刻終止層43〇、第二介電層 440、覆蓋層450及電漿處理48〇,每個元件的細節將不再 贅述。 第4A圖顯示依據本發明之類似於第3A圖之剖視圖。依序在 基材40 0上形成保護層415、第一介電層42〇、蝕刻終止層 430、第二介電層44〇及覆蓋層45〇。 第4 B圖顯 電衆·處理 示依據本發明形成開孔4 6 0於多層材質結構中及 4 8 0之結構剖視圖。 : ί : 4巧上形成光阻層(未圖示),係利用傳統的微影 阻層作:蝕ί ί Ϊ層中形成一開σ。接著利用圖案化的光 電層4二 以移除一部份的覆蓋層450及第二介 渠雙鑲爭::成:孔46°。本發明之實施例中,先形成溝 非等二孔460為一溝渠開口。此外利用持續的 中,刻移除一部份的多層材質結構,在蝕刻製程 害。如上述笛=! 介電層420 ’避免蝕刻損 呔第3B所述,此蝕刻多層材質結構的製程积Page 13 1231528 V. Description of the invention (9) Before the resist layer 39 0 forms a trench pattern on the substrate, plasma treatment 380 steps are performed to remove the inclusions on the surface of the cover layer 3 50 and the side wall of the opening 3 6 0. Nitrogen or amine. Because the plasma treatment 380 can react with amines to neutralize the bases and form a neutral or acidic environment, the photoresist layer 390 used to form the trench pattern will not react with the multilayer material structure. Figures 4A-4C are cross-sectional views illustrating a process for forming a trench dual damascene structure in a semiconductor circuit according to the present invention. The numbers of the same components as 4A-4C and 3A-3_ increase by 1 0 0. These components include a substrate 400, a wire 4o, a protective layer 415, a first dielectric layer 420, an etch stop layer 43o, a second dielectric layer 440, a cover layer 450, and a plasma treatment 48o. The details of the components will not be repeated. FIG. 4A shows a cross-sectional view similar to FIG. 3A according to the present invention. A protective layer 415, a first dielectric layer 420, an etch stop layer 430, a second dielectric layer 440, and a cover layer 450 are sequentially formed on the substrate 400. FIG. 4B shows a cross-sectional view of the structure of the openings 460 in a multilayer material structure and 480 according to the present invention. : ί: 4 A photoresist layer (not shown) is formed on the top, which is formed by using a traditional lithography resist layer to etch a ί layer. Then, a patterned photo-electric layer 42 is used to remove a part of the cover layer 450 and the second channel double-mounting :: into: hole 46 °. In the embodiment of the present invention, the trenches unequal two holes 460 are formed as a trench opening. In addition, part of the multi-layer material structure is continuously removed by etching, which is harmful in the etching process. As described above, the dielectric layer 420 ′ avoids etch damage 所述 As described in Section 3B, the manufacturing process of this multilayer material structure is etched.

1231528 五、發明說明(ίο) 同的反應室中進行。另外,並不需要將所有的材質層加入 結構中,同樣地,除了第4A圖所示之材質層之外,亦可包 含更多的材質層。 接著進行電漿處理製程480,電漿處理製程48 0係使用含鹵 素之電漿,鹵素包含氟、氯、溴或是銦。假如製程中使用 含氯之電漿來處理基材,則含氯的氣體可作為氣體源,氣 體源係為C 12、H C 1、C XC 1 y、C XH yC 1威是其組合之一,以產 生含氯的電漿。在一實施例中,電漿處理480包含氮成分 及惰性氣體,氮成分可由含氮氣體產生,例如N咸是N 20, 惰性氣體可為氦、氖、氬或是氙。值得注意的是,電漿處 理製程4 8 0並不需要使用氮及惰性氣體,較佳實施例中, 以氯作為電漿來源,其流率介於5至4 0 0 s c c m之間,且氬的 率介於1 〇至4 0 0 s c c m之間。在另一實施例中,電梁處理 4 8 0可以使用雙電源系統,藉由施加介於2 〇 〇至2 〇 〇 〇 w a 11 s 之上電極電源,以及介於0至400watts之下電極電源。熟 習此項項技術者應知如何微調上述實施例,而達到移除位 於開孔460中含氮成分或是胺之目的。 ” 第4C圖顯示依據本發明形成圖案化光阻層49〇之社構刊視 圖。在形成溝渠雙鑲嵌結構之製程中,光阻層3;〇的°目的 ,用於形成介層圖案。光阻層490例如可為Duv光阻層,或 何光阻。如上所述,含氮材質或低介電常數材士是胺 ^的來源’由於胺之驗性特性,&阻層(特 物會附荃太圖奩仆的胜外、惠祕々/ 因此’光阻殘餘 附者在圖案化的特徵邊緣或是開孔的侧1231528 V. Description of the Invention (ίο) Performed in the same reaction chamber. In addition, it is not necessary to add all material layers to the structure. Similarly, in addition to the material layers shown in FIG. 4A, more material layers can be included. Plasma treatment process 480 is followed. Plasma treatment process 480 uses a halogen-containing plasma. The halogen contains fluorine, chlorine, bromine, or indium. If a plasma containing chlorine is used to process the substrate in the process, a chlorine-containing gas can be used as a gas source. The gas source is C 12, HC 1, C XC 1 y, C XH yC 1 Wei is one of the combination, To produce a chlorine-containing plasma. In one embodiment, the plasma treatment 480 includes a nitrogen component and an inert gas. The nitrogen component may be generated from a nitrogen-containing gas, such as N 20 and N 20. The inert gas may be helium, neon, argon, or xenon. It is worth noting that the plasma treatment process 480 does not require the use of nitrogen and inert gases. In a preferred embodiment, chlorine is used as the plasma source, and its flow rate is between 5 and 40 sccm, and argon is used. The rate is between 10 and 4 0 sccm. In another embodiment, the electric beam treatment 480 can use a dual power supply system by applying an electrode power supply between 2000 and 2000 wa 11 s and an electrode power supply between 0 and 400 watts. . Those skilled in the art should know how to fine-tune the above embodiments to achieve the purpose of removing nitrogen-containing components or amines in the openings 460. Figure 4C shows a view of the social structure of the patterned photoresist layer 49〇 according to the present invention. In the process of forming the trench dual damascene structure, the photoresist layer 3 °° purpose is used to form the interlayer pattern. Light The resist layer 490 may be, for example, a Duv photoresist layer, or a photoresist. As described above, a nitrogen-containing material or a low dielectric constant material is the source of the amine ^. Due to the experimental characteristics of the amine, the &太太 图 奁 Serve's wins and benefits 々 / Therefore 'resistance of photoresist is on the edge of the patterned feature or the side of the opening

第15頁 1231528 五、發明說明(11) 阻層49 0形成溝渠圖案於基材上之前,進行電漿處理480步 驟,以減低位於覆蓋層450表面及開孔460側壁之含氮成分 或是胺成分。因為電漿處理480可與胺反應,形成光酸, 藉著消除或是減低胺成分,使得用於形成溝渠圖案的光阻 層49 0不會與第4C圖之多層材質結構產生反應。 在填充開孔(例如介層洞/接觸洞,或是具有光阻之溝渠) 之前,先施加含鹵素之電漿處理,以避免光阻殘餘物 開孔中。 [在 雖然本發明已用較佳實施例揭露如上,然其並非用时 「π μ限定 本發明,任何熟習此技藝者,在不脫離本發明之精神和_ 圍内,當可作各種之更動與潤飾,因此本發明之侔嗜二 . 丨木遴範圍 當視後附之申請專利範圍所界定者為準。Page 15 1231528 V. Description of the invention (11) Resist layer 49 0 Before forming a trench pattern on the substrate, perform a plasma treatment 480 step to reduce the nitrogen-containing component or amine located on the surface of the cover 450 and the side wall of the opening 460. ingredient. Because the plasma treatment 480 can react with amine to form a photoacid, by eliminating or reducing the amine component, the photoresist layer 49 0 used to form the trench pattern will not react with the multilayer material structure of FIG. 4C. Before filling the openings (such as vias / contact holes or trenches with photoresist), apply a plasma treatment containing halogen to avoid photoresist residues in the openings. [Although the present invention has been disclosed as above with a preferred embodiment, it is not used when "π μ defines the present invention. Any person skilled in this art can make various changes and modifications without departing from the spirit and scope of the present invention. Retouching, so the second addiction of the present invention. 丨 Mu Lin's scope shall be determined by the scope of the attached patent application.

第16頁 1231528 圖式簡單說明 【圖式簡單說明】 為讓本發明之上述和其他目的、特徵、和優點能更明顯易 懂,下文特舉較佳實施例,並配合所附圖式,作詳細說明 如下: 第1圖係繪示習知技術之一結構剖視圖。 第2圖係繪示習知技術之另一結構剖視圖。 第3A-3D圖係繪示依據本發明在半導體電路中先形成介層 雙鑲嵌結構之製程的剖面圖。Page 16 1231528 Brief description of the drawings [Simplified description of the drawings] In order to make the above and other objects, features, and advantages of the present invention more comprehensible, the following describes the preferred embodiments with the accompanying drawings to make The detailed description is as follows: FIG. 1 is a cross-sectional view showing a structure of a conventional technique. FIG. 2 is a cross-sectional view showing another structure of the conventional technology. Figures 3A-3D are cross-sectional views showing a process of forming a interlayer dual damascene structure in a semiconductor circuit according to the present invention.

第4A-4C圖係繪示依據本發明在半導體電路中先形成溝渠 雙鑲嵌結構之製程的剖面圖。 【元件代表符號簡單說明】 110金屬層115第一保護層 1 2 0第一低介電常數介電層1 2 5蝕刻終止層 130第二低介電常數介電層135第二保護層 20 0基材210金屬層 220内介電層230光阻層 240介層洞250電漿 2 6 0光阻殘餘物3 0 0基材Figures 4A-4C are cross-sectional views illustrating a process for forming a trench dual damascene structure in a semiconductor circuit according to the present invention. [Simple description of element representative symbols] 110 metal layer 115 first protective layer 1 2 0 first low dielectric constant dielectric layer 1 2 5 etch stop layer 130 second low dielectric constant dielectric layer 135 second protective layer 20 0 Substrate 210 Metal layer 220 Inner dielectric layer 230 Photoresist layer 240 Interlayer hole 250 Plasma 2 6 0 Photoresist residue 3 0 0

3 1 0導線3 1 5保護層 320第一介電層330蝕刻終止層 340第二介電層3 5 0覆蓋層 3 6 0開孔3 7 0高分子填充物 380電漿處理390光阻層3 1 0 wire 3 1 5 protective layer 320 first dielectric layer 330 etch stop layer 340 second dielectric layer 3 5 0 cover layer 3 6 0 openings 3 7 0 polymer filler 380 plasma treatment 390 photoresist layer

第17頁 1231528 圖式簡單說明 4 0 0基材41 0導線 415保護層420第一介電層 43 0蝕刻終止層440第二介電層 4 5 0覆蓋層4 6 0開孔 480電漿處理490光阻層Page 17 1231528 Brief description of the diagram 4 0 0 substrate 41 0 wire 415 protective layer 420 first dielectric layer 43 0 etch stop layer 440 second dielectric layer 4 5 0 cover layer 4 6 0 opening 480 plasma treatment 490 photoresist layer

第18頁Page 18

Claims (1)

1231528 六、申請專利範圍 1. 一種避免在開孔中形成殘留光阻的製程方法,在填入 光阻於開孔中的步驟之前,至少包含使用利用含鹵素的電 漿進行處理之步驟。 2 ·如申請專利範圍第1項所述之製程方法,其中該開孔係 為介層洞或是接觸洞。 3. 如申請專利範圍第2項所述之製程方法,其中該光阻用 於形成一溝渠圖案。 4. 如申請專利範圍第1項所述之製程方法,其中該光阻為 深紫外線(DUV)之光阻。 5. 如申請專利範圍第1項所述之製程方法,其中該開孔的 側壁上具有一氮成分。 6. 如申請專利範圍第5項所述之製程方法,其中該氮成分 至少包含胺成分。 7. 如申請專利範圍第6項所述之製程方法,其中利用含鹵 素的電漿進行處理的步驟係用以減少位於該開孔的該側壁 上之該胺成分。 8. 如申請專利範圍第1項所述之製程方法,其中利用含鹵1231528 6. Scope of patent application 1. A manufacturing method for avoiding the formation of residual photoresist in the openings. Before the step of filling the photoresist in the openings, at least the step of using a halogen-containing plasma for processing is included. 2. The process method as described in item 1 of the scope of patent application, wherein the opening is a via hole or a contact hole. 3. The process method as described in item 2 of the patent application scope, wherein the photoresist is used to form a trench pattern. 4. The process method described in item 1 of the scope of patent application, wherein the photoresist is a deep ultraviolet (DUV) photoresist. 5. The manufacturing method according to item 1 of the scope of patent application, wherein a sidewall of the opening has a nitrogen component. 6. The process method as described in item 5 of the scope of patent application, wherein the nitrogen component includes at least an amine component. 7. The process method as described in item 6 of the scope of the patent application, wherein the step of treating with a halogen-containing plasma is to reduce the amine component on the side wall of the opening. 8. The process method described in item 1 of the scope of patent application, wherein the use of halogen-containing 第19頁 1231528 六、申請專利範圍 素的電漿進行處理的步驟中至少包含使用氯反應氣體。 9.如申請專利範圍第8項所述之製程方法,其中該氯反應 氣體係選自Cl2、H(M、CxCly、CxHyCl^其組合之一。 1 Ο.如申請專利範圍第9項所述之製程方法,其中該氯反 應氣體係為C 12。 11.如申請專利範圍第1 0所述之製程方法,其中該氯反應 氣體更包含一惰性氣體。 1 2 .如申請專利範圍第11項所述之製程方法,其中該惰性 氣體為氬氣。 1 3 .如申請專利範圍第1 2項所述之製程方法,其中該C 1妁 流率介於5至4 0 0 s c c m之間,且氬的流率介於1 0至4 0 0 s c c m 之間。 1 4.如申請專利範圍第1 3項所述之製程方法,其中該氯反 應氣體更包含氮成分。 1 5 .如申請專利範圍第1 4項所述之製程方法,其中該氮成 分以N作為氣體源。Page 19 1231528 VI. Scope of patent application The process of plasma processing by element includes at least the use of chlorine reaction gas. 9. The process method as described in item 8 of the scope of the patent application, wherein the chlorine reaction gas system is selected from one of a combination of Cl2, H (M, CxCly, CxHyCl ^). The process method, wherein the chlorine reaction gas system is C 12. 11. The process method according to claim 10 in the patent application scope, wherein the chlorine reaction gas further comprises an inert gas. 1 2. As in the patent application scope item 11 The process method, wherein the inert gas is argon. 1 3. The process method according to item 12 of the scope of patent application, wherein the C 1 flow rate is between 5 and 4 0 0 sccm, and The flow rate of argon is between 10 and 400 sccm. 1 4. The process method as described in item 13 of the scope of patent application, wherein the chlorine reaction gas further comprises a nitrogen component. 1 5. According to the scope of patent application The method according to item 14, wherein the nitrogen component uses N as a gas source. 第20頁 1231528 六、申請專利範圍 1 6. —種避免在介層洞/接觸洞中形成殘留光阻的製程方 法,在填入光阻於該介層洞/接觸洞中的步驟之前,至少 包含使用含氣的電漿進行處理之步驟。 1 7 ·如申請專利範圍第1 6項所述之製程方法,其中該光阻 用於形成一溝渠圖案。 1 8.如申請專利範圍第1 7項所述之製程方法,其中該光阻 為深紫外線(DUV)之光阻。 1 9.如申請專利範圍第1 6項所述之製程方法,其中該介層 洞/接觸洞的側壁上具有一氮成分。 2 0 .如申請專利範圍第1 9項所述之製程方法,其中該氮成 分至少包含胺成分。 2 1.如申請專利範圍第2 0項所述之製程方法,其中利用該 含氯的電漿進行處理的步驟係用以減少位於該開孔的該側 壁上之該胺成分。 2 2.如申請專利範圍第1 7項所述之製程方法,其中該氯之 反應氣體係選自Cl2、HU、CxCly、CxHyCl及其組合之一。 2 3.如申請專利範圍第2 2項所述之製程方法,其中該氣之Page 20 1231528 6. Scope of patent application 1 6. — A process method to avoid the formation of residual photoresist in the via / contact hole, at least before the step of filling the photoresist in the via / contact hole, at least Contains the step of processing using a gas-containing plasma. 17 · The process method as described in item 16 of the patent application scope, wherein the photoresist is used to form a trench pattern. 1 8. The process method as described in item 17 of the scope of patent application, wherein the photoresist is a deep ultraviolet (DUV) photoresist. 19. The process method as described in item 16 of the scope of patent application, wherein the sidewall of the via / contact hole has a nitrogen component. 20. The process method as described in item 19 of the scope of patent application, wherein the nitrogen component includes at least an amine component. 2 1. The process method as described in item 20 of the scope of the patent application, wherein the step of using the chlorine-containing plasma for processing is to reduce the amine component on the side wall of the opening. 2 2. The process method as described in item 17 of the scope of patent application, wherein the reaction gas system of chlorine is selected from the group consisting of Cl2, HU, CxCly, CxHyCl, and combinations thereof. 2 3. The process method as described in item 22 of the scope of patent application, wherein the gas 第21頁 1231528 六、申請專利範圍 反應氣體係為C 1 2。 24.如申請專利範圍第23項所述之製程方法,其中該氣之 反應氣體更包含一惰性氣體。 2 5.如申請專利範圍第24項所述之製程方法,其中該惰性 氣體為氬氣。 2 6 .如申請專利範圍第2 5所述之製程方法,其中該C 1钓流 率介於5至4 0 0 s c c m之間,且氬的流率介於1 0至4 0 0 s c c m之 間。 2 7 .如申請專利範圍第2 6項所述之製程方法,其中該氯之 反應氣體更包含氮成分。 2 8 .如申請專利範圍第2 7項所述之製程方法,其中該氮成 份以N拃為氣體源。 2 9 . —種避免在雙鑲嵌結構之介層洞/接觸洞中形成殘留 光阻的製程方法,至少包含下列步驟: 提供一基材,該基材上具有含胺之材質層; 在該含胺之材質層中形成一介層洞/接觸洞; 以一含氯電漿處理該介層洞/接觸洞;以及 利用一 DUV光阻填入該介層洞/接觸洞中,以形成一溝渠圖Page 21 1231528 6. Scope of patent application The reaction gas system is C 1 2. 24. The process method as described in item 23 of the scope of patent application, wherein the reaction gas of the gas further comprises an inert gas. 2 5. The process method as described in item 24 of the scope of patent application, wherein the inert gas is argon. 26. The process method as described in claim 25, wherein the C 1 fishing flow rate is between 5 and 4 0 0 sccm, and the argon flow rate is between 10 and 4 0 0 sccm. . 27. The process method as described in item 26 of the scope of patent application, wherein the reaction gas of chlorine further comprises a nitrogen component. 28. The process method as described in item 27 of the scope of patent application, wherein the nitrogen component uses N 拃 as a gas source. 2 9. — A method for avoiding the formation of residual photoresist in the interlayer / contact hole of the dual damascene structure, including at least the following steps: providing a substrate having an amine-containing material layer on the substrate; Forming a via hole / contact hole in the amine material layer; treating the via hole / contact hole with a chlorine-containing plasma; and filling the via hole / contact hole with a DUV photoresist to form a trench pattern 第22頁 1231528 六、申請專利範圍 案。 3 0 .如申請專利範圍第2 9項所述之製程方法,其中利用含 氯的電漿進行處理的步驟係用以減少位於該介層洞/接觸 洞的該側壁上之該胺成分。 3 1.如申請專利範圍第2 9項所述之製程方法,其中該氯之 反應氣體係選自C 1 2、HC卜C XC 1 y、C XH yC 1及其組合之一。 3 2 ·如申請專利範圍第3 1項所述之製程方法,其中該氯之 反應氣體係為C1 2。 33. 如申請專利範圍第32項所述之製程方法,其中該氯之 反應氣體更包含一惰性氣體。 34. 如申請專利範圍第33項所述之製程方法,其中該惰性 氣體為氬氣。 3 5 .如申請專利範圍第34項所述之製程方法,其中該C 1钓 流率介於5至40 0 seem之間,且氬的流率介於1 0至40 Osccra 之間。 3 6 .如申請專利範圍第3 5項所述之製程方法,其中該氣反 應氣體更包含氮成分。Page 22 1231528 6. Scope of patent application. 30. The process method as described in item 29 of the scope of the patent application, wherein the step of treating with a plasma containing chlorine is used to reduce the amine component on the sidewall of the via / contact hole. 3 1. The process method as described in item 29 of the scope of the patent application, wherein the chlorine reaction gas system is selected from one of C 1 2, HC, C XC 1 y, C XH yC 1 and combinations thereof. 3 2 · The process method described in item 31 of the scope of patent application, wherein the reaction gas system of chlorine is C1 2. 33. The process method as described in item 32 of the scope of patent application, wherein the reaction gas of chlorine further comprises an inert gas. 34. The process method as described in claim 33, wherein the inert gas is argon. 35. The process method according to item 34 of the scope of patent application, wherein the C 1 fishing flow rate is between 5 and 40 0 seem, and the argon flow rate is between 10 and 40 Osccra. 36. The process method as described in item 35 of the scope of patent application, wherein the gas reaction gas further comprises a nitrogen component. 第23頁 1231528 六、申請專利範圍 3 7·如申請專利範圍第36項所述之製程方法,其中該氮成 份以N拃為氣體源。Page 23 1231528 6. Scope of patent application 37. The process method described in item 36 of the scope of patent application, wherein the nitrogen component uses N 拃 as a gas source. 第24頁Page 24
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