TW200522154A - Method of preventing photoresist residues - Google Patents

Abstract

A method to prevent photoresist residues formed in an contact or via hole is provided. The method includes using a halogen-containing plasma treatment before the contact or via hole is filled with a photoresist. Due to the halogen-containing plasma treatment, amine components on the sidewalls of a via or contact hole or trench opening can be efficiently removed. Accordingly, photoresist residues or via poison can be avoided.

Description

200522154 V. Description of the invention (1) --------- [Technical field to which the invention belongs] = A method for manufacturing a semiconductor integrated circuit, and particularly there is no reference to # method. [Prior art] In a half-V body, a 2 is used to connect many elements to each other using metal wires. In general, a metal window is connected to each semiconductor circuit element using a contact window, and a metal window is used to connect the metal wires. The connection points of metal wires and vias / contacts are usually made using different lithography, etching, and film deposition processes. As the size of semiconductor elements continues to shrink, semiconductor wafers are getting smaller and smaller, and the element size is getting larger and larger, so misalignment between different pattern layers often occurs. In the conventional technology, some methods are used in the semiconductor wafer process to improve the resolution of the lithography process, such as Deep Ultraviolet (DUV) and Extreffle Ultra — violet (EUV). Photoetching technology, in order to improve the resolution of semiconductor processes, uses a light source with a wavelength of 193 nm or 157 nm, or even shorter wavelengths. Due to the resistance value of the metal wires and the parasitic capacitance between the wires, the problem of the resistance-capacitance (R c) delay of the multilayer interconnection in another semiconductor circuit is caused. These are the main factors affecting the operating speed of the semiconductor circuit. Other methods use various materials to solve the problem of rc delay. For example, in the semiconductor industry, low dielectric constant materials are often used because of their lower dielectric constant. In addition, steel metals with low resistance values can also be used instead of aluminum steel. (A 1-Cu) metal 'as a conductive material. Due to the low dielectric constant material and low

Page 6 200522154 V. Description of the invention (2) Copper metal with resistance value, so it can effectively reduce the RC delay effect of the semiconductor interconnect. However, it is not easy to use traditional noodles. In the structure, multiple layers of copper are engraved. Therefore, a dual damascene process is used to manufacture the patterning process of steel interconnection and green engraving. In general, the double inlaying process is divided into the steps of the inlaying process of forming the trench first (the process and the inlay ^ netl of the via hole) first, in the steps of The interconnect metal dielectric is opened on an inter-metal layer (IMD) layer, and a patterned photoresist is formed on the IMD layer having a trench opening with ^ 7, followed by a via structure. . Generally, a pattern stomach 'is formed to form a via structure to be located within the trench opening. Next, an etching process is performed to convert the photoresist layer to the I MD layer, and finally fill the vias and trench openings with conductive dielectric holes such as aluminum-copper or copper metal to form the vias. And trench material. For example, in the step of forming the via hole first, the wire is used. The IMD layer was etched to form a via structure, and then a patterned photoresist layer was deposited on the circle with the via & etch stop layer to form a trench structure. A trench structure is formed by a crystallizing process, and an etch stop layer is used to remove—using etching

Floor. In addition, the 镶嵌 MD photoresist polymer (Polyraer), which is the first feature of the interlayer hole formation process, is filled in the interlayer hole to protect the metal conductive layer under the interlayer ^ hole from the trench etching process. Damage; Finally, a metal is filled in the via hole structure and the trench opening, for example, none of copper or various metals such as copper, silver, gold, and alloy to form the via and the trench wire, respectively. In the inlaying process of forming a via or a trench first, a dielectric worship is used.

200522154 V. Description of the invention (3) is an anti-reflection coating (ARC), and an etch stop layer or a chemical-mechanical polishing (CMP) stop layer is used in the dual damascene process. The reason for using the anti-reflection layer (ARC) is to avoid or eliminate the interference or diffraction effect caused by the reflected light during the lithography process. In addition, in order to planarize the surface of a multilayer structure of a semiconductor circuit, a CMP process or an etch-back process is required. Generally, a CMP process is used when a dielectric layer with strong bonding has an anti-etchback effect. According to the requirements of the lithography process and the planarization process, oxynitride is used as the anti-reflection layer. However, the anti-reflection layer also causes other problems in the semiconductor circuit structure. One of the problems affecting the DUV lithography process is the interaction between the atmosphere-containing medium and the ρυν photoresist layer. Due to the free radicals of nitrogen generated by the nitrogen-containing medium, the interaction between the nitrogen-containing medium layer and the DUV photoresist layer neutralizes the photoresist of the photoresist. Therefore, the residual light is left on the edge of the patterned feature shape or the sidewall of the structure. When residues appear in the interstitial or contact holes, this phenomenon is called interstitial / gastric barrier (Poision), and some structures and methods are used in the conventional technology to solve these process problems. / A method for reducing the interlayer obstruction of the dual damascene structure is described in U.S. Patent No. 6 319,809, in which FIG. 1 shows a cross-sectional view of a conventional technique. First, a metal layer 11 o and a first protective layer are formed on the substrate. // Then a first low-k dielectric layer 12 o, an etch stop layer 125, and a second are sequentially formed on the first protective layer 115. Low dielectric constant dielectric layer 130 and second protective layer 200522154 1 35. Then, a photolithography process is used to form a via / contact hole in the multilayer structure. After the photoresist is removed, a UV light irradiation step is used to remove the residual photoresist on the via / contact hole. θ Figure 2 shows the method of reducing the resistance of the interlayer / contact hole and removing the photoresist. For example, US Patent Application No. 2001/003674 0, a metal layer 210 is first formed on the substrate 200, and then the substrate An inter-layer dielectric (ILD) 22 0 and a photoresist layer 230 are sequentially formed on 20 0, and then a contact hole or a dielectric hole 24 is formed in the ILD layer 220 and the photo resist layer 230. Then, using CF and Η 2 0 plasma 2 50 to remove the photoresist residue 2 60 and the photoresist layer 2 3 0, wherein the photoresist residue 2 60 is in the interlayer / contact hole etching process. Formation of 0 It is therefore necessary to avoid the formation of photoresist residues in the openings, where the openings are vias, contact holes or trenches. [Summary of the Invention] The present invention provides a manufacturing method for avoiding the formation of photoresist residues in openings. This process method is to use a plasma containing plasma to process the openings before filling the photoresist in the openings. The purpose of photoresist is to form a trench pattern. The photoresist may be, for example, a DUV photoresist 'or an EUV photoresist, or an electron beam photoresist. Nitrogen-containing materials or materials with a low dielectric constant are sources of amines. Because of amines, the photoresist (especially Duv photoresist) patterns cannot be completely transferred to acidic materials after the exposure step, so 'photoresist residues will Attached to the edge of the patterned feature shape or the side wall of the opening. Before using a photoresist to form a trench pattern on a substrate,

200522154 V. Description of the invention (5) Plasma treatment step 'to reduce the component or amine component on the surface of the cover layer and the side wall of the opening. Because the plasma treatment can react with amine to form an acidic environment, by eliminating or reducing the alkaline components, the photoresist used to form the trench pattern will not react with the test substance of the interlayer material, which effectively avoids photoresist. Residues or residues of harmful vias. / [Embodiment] Figures 3A-3D are cross-sectional views showing a process of first forming a interlayer dual damascene structure in a semiconductor circuit according to the present invention. Figure 3A is a cross-sectional view showing a multilayer material structure formed on a substrate 300 according to the present invention. First, a substrate 300 having a wire 310 is provided, wherein the substrate 300 is a semiconductor with various components, and the substrate 300 may be, for example, a silicon substrate for silicon, a silicon germanium substrate, an insulating silicon substrate (S0 丨), or Is a III-v composite substrate. The conductive wire 3 1 0 is composed of a conductive material, such as copper-metal or copper metal. In addition, the conductive wire 3 1 0 can be formed by a lithographic etching method or a chemical mechanical polishing method. Next, a multi-layer material structure is formed on the substrate 300, that is, a protective layer 315, a first dielectric layer 320, an etch stop layer 330, a second dielectric layer 3400, and a protective layer 315 are sequentially formed on the substrate 300. Covering layer 3 5 0. The protective layer 315 is used to protect components on the substrate 300 to isolate impurities generated by the first dielectric layer 320. The protective layer 315 may be, for example, a silicon nitride layer, an oxynitride / silicon layer, a silicon carbide layer, or any material having the same function as the protective layer 315. In one embodiment, a silicon nitride layer is used as the protective layer 315 with a thickness

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Between 100 and 900 Angstroms' and formed by atmospheric pressure (APCVD) or low-pressure chemical vapor deposition (Lpcv = learn vapor deposition (PECVD). To, 隹-people injustice and rare carving During the manufacturing process, the final termination layer interlayer / contact hole is formed again. Generally speaking, the etching process has a higher rate for the second dielectric layer 34 than for the remaining termination layer 33G. When When a nitride nitride layer is used as the etch stop layer 330, the thickness of the silicon nitride layer is between 0 and 1,000 Angstroms, and the atmospheric pressure chemical vapor deposition method (APCVD) or low pressure chemical vapor deposition method is used. (LPCVD), or plasma-assisted chemical vapor deposition (pECVD). The cover layer 350 is used as an anti-reflection layer (ARC) in the subsequent lithographic process. In addition, the cover layer 350 can also be used as an etching stop layer, The protective layer or a combination thereof. The cover layer 350 may be, for example, a silicon nitride layer or a silicon oxynitride layer. Any material having the same function as the cover layer 350. In one embodiment, a nitrided layer is used as the cover. Layer 350 having a thickness between 50 and 700 angstroms and utilizing atmospheric pressure chemical vapor deposition (APCVD) It is formed by low pressure chemical vapor deposition (LPCVD) or plasma assisted chemical vapor deposition (pEcvS). ^ The first dielectric layer 320 and the second dielectric layer 340 may be the same or different low dielectrics. The material of the electric constant, the dielectric constant is less than 4.0, such as Si LK (Poly-arylene Ether), FLARE (Fluorinated Poly-arylene Ether) or HSQ (Hydrogen Silsesquioxane). In one embodiment, the first dielectric The thickness of the layer 280 and the first dielectric layer 340 is between 2000 and 6000 angstroms, and can be formed by a spin coating method or a chemical vapor deposition method. In another embodiment, the first Dielectric

200522154 V. Description of the invention (7) The layer 320 and the second dielectric layer 34 may be made of a low dielectric constant material, and its dielectric constant is greater than 3.0. Those familiar with this technology should understand that the above-mentioned multi-layer material structure is based on the integrated circuit process technology and the new materials used in the process, and it is not necessary to form all dielectric layers on the substrate 300. Similarly, in addition to the material buckle layer shown in FIG. 3, the multilayer material structure may also include its material layer. FIG. 3B is a cross-sectional view of a structure in which openings are formed in the multilayer material structure of FIG. 3A of the present invention. A photoresist layer (not shown) is formed on the cover layer 350, and an opening is formed in the photoresist layer by using a conventional lithography touch-etching process'. Then use the patterned photoresist layer as an etching mask to remove a part of the cover layer 35, the second dielectric layer 3 40, the #etch stop layer 3 3 0, the dielectric layer 3 2 0, and the protection. Layer 3 1 5 to form an opening 3 6 0. In the process of forming the interlayer dual damascene structure first, the opening 36 is a via hole / contact hole. In addition, part of the multilayer material structure is removed by continuous anisotropic etching. This etching process can be performed in a single reaction chamber or different reaction chambers. Figure 3C shows a cross-sectional view of the structure of the electrical destruction process 380 after the polymer plug 370 is formed in the via hole 360. Next, a process for forming the plug 370 and a plasma processing process will be described. After the openings 360 are formed, a filling material (not shown) is filled into the openings 360 and the surface thereof is flattened. The filling material may be, for example, a polymer material such as resin. Then, an etch-back step is performed to remove a part of the filling layer and form a molecular filler 3 70 in the opening 3 6 0 in FIG. 3C. The purpose of the polymer filler 3 7 0 is to protect the wire. 3 1 0, to avoid the damage of the subsequent etching process.

Page 12 200522154 V. Description of the invention (8) However, it is not necessary to form a polymer filler 3 7 0 'in the opening 3 6 0, but using the polymer filler 370 will more effectively protect the substrate 3 0 0 from Damage to subsequent etching processes. Next, a plasma treatment process 380 is performed. The plasma treatment process 380 uses a halogen-containing plasma. The halogen contains fluorine, chlorine, bromine, or indium. If a plasma containing chlorine is used to process the substrate in the process, the gas containing chlorine can be used as the gas source. The gas source is C 1 2, HC 1, C XC 1 y, C XH yC 1 and Wei is one of the combination. To produce a gas-containing plasma. In one embodiment, the plasma treatment 38 includes a nitrogen gas. The nitrogen gas may be generated from a nitrogen-containing gas, such as N minus N 20. The inert gas may be helium, neon, argon, or xenon. In a preferred embodiment, chlorine is used as the plasma source, the flow rate is between 5 and 400 seem, and the rate of argon is between 10 and 40 0 SCCm. In addition, N2 / 〇 can also be used in the described embodiments. In another embodiment, the electric power processing 380 can use a dual power source ^ on η by applying an electrode power source between 200 and 2000 watts, and how to apply the electrode power source under 400 Watts. Those skilled in the art should know that biting is the 2 embodiment described above, and the purpose of removing the nitrogen-containing scopolamine located in the opening 360 is achieved. Structure of the structure section. The resistance is as above. The resist layer 390 may be, for example, a DUV photoresist layer, or any light source. Or the low-dielectric constant material is produced by amine for the exposure step. The photoresist layer (especially DUV photoresist) cannot be attached to the pattern. Side wall. In use light

200522154 V. Description of the invention (9) Before forming the trench pattern on the substrate, the resist layer 3 9 0 is subjected to a plasma treatment step 3 8 0 to remove the inclusions on the surface of the cover 3 5 0 and the side wall of the opening 3 6 0. Nitrogen or amine. Because the plasma treatment 38 0 can react with amines, neutralize the bases, and form a neutral or acidic environment, so that the photoresist layer 39 0 used to form the trench pattern will not react with the multilayer material structure. Figures 4A-4C are cross-sectional views illustrating a process for forming a trench dual damascene structure in a semiconductor circuit according to the present invention. The numbers of the same components in 4A-4C and 3A-3D are increased by 100. These components include a substrate 400, a wire 4 10, a protective layer 415, a first dielectric layer 420, an etch stop layer 430, a second dielectric layer 4 40, a cover layer 450, and a plasma treatment 480. The details will not be repeated. FIG. 4A shows a cross-sectional view similar to FIG. 3A according to the present invention. A protective layer 415, a first dielectric layer 420, an etch stop layer 430, a second dielectric layer 440, and a cover layer 450 are sequentially formed on the substrate 400. FIG. 4B shows a cross-sectional view of a structure in which openings 460 are formed in a multilayer material structure and plasma treatment 480 according to the present invention. A photoresist layer (not shown) is formed on the cover layer 450. A conventional photolithographic etching process is used to form an opening in the photoresist layer. Then, a patterned photoresist layer is used as an etching mask to remove a part of the cover layer 450 and the second dielectric layer 440 to form an opening 460. In the embodiment of the present invention, a trench dual mosaic structure is first formed, and the opening 460 is a trench opening. In addition, part of the multilayer material structure is removed by continuous anisotropic etching. During the etching process, the etch stop layer 4 3 0 is used to protect the first dielectric layer 4 2 0 and avoid etch damage. As described in Section 3B above, the process of etching a multilayer material structure can be

Page 14 200522154 V. Description of the Invention (ίο) Performed in the same reaction chamber. In addition, it is not necessary to add all material layers to the structure. Similarly, in addition to the material layers shown in FIG. 4A, more material layers can be included. Plasma treatment process 480 is followed. Plasma treatment process 480 uses a halogen-containing plasma. The halogen contains fluorine, chlorine, bromine or indium. If a plasma containing chlorine is used to process the substrate in the manufacturing process, gas containing gas can be used as a gas source. The gas source is C 1 2, HC 1, c XC 1 y, c XH yc 1. To produce a gas-containing plasma. In one embodiment, the plasma treatment 480 includes a nitrogen component and an inert gas. The nitrogen component may be generated from a nitrogen-containing gas, such as N or N20. The inert gas may be helium, neon, argon, or xenon. It is worth noting that the plasma treatment process 480 does not require the use of nitrogen and inert gases. In a preferred embodiment, chlorine is used as the source of the electropolymerization. Its flow rate is between 5 and 40 sccm, and argon is used. The flow rate is between 10 and 400 seem. In another embodiment, the plasma treatment 480 may use a dual power supply system by applying an electrode power source between 2000 and 2000 watts and an electrode power source between 0 and 400 watts. Those skilled in the art should know how to fine-tune the above embodiments to achieve the purpose of removing nitrogen-containing components or amines in the openings 460. FIG. 4C shows that a patterned photoresist layer is formed in accordance with the present invention. 49 ^ ^ ^ 490 ,, ^ ^ ^ 0; νΓΓ / ^ = any photoresist. As mentioned above, nitrogen-containing materials or low-dielectric-constant materials are the source of amines. "Because of the amine's experimental properties," the photoresist layer (especially thorium) cannot be completely converted into an acidic material after exposure. On the edge of the patterned feature or the side wall of the opening, 200522154

V. Description of the invention (11) Before the resist layer 490 forms a trench pattern on the substrate, a plasma treatment 48 () + step is performed to reduce the nitrogen content on the surface of the cover layer 4 50 and the side wall of the opening 4 6 0. Or amine. Because plasma treatment 480 can react with amines to form photoacids. By eliminating or reducing the amine component, the & woodblock photoresist layer 49 0 used to form the trench pattern will not have a multilayer material structure as shown in FIG. 4C. Produce a response. Before filling the openings (such as vias / contact holes, or trenches with photoresistance, apply plasma treatment with peptin to avoid photoresistive bushes). Thread remains

Although the present invention has been disclosed as above with the preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and decorations without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be determined by the scope of the attached patent application.

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200522154 Brief description of the drawings [Simplified description of the drawings] In order to make the above and other objects, features, and advantages of the present invention more comprehensible, the preferred embodiments are described below in detail with the accompanying drawings, as described below in detail : Figure 1 is a cross-sectional view showing a structure of a conventional technique. FIG. 2 is a cross-sectional view showing another structure of the conventional technology. Figures 3A-3D are cross-sectional views showing a process of forming a interlayer dual damascene structure in a semiconductor circuit according to the present invention.

Figures 4A-4C are cross-sectional views illustrating a process for forming a trench dual damascene structure in a semiconductor circuit according to the present invention. [Simple description of element representative symbols] 110 metal layer 115 first protective layer 1 2 0 first low dielectric constant dielectric layer 1 2 5 etch stop layer 130 second low dielectric constant dielectric layer 135 second protective layer 2 0 0 Substrate 210 Metal layer 220 Inner dielectric layer 230 Photoresist layer 240 Interlayer hole 250 Plasma

2 6 0 Photoresist residue 3 0 0 Substrate 3 1 0 Wire 3 1 5 Protective layer 320 First dielectric layer 330 Etch stop layer 34 0 Second dielectric layer 3 5 0 Cover layer 3 6 0 Opening hole 3 7 0 Polymer Filler 380 Plasma Treatment 390 Photoresist Layer

Page 17 200522154 Brief description of the diagram 4 0 0 substrate 4 1 0 wire 415 protective layer 420 first dielectric layer 430 etch stop layer 440 second dielectric layer 4 5 0 cover layer 4 6 0 opening 480 plasma treatment 490 photoresist layer

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Claims (1)

200522154 VI. Scope of patent application 1. A manufacturing method for avoiding the formation of residual photoresist in the openings. Before the step of filling the photoresist in the openings, at least the step of using a plasma containing i element for processing is included. 2. The process method described in item 1 of the scope of patent application, wherein the opening is a via hole or a contact hole. 3. The process method as described in item 2 of the patent application scope, wherein the photoresist is used to form a trench pattern. 4. The process method described in item 1 of the scope of patent application, wherein the photoresist is a deep ultraviolet (DUV) photoresist. 5. The manufacturing method according to item 1 of the scope of patent application, wherein a sidewall of the opening has a nitrogen component. 6. The process method as described in item 5 of the scope of patent application, wherein the nitrogen component includes at least an amine component. 7. The process method as described in item 6 of the scope of patent application, wherein the step of treating with a halogen-containing plasma is to reduce the amine component on the side wall of the opening. 8. The process method as described in item 1 of the scope of patent application, wherein the use of halogen-containing Page 19, 200522154 VI. Scope of patent application The process of plasma processing of elementary element includes at least the use of chlorine reaction gas. 9. The process method as described in item 8 of the scope of patent application, wherein the gas reaction gas system is selected from one of C 1 2, HC, C XC 1 y, C XH yC 1 and combinations thereof. 10. The process method as described in item 9 of the scope of patent application, wherein the chlorine reaction gas system is C1 2. 11. The process method as described in claim 10, wherein the gas reaction gas further comprises an inert gas. 1 2. The process method as described in item 11 of the scope of patent application, wherein the inert gas is argon. 1 3. The process method as described in item 12 of the scope of patent application, wherein the C 1 flow rate is between 5 and 4 0 0 sccm, and the flow rate of argon is between 10 and 4 0 0 sccm. between. 14. The process method as described in item 13 of the scope of patent application, wherein the chlorine reaction gas further includes a nitrogen component. 15. The process method as described in item 14 of the scope of patent application, wherein the nitrogen component uses N 拃 as a gas source. Page 20 200522154 VI. Scope of patent application 1 6. — A process method to avoid the formation of residual photoresist in the via / contact hole, at least before the step of filling the photoresist in the via / contact hole, at least Contains the step of processing using a plasma containing chlorine. 1 7. The process method as described in item 16 of the patent application scope, wherein the photoresist is used to form a trench pattern. 1 8. The process method as described in item 17 of the scope of patent application, wherein the photoresist is a deep ultraviolet (DUV) photoresist. 19. The process method as described in item 16 of the scope of patent application, wherein the sidewall of the via / contact hole has a nitrogen component. 20. The process method as described in item 19 of the scope of patent application, wherein the nitrogen component includes at least an amine component. 2 1. The process method as described in item 20 of the scope of the patent application, wherein the step of using the chlorine-containing plasma for processing is to reduce the amine component on the side wall of the opening. 2 2. The process method as described in item 17 of the scope of the patent application, wherein the chlorine reaction gas system is selected from one of C 1 2, HC, C XC 1 y, C XH yC 1 and combinations thereof. 2 3. The process method described in item 22 of the scope of patent application, wherein the gas Page 21 200522154 — VI. Scope of Patent Application The reaction gas system is c 1 2. 24. The process method as described in item 23 of the scope of patent application, wherein the reaction gas further comprises an inert gas. 2 5 · The process method described in item 24 of the scope of patent application, the gas is argon. 2 6 · The process method according to claim 25 of the patent application scope, wherein the rate is between 5 and 40 sccin, and the flow rate of argon is between 10 and 10. 2 7 · The process method described in item 26 of the scope of patent application, the reaction gas further contains a nitrogen component. 2 8 · According to the process method described in item 27 of the scope of patent application, | N is used as the gas source. 29 · —A manufacturing method for avoiding 4 f resistance in the interlayer / contact hole of the dual damascene structure, including at least the following steps: providing a substrate having an amine-containing material layer on the substrate; Forming a via hole / contact hole in the material layer; processing the via hole / contact hole with a gas-containing plasma; and | filling the via hole / contact hole with a DUV photoresist to shape the chlorine Wherein the C 1 stream of 4 0 0 sccm in the inertia where the gas in which the gas is formed to form a residual channel 200522154 6. Application for Patent Scope. 3. · As described in item 29 of the scope of the patent application: f :: $ 丄 $ The step of using chlorine-containing electropolymerization for processing is used to plant y; i; the amine on the side wall of the hole / contact hole ingredient. ， + · 的 Process method, Xi Xi Xi 31. As the patent application scope of $ 29 "the combination of two. The reaction gas system is selected from Cl2, HCl, C 'yi process method, which contains female fatigue:? 3 2. As described in item 31 of the scope of the patent application, the reaction gas system is C 1 2. The process method of nr Μ ′, where the gas is 3 3 · The reactant gas as in item 32 of the scope of the patent application further contains an inert gas. Gas. / Π process method 'where the inert 3 4 · as in the scope of the patent application No. 33 household gas is nitrogen., + · Process method, where the C 1 ~ 35. as in the scope of the patent application No. 34 The flow rate of f is between 10 and 400 sccm, the flow rate is between 5 and 400 sccm, and the real class *. The process method, wherein the chlorine is 3 6. The response gas described in the item further contains a nitrogen component. 200522154 Page 24