JP2007335879A - 多孔質層を含む半導体発光デバイス - Google Patents
多孔質層を含む半導体発光デバイス Download PDFInfo
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- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 claims description 2
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- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 2
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- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
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- 229910005540 GaP Inorganic materials 0.000 description 1
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- 229910052785 arsenic Inorganic materials 0.000 description 1
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- 239000013078 crystal Substances 0.000 description 1
- HQWPLXHWEZZGKY-UHFFFAOYSA-N diethylzinc Chemical compound CC[Zn]CC HQWPLXHWEZZGKY-UHFFFAOYSA-N 0.000 description 1
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- 229910052698 phosphorus Inorganic materials 0.000 description 1
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- 229920002120 photoresistant polymer Polymers 0.000 description 1
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- 229910052725 zinc Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/16—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- H01L33/0093—Wafer bonding; Removal of the growth substrate
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- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/04—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
- H01L33/06—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
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- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/20—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
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- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/20—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
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- H01L33/26—Materials of the light emitting region
- H01L33/30—Materials of the light emitting region containing only elements of group III and group V of the periodic system
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Abstract
【解決手段】発光デバイスは、n型領域とp型領域の間に配置された発光層を有する半導体構造体を含む。多孔質領域は、発光層とn型領域及びp型領域のうちの1つに電気的に接続したコンタクトとの間に配置される。多孔質領域は、吸収性のコンタクトから離れる方向に光を散乱させ、これによりデバイスからの光抽出を向上させることができる。幾つかの実施形態において、多孔質領域は、GaN又はGaPのようなn型半導体材料である。
【選択図】図4
Description
32、92 n型領域
34、94、146 活性領域
36、96、148 p型領域
38、98 厚い領域、多孔質領域
40 接合領域、多孔質領域
44、120、144 nコンタクト
46、126、147 pコンタクト
121 メサ
140 多孔質領域
130、145 マウント
Claims (36)
- n型領域とp型領域との間に配置された発光層を含む半導体構造体と、
前記n型領域及び前記p型領域のうちの一方に対して電気的に接続されたコンタクトと
を具備し、
前記半導体構造体が前記コンタクトと前記発光層との間に配置された多孔質領域を含み、
前記半導体構造体が、該半導体構造体から抽出される光が放出される上部表面をさらに含み、
前記発光層が前記上部表面と前記多孔質領域との間に配置される、
ことを特徴とするデバイス。 - 前記多孔質領域が4ミクロンと40ミクロンとの間の厚さを有する、請求項1に記載のデバイス。
- 前記多孔質領域が5%と80%の間の多孔率を有し、
該多孔率が前記多孔質領域中の空気の容量百分率である、請求項1に記載のデバイス。 - 前記多孔質領域が20%と40%の間の多孔率を有し、
該多孔率が前記多孔質領域の中の空気の容量百分率である、請求項1に記載のデバイス。 - 前記多孔質領域がn型領域を含む請求項1に記載のデバイス。
- 前記多孔質領域がp型領域を含む請求項1に記載のデバイス。
- 前記多孔質領域がGaPを含む請求項1に記載のデバイス。
- 前記発光層に最も近い前記多孔質領域の表面が、該発光層に対して0.1ミクロンから0.4ミクロンだけ間隔をおかれている、請求項1に記載のデバイス。
- 前記多孔質領域が前記n型領域と前記コンタクトとの間に配置される、請求項1に記載のデバイス。
- 前記コンタクトが第1コンタクトであり、該第1コンタクトが前記半導体構造体の底部表面上の前記n型領域に対して電気的に接続された、デバイスであって、
さらに、前記半導体構造体の上部表面上の前記p型領域に対して電気的に接続された第2コンタクトを具備する、請求項9に記載のデバイス。 - 前記多孔質領域が前記p型領域と前記コンタクトとの間に配置される、請求項1に記載のデバイス。
- 前記コンタクトが第1コンタクトであり、該第1コンタクトが前記p型領域に対して電気的に接続された、デバイスであって、
さらに、前記n型領域に対して電気的に接続された第2コンタクトを具備し、
前記第1コンタクトが、前記半導体構造体の底部表面上に配置され、前記第2コンタクトの少なくとも一部分が該半導体構造体中に形成されたトレンチ内に配置される、請求項11に記載のデバイス。 - 前記コンタクトが第1コンタクトであるデバイスであって、
さらに第2コンタクトを具備し、
前記第1コンタクト及び前記第2コンタクトのうちの一方が前記半導体構造体の底部表面上に配置され、前記第1コンタクト及び前記第2コンタクトのうちの他方が前記半導体構造体中に形成されたトレンチ内に配置される、請求項1に記載のデバイス。 - 前記半導体構造体の上部表面の上に配置された導電性材料をさらに具備する、請求項13に記載のデバイス。
- 前記導電性材料がインジウムスズ酸化物を含む請求項14に記載のデバイス。
- AlInP及びInGaPの交互層を含む超格子をさらに具備し、
該超格子が、前記発光層と前記半導体構造体の上部表面との間に配置される、請求項13に記載のデバイス。 - 前記半導体構造体の側部表面が該半導体構造体の上部表面に対して実質的に垂直である、請求項1に記載のデバイス。
- 前記半導体構造体の側部表面が該半導体構造体の上部表面に対して傾斜している、請求項1に記載のデバイス。
- 前記半導体構造体の側部表面が多孔質である請求項1に記載のデバイス。
- 前記半導体構造体の上部表面の上に配置された偏光子をさらに具備する、請求項1に記載のデバイス。
- 上部表面を有する半導体構造体を具備し、
前記半導体構造体がn型領域とp型領域との間に配置された発光層を含み、
前記上部表面の第1の部分が多孔質領域の上部表面であり、
該上部表面の第2の部分が非多孔質領域の上部表面である、
ことを特徴とするデバイス。 - 前記上部表面の前記第2の部分が、前記半導体構造体から抽出される光の大部分が放出される表面である、請求項21に記載のデバイス。
- 前記発光層の側部領域が前記上部表面の前記第2の部分に対応する、請求項21に記載のデバイス。
- 前記多孔質領域がGaNである請求項21に記載のデバイス。
- n型領域とp型領域との間に配置される発光層を含んだ半導体構造体を準備する段階と、
前記半導体構造体における或る領域を多孔質にする段階と、
前記半導体構造体の上にコンタクトを形成する段階と、
を含み、
前記コンタクトが前記n型領域及び前記p型領域のうちの一方に対して電気的に接続されており、
前記半導体構造体における前記多孔質領域が、前記コンタクトと前記発光層との間に配置されており、
前記半導体構造体が、さらに、該半導体構造体から抽出される光が放出される上部表面を具備し、
前記発光層が前記上部表面と前記多孔質領域との間に配置されている、
ことを特徴とする方法。 - 前記半導体構造体を準備する段階が、成長基板の上に半導体構造体を成長させることを含み、
さらに、
前記成長基板を取り除く段階と、
前記半導体構造体をホスト基板に接合する段階と、
を含む、請求項25に記載の方法。 - 前記半導体構造体を準備する段階が、成長基板の上に半導体構造体を成長させることを含み、
さらに、
前記半導体構造体をダイシングして個別の発光デバイスにする段階と、
単一の発光デバイスをマウントに接続する段階と、
前記接続する段階の後に、前記成長基板を除去する段階と、
を含む、請求項25に記載の方法。 - さらに、前記成長基板を取り除く段階により露出した表面を粗面化する段階を含む、請求項27に記載の方法。
- さらに、前記成長基板を取り除く段階により露出した表面の上に導電性材料を形成する段階を含む、請求項27に記載の方法。
- さらに、前記成長基板を取り除く段階により露出した表面の上に偏光子を配置する段階を含む、請求項27に記載の方法。
- 前記半導体構造体における或る領域を多孔質にする段階の後に、前記多孔質領域が5%と80%との間の多孔率を有し、該多孔率が多孔質領域中の空気の容量百分率である、請求項25に記載の方法。
- 前記半導体構造体における或る領域を多孔質にする段階の後に、前記多孔質領域が20%と40%との間の多孔率を有し、該多孔率が多孔質領域中の空気の容量百分率である、請求項25に記載の方法。
- 前記多孔質領域がn型領域を含む請求項25に記載の方法。
- 前記多孔質領域がp型領域を含む請求項25に記載の方法。
- 前記多孔質領域がGaPを含む請求項25に記載の方法。
- 前記半導体構造体における或る領域を多孔質にする段階が、
前記半導体構造体の中にn型層を準備すること、
前記n型層を多孔質にすること、及び、
前記n型多孔質層をp型導電型に変換すること、
を含む、請求項25に記載の方法。
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Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/423,413 | 2006-06-09 | ||
US11/423,413 US8174025B2 (en) | 2006-06-09 | 2006-06-09 | Semiconductor light emitting device including porous layer |
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JP2012255068A Division JP5542899B2 (ja) | 2006-06-09 | 2012-11-21 | 多孔質層を含む半導体発光デバイス |
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JP2007335879A true JP2007335879A (ja) | 2007-12-27 |
JP5456957B2 JP5456957B2 (ja) | 2014-04-02 |
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EP2033238B1 (en) | 2015-10-14 |
WO2008007235A2 (en) | 2008-01-17 |
BRPI0712115A2 (pt) | 2012-01-31 |
EP2033238A2 (en) | 2009-03-11 |
WO2008007235A3 (en) | 2008-05-02 |
CN101467268A (zh) | 2009-06-24 |
BRPI0712115B1 (pt) | 2018-07-03 |
JP2013051437A (ja) | 2013-03-14 |
US8174025B2 (en) | 2012-05-08 |
TWI455346B (zh) | 2014-10-01 |
JP5456957B2 (ja) | 2014-04-02 |
CN101467268B (zh) | 2012-02-29 |
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JP5542899B2 (ja) | 2014-07-09 |
US20070284607A1 (en) | 2007-12-13 |
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