JP2007300103A - 埋め込みカーボン・ドーパントを用いた半導体デバイス - Google Patents
埋め込みカーボン・ドーパントを用いた半導体デバイス Download PDFInfo
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- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 title claims abstract description 51
- 229910052799 carbon Inorganic materials 0.000 title claims abstract description 51
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 239000002019 doping agent Substances 0.000 title description 3
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims abstract description 62
- 239000000463 material Substances 0.000 claims abstract description 48
- 230000001939 inductive effect Effects 0.000 claims abstract description 32
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 15
- 238000004519 manufacturing process Methods 0.000 claims abstract description 10
- 238000000034 method Methods 0.000 claims description 41
- 125000004432 carbon atom Chemical group C* 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 29
- 229910052710 silicon Inorganic materials 0.000 abstract description 27
- 239000010703 silicon Substances 0.000 abstract description 27
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 abstract description 2
- 230000008569 process Effects 0.000 description 18
- 238000002955 isolation Methods 0.000 description 11
- 239000000758 substrate Substances 0.000 description 8
- 229910052732 germanium Inorganic materials 0.000 description 6
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 6
- 238000012545 processing Methods 0.000 description 6
- 238000005530 etching Methods 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- 125000006850 spacer group Chemical group 0.000 description 5
- 238000001459 lithography Methods 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000013461 design Methods 0.000 description 2
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- 229920002120 photoresistant polymer Polymers 0.000 description 2
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- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
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- 238000004364 calculation method Methods 0.000 description 1
- 239000007833 carbon precursor Substances 0.000 description 1
- 230000002596 correlated effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
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- 230000006698 induction Effects 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 238000000608 laser ablation Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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- -1 nitride compound Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
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- 239000002243 precursor Substances 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000010561 standard procedure Methods 0.000 description 1
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78684—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys
- H01L29/78687—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys with a multilayer structure or superlattice structure
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Abstract
【解決手段】 半導体構造体、及び、半導体デバイス、より具体的にはN型FETデバイスを製造する方法である。本デバイスは、構造体におけるミスフィット転位の発生及び伝播を減少させる層間の界面の材料を介して応力誘発層の上に設けられる応力受容層を含む。応力受容層はシリコン(Si)であり、応力誘発層はシリコン・ゲルマニウム(SiGe)であり、材料は、デバイスを形成する間に両層をドープすることによって与えられるカーボンである。カーボンは、SiGe層全体にわたってドープすることもできる。
【選択図】 図4
Description
12:埋め込み酸化層(BOX)
14:シリコン層(Si層)
16:シリコン・ゲルマニウム層(SiGe層)
18:カーボン領域
20:シリコン層(Si層)
22:浅いトレンチ分離領域(STI)
24:ポリシリコン・ゲート
26:SiNキャップ
28:側壁スペーサ
30:エピタキシャル成長シリコン(eSi)
Claims (16)
- 半導体構造体を製造する方法であって、
層間の界面を有するように応力誘発層の上に応力受容層を形成するステップと、
前記界面におけるミスフィット転位を減少させるために、前記応力受容層と前記応力誘発層との間の前記界面にカーボン・ドーピングを行うステップと、
を含む方法。 - 前記応力誘発層は緩和SiGe層及び非緩和SiGe層の少なくとも一方を含み、前記応力受容層は上部のSi層である、請求項1に記載の方法。
- 前記カーボン・ドーピングは、
前記応力受容層と前記応力誘発層との間の界面において行われる、
前記応力受容層と前記応力誘発層との間の界面において行われ、カーボン・ドープ応力誘発層を形成する、又は、
カーボン・ドープ応力誘発層を形成するように行われる、のいずれか一つを含む、
請求項1に記載の方法。 - 前記カーボン・ドーピングの割合が、0.01%から1%(原子百分率)までの間である、請求項3に記載の方法。
- 前記カーボン・ドーピングは、前記界面において50Åから500Åまでの厚さを含む、請求項3に記載の方法。
- 前記カーボン・ドーピングは、前記応力誘発層の形成の間に行われる、請求項3に記載の方法。
- 前記カーボン・ドーピングは、前記応力受容層の形成の間に行われる、請求項3に記載の方法。
- 前記カーボン・ドーピングは、前記応力誘発層及び前記応力受容層の両方の形成の間に行われる、請求項1に記載の方法。
- 前記応力誘発層によって生成される引張応力が、前記応力誘発層と前記応力受容層との界面におけるドーピングによって安定する、請求項1に記載の方法。
- 前記応力誘発層は、緩和状態又は初期非緩和状態のSiGeである、請求項9に記載の方法。
- 前記応力受容層の上に第1のゲートを形成するステップと、
前記第1のゲート、前記応力受容層、前記応力誘発層、及び前記材料の一部を保護するステップと、
前記応力受容層、前記応力誘発層、及び前記材料の保護されていない部分に開口部を形成し、前記開口部をエピタキシャル材料で充填するステップと、
をさらに含む、請求項1に記載の方法。 - 前記応力誘発層は、引張応力を前記応力受容層に与える、請求項1に記載の方法。
- 第1の材料と第2の材料とカーボン・ドープ材料とを有する応力含有構造体の上に配置された少なくとも1つのゲート・スタックを含み、前記カーボン・ドープ材料が前記構造体におけるミスフィット転位を減少させるように構成された、半導体構造体であって、前記カーボン・ドープ材料は、
前記第1の材料と前記第2の材料との界面にある、
第1のカーボン・ドープ材料を形成する前記第1の材料内に存在する、及び、
第2のカーボン・ドープ材料を形成する前記第2の材料内に存在する、
のうちの少なくとも1つであり、
前記第1の材料は応力誘発材料であり、前記第2の材料は応力受容材料である、半導体構造体。 - SiGe応力誘発層とSi応力受容層と層状構造体におけるミスフィット転位を減少させるカーボン・ドープ材料とを含む前記層状構造体の上に配置されたN型FETデバイス含む半導体デバイス。
- 前記カーボン・ドープ材料は、0.01原子百分率から1原子百分率までの範囲であり、ドープされたカーボンが、1立方センチメートル当たり1020カーボン原子より高い濃度である、請求項14に記載のデバイス。
- 前記カーボンが、
前記SiGe応力誘発層と前記Si応力受容層との間の界面にある、
前記SiGe応力誘発層と前記Si応力受容層との間の界面、及び、カーボン・ドープSiGe応力誘発層にある、又は、
前記SiGe応力誘発層内にある、のいずれか一つである、
請求項14に記載のデバイス。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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US11/381,810 US7560326B2 (en) | 2006-05-05 | 2006-05-05 | Silicon/silcion germaninum/silicon body device with embedded carbon dopant |
US11/381810 | 2006-05-05 |
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JP2007300103A true JP2007300103A (ja) | 2007-11-15 |
JP5160137B2 JP5160137B2 (ja) | 2013-03-13 |
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US (1) | US7560326B2 (ja) |
JP (1) | JP5160137B2 (ja) |
CN (1) | CN101068004A (ja) |
TW (1) | TW200807572A (ja) |
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JP2012514348A (ja) * | 2008-12-31 | 2012-06-21 | インテル コーポレイション | 金属ソース/ドレイン及びコンフォーマル再成長ソース/ドレインにより発生される一軸性歪みを有する量子井戸mosfetチャネル |
US10269961B2 (en) | 2009-06-12 | 2019-04-23 | Sony Corporation | Semiconductor device having curved gate electrode aligned with curved side-wall insulating film and stress-introducing layer between channel region and source and drain regions |
US9947790B2 (en) | 2009-06-12 | 2018-04-17 | Sony Corporation | Semiconductor device having curved gate electrode aligned with curved side-wall insulating film and stress-introducing layer between channel region and source and drain regions |
US10854751B2 (en) | 2009-06-12 | 2020-12-01 | Sony Corporation | Semiconductor device having curved gate electrode aligned with curved side-wall insulating film and stress-introducing layer between channel region and source and drain regions |
US10535769B2 (en) | 2009-06-12 | 2020-01-14 | Sony Corporation | Semiconductor device having curved gate electrode aligned with curved side-wall insulating film and stress-introducing layer between channel region and source and drain regions |
US9337305B2 (en) | 2009-06-12 | 2016-05-10 | Sony Corporation | Semiconductor device having curved gate electrode aligned with curved side-wall insulating film and stress-introducing layer between channel region and source and drain regions |
JP2010287760A (ja) * | 2009-06-12 | 2010-12-24 | Sony Corp | 半導体装置およびその製造方法 |
US9601622B2 (en) | 2009-06-12 | 2017-03-21 | Sony Corporation | Semiconductor device having curved gate electrode aligned with curved side-wall insulating film and stress-introducing layer between channel region and source and drain regions |
KR101417977B1 (ko) * | 2012-12-28 | 2014-07-09 | 연세대학교 산학협력단 | 반도체 장치 및 그 제조 방법 |
US9806178B2 (en) | 2014-03-17 | 2017-10-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET structure and method for fabricating the same |
US9520498B2 (en) | 2014-03-17 | 2016-12-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET structure and method for fabricating the same |
US10164068B2 (en) | 2014-03-17 | 2018-12-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET structure and method for fabricating the same |
KR101646843B1 (ko) * | 2014-03-17 | 2016-08-08 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | Finfet 구조물 및 이의 형성 방법 |
KR20150108300A (ko) * | 2014-03-17 | 2015-09-25 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | Finfet 구조물 및 이의 형성 방법 |
US10998425B2 (en) | 2014-03-17 | 2021-05-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET structure and method for fabricating the same |
JP2015084440A (ja) * | 2014-12-17 | 2015-04-30 | ソニー株式会社 | 半導体装置 |
Also Published As
Publication number | Publication date |
---|---|
US7560326B2 (en) | 2009-07-14 |
JP5160137B2 (ja) | 2013-03-13 |
CN101068004A (zh) | 2007-11-07 |
US20070257249A1 (en) | 2007-11-08 |
TW200807572A (en) | 2008-02-01 |
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