JP2007142436A - 整列マーク膜を備える半導体素子及びその製造方法 - Google Patents

整列マーク膜を備える半導体素子及びその製造方法 Download PDF

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JP2007142436A
JP2007142436A JP2006313358A JP2006313358A JP2007142436A JP 2007142436 A JP2007142436 A JP 2007142436A JP 2006313358 A JP2006313358 A JP 2006313358A JP 2006313358 A JP2006313358 A JP 2006313358A JP 2007142436 A JP2007142436 A JP 2007142436A
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film
alignment mark
pad electrode
passivation
semiconductor device
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JP2006313358A
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JP2007142436A5 (enExample
Inventor
Ho-Ik Hwang
皓▲イク▼ 黄
Soo-Cheol Lee
李　受哲
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Publication of JP2007142436A publication Critical patent/JP2007142436A/ja
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
JP2006313358A 2005-11-22 2006-11-20 整列マーク膜を備える半導体素子及びその製造方法 Pending JP2007142436A (ja)

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KR1020050111994A KR100660893B1 (ko) 2005-11-22 2005-11-22 정렬 마크막을 구비하는 반도체 소자 및 그 제조 방법

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JP2007142436A true JP2007142436A (ja) 2007-06-07
JP2007142436A5 JP2007142436A5 (enExample) 2010-01-14

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US (1) US7482703B2 (enExample)
JP (1) JP2007142436A (enExample)
KR (1) KR100660893B1 (enExample)
CN (1) CN1971903B (enExample)
DE (1) DE102006056066A1 (enExample)

Cited By (4)

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