JP2007103009A5 - - Google Patents

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Publication number
JP2007103009A5
JP2007103009A5 JP2007011197A JP2007011197A JP2007103009A5 JP 2007103009 A5 JP2007103009 A5 JP 2007103009A5 JP 2007011197 A JP2007011197 A JP 2007011197A JP 2007011197 A JP2007011197 A JP 2007011197A JP 2007103009 A5 JP2007103009 A5 JP 2007103009A5
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JP
Japan
Prior art keywords
burst
semiconductor memory
refresh
cell array
signal
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Granted
Application number
JP2007011197A
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English (en)
Japanese (ja)
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JP4489784B2 (ja
JP2007103009A (ja
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Publication date
Application filed filed Critical
Priority to JP2007011197A priority Critical patent/JP4489784B2/ja
Priority claimed from JP2007011197A external-priority patent/JP4489784B2/ja
Publication of JP2007103009A publication Critical patent/JP2007103009A/ja
Publication of JP2007103009A5 publication Critical patent/JP2007103009A5/ja
Application granted granted Critical
Publication of JP4489784B2 publication Critical patent/JP4489784B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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JP2007011197A 2002-04-15 2007-01-22 半導体メモリ Expired - Lifetime JP4489784B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2007011197A JP4489784B2 (ja) 2002-04-15 2007-01-22 半導体メモリ

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2002111877 2002-04-15
JP2007011197A JP4489784B2 (ja) 2002-04-15 2007-01-22 半導体メモリ

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP2002156832A Division JP4078119B2 (ja) 2002-04-15 2002-05-30 半導体メモリ

Publications (3)

Publication Number Publication Date
JP2007103009A JP2007103009A (ja) 2007-04-19
JP2007103009A5 true JP2007103009A5 (enExample) 2007-07-05
JP4489784B2 JP4489784B2 (ja) 2010-06-23

Family

ID=35476351

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007011197A Expired - Lifetime JP4489784B2 (ja) 2002-04-15 2007-01-22 半導体メモリ

Country Status (2)

Country Link
JP (1) JP4489784B2 (enExample)
CN (1) CN100456387C (enExample)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101499314B (zh) * 2008-01-29 2012-02-29 财团法人工业技术研究院 存储器装置与其更新方法
KR101020290B1 (ko) * 2009-01-12 2011-03-07 주식회사 하이닉스반도체 버스트모드 제어회로
KR102479500B1 (ko) * 2018-08-09 2022-12-20 에스케이하이닉스 주식회사 메모리 장치, 메모리 시스템 및 그 메모리 장치의 리프레시 방법
KR20200056731A (ko) * 2018-11-15 2020-05-25 에스케이하이닉스 주식회사 반도체장치
KR20210121660A (ko) * 2020-03-31 2021-10-08 에스케이하이닉스 주식회사 메모리 시스템 및 그것의 동작 방법
CN113495676B (zh) * 2020-04-01 2023-09-29 长鑫存储技术有限公司 读写方法及存储器装置
CN113495674B (zh) 2020-04-01 2023-10-10 长鑫存储技术有限公司 读写方法及存储器装置
CN113900580B (zh) * 2020-07-06 2024-09-27 旺宏电子股份有限公司 存储器装置、电子装置及与其相关的读取方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06111568A (ja) * 1992-09-28 1994-04-22 Sanyo Electric Co Ltd 画像メモリ装置
JP2605576B2 (ja) * 1993-04-02 1997-04-30 日本電気株式会社 同期型半導体メモリ
KR950010624B1 (ko) * 1993-07-14 1995-09-20 삼성전자주식회사 반도체 메모리장치의 셀프리프레시 주기조절회로
JPH08129882A (ja) * 1994-10-31 1996-05-21 Mitsubishi Electric Corp 半導体記憶装置
JP4000206B2 (ja) * 1996-08-29 2007-10-31 富士通株式会社 半導体記憶装置
JP3001475B2 (ja) * 1997-08-28 2000-01-24 日本電気アイシーマイコンシステム株式会社 半導体記憶装置
JP2929194B1 (ja) * 1998-01-27 1999-08-03 株式会社テーアンテー スライドスイッチ
TW463174B (en) * 1999-02-16 2001-11-11 Fujitsu Ltd Semiconductor device having test mode entry circuit

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