JP2006512776A5 - - Google Patents

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Publication number
JP2006512776A5
JP2006512776A5 JP2004565772A JP2004565772A JP2006512776A5 JP 2006512776 A5 JP2006512776 A5 JP 2006512776A5 JP 2004565772 A JP2004565772 A JP 2004565772A JP 2004565772 A JP2004565772 A JP 2004565772A JP 2006512776 A5 JP2006512776 A5 JP 2006512776A5
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JP
Japan
Prior art keywords
integrated circuit
memory
block
nand
line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2004565772A
Other languages
English (en)
Japanese (ja)
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JP2006512776A (ja
Filing date
Publication date
Priority claimed from US10/335,078 external-priority patent/US7505321B2/en
Priority claimed from US10/335,089 external-priority patent/US7005350B2/en
Application filed filed Critical
Priority claimed from PCT/US2003/041446 external-priority patent/WO2004061863A2/en
Publication of JP2006512776A publication Critical patent/JP2006512776A/ja
Publication of JP2006512776A5 publication Critical patent/JP2006512776A5/ja
Withdrawn legal-status Critical Current

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JP2004565772A 2002-12-31 2003-12-29 直列接続されたトランジスタ列を組込んだプログラマブルメモリアレイ構造およびこの構造を製造して作動させるための方法 Withdrawn JP2006512776A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/335,078 US7505321B2 (en) 2002-12-31 2002-12-31 Programmable memory array structure incorporating series-connected transistor strings and methods for fabrication and operation of same
US10/335,089 US7005350B2 (en) 2002-12-31 2002-12-31 Method for fabricating programmable memory array structures incorporating series-connected transistor strings
PCT/US2003/041446 WO2004061863A2 (en) 2002-12-31 2003-12-29 Programmable memory array structure incorporating series-connected transistor strings and methods for fabrication and operation of same

Publications (2)

Publication Number Publication Date
JP2006512776A JP2006512776A (ja) 2006-04-13
JP2006512776A5 true JP2006512776A5 (cg-RX-API-DMAC7.html) 2007-02-22

Family

ID=32716876

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004565772A Withdrawn JP2006512776A (ja) 2002-12-31 2003-12-29 直列接続されたトランジスタ列を組込んだプログラマブルメモリアレイ構造およびこの構造を製造して作動させるための方法

Country Status (3)

Country Link
JP (1) JP2006512776A (cg-RX-API-DMAC7.html)
AU (1) AU2003300007A1 (cg-RX-API-DMAC7.html)
WO (1) WO2004061863A2 (cg-RX-API-DMAC7.html)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100657910B1 (ko) * 2004-11-10 2006-12-14 삼성전자주식회사 멀티비트 플래시 메모리 소자, 그 동작 방법, 및 그 제조방법
DE102005017072A1 (de) * 2004-12-29 2006-07-13 Hynix Semiconductor Inc., Ichon Ladungsfalle- bzw. Ladung-Trap-Isolator-Speichereinrichtung
US7473589B2 (en) * 2005-12-09 2009-01-06 Macronix International Co., Ltd. Stacked thin film transistor, non-volatile memory devices and methods for fabricating the same
US7709334B2 (en) * 2005-12-09 2010-05-04 Macronix International Co., Ltd. Stacked non-volatile memory device and methods for fabricating the same
US7317641B2 (en) 2005-06-20 2008-01-08 Sandisk Corporation Volatile memory cell two-pass writing method
US7764549B2 (en) 2005-06-20 2010-07-27 Sandisk 3D Llc Floating body memory cell system and method of manufacture
US7489546B2 (en) 2005-12-20 2009-02-10 Micron Technology, Inc. NAND architecture memory devices and operation
US8759915B2 (en) 2006-03-20 2014-06-24 Micron Technology, Inc. Semiconductor field-effect transistor, memory cell and memory device
KR100806339B1 (ko) * 2006-10-11 2008-02-27 삼성전자주식회사 3차원적으로 배열된 메모리 셀들을 구비하는 낸드 플래시메모리 장치 및 그 제조 방법
US7675783B2 (en) * 2007-02-27 2010-03-09 Samsung Electronics Co., Ltd. Nonvolatile memory device and driving method thereof
JP5175526B2 (ja) * 2007-11-22 2013-04-03 株式会社東芝 不揮発性半導体記憶装置及びその製造方法
JP5288933B2 (ja) * 2008-08-08 2013-09-11 株式会社東芝 半導体記憶装置及びその製造方法
JP5322533B2 (ja) 2008-08-13 2013-10-23 株式会社東芝 不揮発性半導体記憶装置、及びその製造方法
JP4945609B2 (ja) 2009-09-02 2012-06-06 株式会社東芝 半導体集積回路装置
KR101547328B1 (ko) * 2009-09-25 2015-08-25 삼성전자주식회사 강유전체 메모리 소자 및 그 동작 방법
JP5395738B2 (ja) * 2010-05-17 2014-01-22 株式会社東芝 半導体装置
US8755227B2 (en) * 2012-01-30 2014-06-17 Phison Electronics Corp. NAND flash memory unit, NAND flash memory array, and methods for operating them
JP2013161878A (ja) * 2012-02-02 2013-08-19 Renesas Electronics Corp 半導体装置、および半導体装置の製造方法
US11729989B2 (en) * 2020-01-06 2023-08-15 Iu-Meng Tom Ho Depletion mode ferroelectric transistors
JP2021141283A (ja) 2020-03-09 2021-09-16 キオクシア株式会社 半導体記憶装置
CN112470225B (zh) * 2020-10-23 2022-12-09 长江先进存储产业创新中心有限责任公司 用以提高2堆叠体3d pcm存储器的数据吞吐量的编程和读取偏置和访问方案

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5680347A (en) * 1994-06-29 1997-10-21 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device
AU7475196A (en) * 1995-10-25 1997-05-15 Nvx Corporation Semiconductor non-volatile memory device having a nand cell structure
KR100206709B1 (ko) * 1996-09-21 1999-07-01 윤종용 멀티비트 불휘발성 반도체 메모리의 셀 어레이의 구조 및 그의 구동방법
US6888750B2 (en) * 2000-04-28 2005-05-03 Matrix Semiconductor, Inc. Nonvolatile memory on SOI and compound semiconductor substrates and method of fabrication

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