AU2003300007A1 - Programmable memory array structure incorporating series-connected transistor strings and methods for fabrication and operation of same - Google Patents

Programmable memory array structure incorporating series-connected transistor strings and methods for fabrication and operation of same

Info

Publication number
AU2003300007A1
AU2003300007A1 AU2003300007A AU2003300007A AU2003300007A1 AU 2003300007 A1 AU2003300007 A1 AU 2003300007A1 AU 2003300007 A AU2003300007 A AU 2003300007A AU 2003300007 A AU2003300007 A AU 2003300007A AU 2003300007 A1 AU2003300007 A1 AU 2003300007A1
Authority
AU
Australia
Prior art keywords
fabrication
methods
memory array
same
array structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2003300007A
Other languages
English (en)
Other versions
AU2003300007A8 (en
Inventor
En-Hsing Chen
Luca G. Fasoli
Alper Ilkbahar
Igor Kouznetsov
Sucheta Nallamothu
Christopher Petti
Roy E. Scheuerlein
Andrew J. Walker
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SanDisk 3D LLC
Original Assignee
Matrix Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US10/335,089 external-priority patent/US7005350B2/en
Priority claimed from US10/335,078 external-priority patent/US7505321B2/en
Application filed by Matrix Semiconductor Inc filed Critical Matrix Semiconductor Inc
Publication of AU2003300007A1 publication Critical patent/AU2003300007A1/en
Publication of AU2003300007A8 publication Critical patent/AU2003300007A8/xx
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Thin Film Transistor (AREA)
AU2003300007A 2002-12-31 2003-12-29 Programmable memory array structure incorporating series-connected transistor strings and methods for fabrication and operation of same Abandoned AU2003300007A1 (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US10/335,089 US7005350B2 (en) 2002-12-31 2002-12-31 Method for fabricating programmable memory array structures incorporating series-connected transistor strings
US10/335,078 US7505321B2 (en) 2002-12-31 2002-12-31 Programmable memory array structure incorporating series-connected transistor strings and methods for fabrication and operation of same
US10/335,089 2002-12-31
US10/335,078 2002-12-31
PCT/US2003/041446 WO2004061863A2 (en) 2002-12-31 2003-12-29 Programmable memory array structure incorporating series-connected transistor strings and methods for fabrication and operation of same

Publications (2)

Publication Number Publication Date
AU2003300007A1 true AU2003300007A1 (en) 2004-07-29
AU2003300007A8 AU2003300007A8 (en) 2004-07-29

Family

ID=32716876

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2003300007A Abandoned AU2003300007A1 (en) 2002-12-31 2003-12-29 Programmable memory array structure incorporating series-connected transistor strings and methods for fabrication and operation of same

Country Status (3)

Country Link
JP (1) JP2006512776A (cg-RX-API-DMAC7.html)
AU (1) AU2003300007A1 (cg-RX-API-DMAC7.html)
WO (1) WO2004061863A2 (cg-RX-API-DMAC7.html)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100657910B1 (ko) * 2004-11-10 2006-12-14 삼성전자주식회사 멀티비트 플래시 메모리 소자, 그 동작 방법, 및 그 제조방법
DE102005017072A1 (de) * 2004-12-29 2006-07-13 Hynix Semiconductor Inc., Ichon Ladungsfalle- bzw. Ladung-Trap-Isolator-Speichereinrichtung
US7473589B2 (en) * 2005-12-09 2009-01-06 Macronix International Co., Ltd. Stacked thin film transistor, non-volatile memory devices and methods for fabricating the same
US7709334B2 (en) * 2005-12-09 2010-05-04 Macronix International Co., Ltd. Stacked non-volatile memory device and methods for fabricating the same
US7317641B2 (en) 2005-06-20 2008-01-08 Sandisk Corporation Volatile memory cell two-pass writing method
US7764549B2 (en) 2005-06-20 2010-07-27 Sandisk 3D Llc Floating body memory cell system and method of manufacture
US7489546B2 (en) 2005-12-20 2009-02-10 Micron Technology, Inc. NAND architecture memory devices and operation
US8759915B2 (en) 2006-03-20 2014-06-24 Micron Technology, Inc. Semiconductor field-effect transistor, memory cell and memory device
KR100806339B1 (ko) * 2006-10-11 2008-02-27 삼성전자주식회사 3차원적으로 배열된 메모리 셀들을 구비하는 낸드 플래시메모리 장치 및 그 제조 방법
US7675783B2 (en) * 2007-02-27 2010-03-09 Samsung Electronics Co., Ltd. Nonvolatile memory device and driving method thereof
JP5175526B2 (ja) * 2007-11-22 2013-04-03 株式会社東芝 不揮発性半導体記憶装置及びその製造方法
JP5288933B2 (ja) * 2008-08-08 2013-09-11 株式会社東芝 半導体記憶装置及びその製造方法
JP5322533B2 (ja) 2008-08-13 2013-10-23 株式会社東芝 不揮発性半導体記憶装置、及びその製造方法
JP4945609B2 (ja) * 2009-09-02 2012-06-06 株式会社東芝 半導体集積回路装置
KR101547328B1 (ko) * 2009-09-25 2015-08-25 삼성전자주식회사 강유전체 메모리 소자 및 그 동작 방법
JP5395738B2 (ja) * 2010-05-17 2014-01-22 株式会社東芝 半導体装置
US8755227B2 (en) 2012-01-30 2014-06-17 Phison Electronics Corp. NAND flash memory unit, NAND flash memory array, and methods for operating them
JP2013161878A (ja) * 2012-02-02 2013-08-19 Renesas Electronics Corp 半導体装置、および半導体装置の製造方法
US11729989B2 (en) * 2020-01-06 2023-08-15 Iu-Meng Tom Ho Depletion mode ferroelectric transistors
JP2021141283A (ja) 2020-03-09 2021-09-16 キオクシア株式会社 半導体記憶装置
WO2022082732A1 (en) * 2020-10-23 2022-04-28 Yangtze Advanced Memory Industrial Innovation Center Co., Ltd. A program and read bias and access scheme to improve data throughput for 2 stack 3d pcm memory

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5680347A (en) * 1994-06-29 1997-10-21 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device
WO1997015929A1 (en) * 1995-10-25 1997-05-01 Nvx Corporation Semiconductor non-volatile memory device having a nand cell structure
KR100206709B1 (ko) * 1996-09-21 1999-07-01 윤종용 멀티비트 불휘발성 반도체 메모리의 셀 어레이의 구조 및 그의 구동방법
US6888750B2 (en) * 2000-04-28 2005-05-03 Matrix Semiconductor, Inc. Nonvolatile memory on SOI and compound semiconductor substrates and method of fabrication

Also Published As

Publication number Publication date
WO2004061863A3 (en) 2004-12-16
AU2003300007A8 (en) 2004-07-29
WO2004061863A2 (en) 2004-07-22
JP2006512776A (ja) 2006-04-13

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase