JP2006506806A - ハイブリッド誘電体を備えた高信頼低誘電率相互接続構造 - Google Patents

ハイブリッド誘電体を備えた高信頼低誘電率相互接続構造 Download PDF

Info

Publication number
JP2006506806A
JP2006506806A JP2004550790A JP2004550790A JP2006506806A JP 2006506806 A JP2006506806 A JP 2006506806A JP 2004550790 A JP2004550790 A JP 2004550790A JP 2004550790 A JP2004550790 A JP 2004550790A JP 2006506806 A JP2006506806 A JP 2006506806A
Authority
JP
Japan
Prior art keywords
layer
dielectric layer
hard mask
dielectric
interconnect structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2004550790A
Other languages
English (en)
Japanese (ja)
Other versions
JP2006506806A5 (enExample
Inventor
フッツシモンズ、ジョン
グレコ、ステファン
リー、ジア
ゲイツ、ステファン
スプーナー、テリー
アングヤル、マシュー
ヒクリ、ハビブ
スタンダート、セオドラス
ビリー、グレン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JP2006506806A publication Critical patent/JP2006506806A/ja
Publication of JP2006506806A5 publication Critical patent/JP2006506806A5/ja
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76832—Multiple layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76835—Combinations of two or more different dielectric layers having a low dielectric constant
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H01L23/53295—Stacked insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)
JP2004550790A 2002-11-14 2003-11-07 ハイブリッド誘電体を備えた高信頼低誘電率相互接続構造 Pending JP2006506806A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/294,139 US6917108B2 (en) 2002-11-14 2002-11-14 Reliable low-k interconnect structure with hybrid dielectric
PCT/GB2003/004814 WO2004044978A1 (en) 2002-11-14 2003-11-07 Reliable low-k interconnect structure with hybrid dielectric

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2010247790A Division JP2011061228A (ja) 2002-11-14 2010-11-04 ハイブリッド誘電体を備えた高信頼低誘電率相互接続構造

Publications (2)

Publication Number Publication Date
JP2006506806A true JP2006506806A (ja) 2006-02-23
JP2006506806A5 JP2006506806A5 (enExample) 2006-12-07

Family

ID=32296906

Family Applications (2)

Application Number Title Priority Date Filing Date
JP2004550790A Pending JP2006506806A (ja) 2002-11-14 2003-11-07 ハイブリッド誘電体を備えた高信頼低誘電率相互接続構造
JP2010247790A Pending JP2011061228A (ja) 2002-11-14 2010-11-04 ハイブリッド誘電体を備えた高信頼低誘電率相互接続構造

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP2010247790A Pending JP2011061228A (ja) 2002-11-14 2010-11-04 ハイブリッド誘電体を備えた高信頼低誘電率相互接続構造

Country Status (8)

Country Link
US (2) US6917108B2 (enExample)
EP (1) EP1561241A1 (enExample)
JP (2) JP2006506806A (enExample)
KR (1) KR100773003B1 (enExample)
CN (1) CN1314101C (enExample)
AU (1) AU2003279460A1 (enExample)
TW (1) TWI234231B (enExample)
WO (1) WO2004044978A1 (enExample)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010267971A (ja) * 2009-05-13 2010-11-25 Air Products & Chemicals Inc 窒素含有前駆物質を用いる誘電体バリアの堆積
JP2012190900A (ja) * 2011-03-09 2012-10-04 Sony Corp 半導体装置及びその製造方法
US11384429B2 (en) 2008-04-29 2022-07-12 Applied Materials, Inc. Selective cobalt deposition on copper surfaces

Families Citing this family (47)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7425346B2 (en) * 2001-02-26 2008-09-16 Dielectric Systems, Inc. Method for making hybrid dielectric film
JP2004146798A (ja) * 2002-09-30 2004-05-20 Sanyo Electric Co Ltd 半導体装置およびその製造方法
JP3898133B2 (ja) * 2003-01-14 2007-03-28 Ｎｅｃエレクトロニクス株式会社 ＳｉＣＨＮ膜の成膜方法。
JP3715626B2 (ja) * 2003-01-17 2005-11-09 株式会社東芝 半導体装置の製造方法および半導体装置
JP4086673B2 (ja) * 2003-02-04 2008-05-14 Ｎｅｃエレクトロニクス株式会社 半導体装置及びその製造方法
US7081673B2 (en) * 2003-04-17 2006-07-25 International Business Machines Corporation Multilayered cap barrier in microelectronic interconnect structures
US6919636B1 (en) * 2003-07-31 2005-07-19 Advanced Micro Devices, Inc. Interconnects with a dielectric sealant layer
US7199046B2 (en) * 2003-11-14 2007-04-03 Tokyo Electron Ltd. Structure comprising tunable anti-reflective coating and method of forming thereof
US20050130407A1 (en) * 2003-12-12 2005-06-16 Jui-Neng Tu Dual damascene process for forming a multi-layer low-k dielectric interconnect
US7224068B2 (en) * 2004-04-06 2007-05-29 Taiwan Semiconductor Manufacturing Company, Ltd. Stable metal structure with tungsten plug
US20060012014A1 (en) * 2004-07-15 2006-01-19 International Business Machines Corporation Reliability of low-k dielectric devices with energy dissipative layer
US20060027924A1 (en) * 2004-08-03 2006-02-09 Taiwan Semiconductor Manufacturing Co., Ltd. Metallization layers for crack prevention and reduced capacitance
US6974772B1 (en) * 2004-08-19 2005-12-13 Intel Corporation Integrated low-k hard mask
US7348672B2 (en) * 2005-07-07 2008-03-25 Taiwan Semiconductor Manufacturing Co., Ltd. Interconnects with improved reliability
US7341941B2 (en) * 2005-08-19 2008-03-11 Texas Instruments Incorporated Methods to facilitate etch uniformity and selectivity
US7394154B2 (en) * 2005-09-13 2008-07-01 International Business Machines Corporation Embedded barrier for dielectric encapsulation
US20070059922A1 (en) * 2005-09-13 2007-03-15 International Business Machines Corporation Post-etch removal of fluorocarbon-based residues from a hybrid dielectric structure
BRPI0618247A2 (pt) * 2005-11-03 2011-08-23 Redpoint Bio Corp ensaio de triagem de alto rendimento para canal iÈnico trpm5
US20070155186A1 (en) * 2005-11-22 2007-07-05 International Business Machines Corporation OPTIMIZED SiCN CAPPING LAYER
US7338893B2 (en) * 2005-11-23 2008-03-04 Texas Instruments Incorporated Integration of pore sealing liner into dual-damascene methods and devices
US7358182B2 (en) * 2005-12-22 2008-04-15 International Business Machines Corporation Method of forming an interconnect structure
US20070152332A1 (en) * 2006-01-04 2007-07-05 International Business Machines Corporation Single or dual damascene via level wirings and/or devices, and methods of fabricating same
US7473636B2 (en) * 2006-01-12 2009-01-06 International Business Machines Corporation Method to improve time dependent dielectric breakdown
US20070278682A1 (en) * 2006-05-31 2007-12-06 Chung-Chi Ko Self-assembled mono-layer liner for cu/porous low-k interconnections
US7727885B2 (en) * 2006-08-29 2010-06-01 Texas Instruments Incorporated Reduction of punch-thru defects in damascene processing
US7466027B2 (en) * 2006-09-13 2008-12-16 Taiwan Semiconductor Manufacturing Co., Ltd. Interconnect structures with surfaces roughness improving liner and methods for fabricating the same
US7749894B2 (en) * 2006-11-09 2010-07-06 Chartered Semiconductor Manufacturing Ltd. Integrated circuit processing system
US7723226B2 (en) * 2007-01-17 2010-05-25 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnects containing bilayer porous low-k dielectrics using different porogen to structure former ratio
US7947565B2 (en) 2007-02-07 2011-05-24 United Microelectronics Corp. Forming method of porous low-k layer and interconnect process
US7485949B2 (en) * 2007-05-02 2009-02-03 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device
US7718525B2 (en) 2007-06-29 2010-05-18 International Business Machines Corporation Metal interconnect forming methods and IC chip including metal interconnect
US20090032491A1 (en) * 2007-08-03 2009-02-05 International Business Machines Corporation Conductive element forming using sacrificial layer patterned to form dielectric layer
US20090176367A1 (en) * 2008-01-08 2009-07-09 Heidi Baks OPTIMIZED SiCN CAPPING LAYER
US8212337B2 (en) 2008-01-10 2012-07-03 International Business Machines Corporation Advanced low k cap film formation process for nano electronic devices
US7863176B2 (en) * 2008-05-13 2011-01-04 Micron Technology, Inc. Low-resistance interconnects and methods of making same
JP2010003894A (ja) * 2008-06-20 2010-01-07 Nec Electronics Corp 半導体装置の製造方法及び半導体装置
US8189292B2 (en) * 2008-12-24 2012-05-29 Hitachi Global Storage Technologies Netherlands B.V. Method for manufacturing a magnetic write head having a write pole with a trailing edge taper using a Rieable hard mask
US8836127B2 (en) * 2009-11-19 2014-09-16 Taiwan Semiconductor Manufacturing Co., Ltd. Interconnect with flexible dielectric layer
US8461683B2 (en) * 2011-04-01 2013-06-11 Intel Corporation Self-forming, self-aligned barriers for back-end interconnects and methods of making same
US8980740B2 (en) 2013-03-06 2015-03-17 Globalfoundries Inc. Barrier layer conformality in copper interconnects
US9385086B2 (en) * 2013-12-10 2016-07-05 Taiwan Semiconductor Manufacturing Co., Ltd. Bi-layer hard mask for robust metallization profile
US20170092753A1 (en) 2015-09-29 2017-03-30 Infineon Technologies Austria Ag Water and Ion Barrier for III-V Semiconductor Devices
US9905456B1 (en) * 2016-09-26 2018-02-27 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US10256191B2 (en) 2017-01-23 2019-04-09 International Business Machines Corporation Hybrid dielectric scheme for varying liner thickness and manganese concentration
US11217481B2 (en) * 2019-11-08 2022-01-04 International Business Machines Corporation Fully aligned top vias
US11244854B2 (en) 2020-03-24 2022-02-08 International Business Machines Corporation Dual damascene fully aligned via in interconnects
KR102881251B1 (ko) 2021-01-11 2025-11-04 삼성전자주식회사 반도체 장치 및 이의 제조 방법

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000079586A1 (en) * 1999-06-24 2000-12-28 Hitachi, Ltd. Production method for semiconductor integrated circuit device and semiconductor integrated circuit device
JP2001284454A (ja) * 2000-02-29 2001-10-12 Internatl Business Mach Corp <Ibm> マルチレベル共面相互接続構造
US20020164889A1 (en) * 2001-05-02 2002-11-07 Cheng-Yuan Tsai Method for improving adhesion of low k materials with adjacent layer

Family Cites Families (43)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6265780B1 (en) 1998-12-01 2001-07-24 United Microelectronics Corp. Dual damascene structure for the wiring-line structures of multi-level interconnects in integrated circuit
US6245662B1 (en) 1998-07-23 2001-06-12 Applied Materials, Inc. Method of producing an interconnect structure for an integrated circuit
US6265779B1 (en) * 1998-08-11 2001-07-24 International Business Machines Corporation Method and material for integration of fuorine-containing low-k dielectrics
JP2000150516A (ja) 1998-09-02 2000-05-30 Tokyo Electron Ltd 半導体装置の製造方法
US6159842A (en) 1999-01-11 2000-12-12 Taiwan Semiconductor Manufacturing Company Method for fabricating a hybrid low-dielectric-constant intermetal dielectric (IMD) layer with improved reliability for multilevel interconnections
US6187663B1 (en) 1999-01-19 2001-02-13 Taiwan Semiconductor Manufacturing Company Method of optimizing device performance via use of copper damascene structures, and HSQ/FSG, hybrid low dielectric constant materials
US6380091B1 (en) 1999-01-27 2002-04-30 Advanced Micro Devices, Inc. Dual damascene arrangement for metal interconnection with oxide dielectric layer and low K dielectric constant layer
US6312793B1 (en) * 1999-05-26 2001-11-06 International Business Machines Corporation Multiphase low dielectric constant material
US6770975B2 (en) 1999-06-09 2004-08-03 Alliedsignal Inc. Integrated circuits with multiple low dielectric-constant inter-metal dielectrics
US6319814B1 (en) * 1999-10-12 2001-11-20 United Microelectronics Corp. Method of fabricating dual damascene
US6406994B1 (en) 1999-12-03 2002-06-18 Chartered Semiconductor Manufacturing Ltd. Triple-layered low dielectric constant dielectric dual damascene approach
FR2802336B1 (fr) * 1999-12-13 2002-03-01 St Microelectronics Sa Structure d'interconnexions de type damascene et son procede de realisation
US6362091B1 (en) 2000-03-14 2002-03-26 Intel Corporation Method for making a semiconductor device having a low-k dielectric layer
US6440878B1 (en) * 2000-04-03 2002-08-27 Sharp Laboratories Of America, Inc. Method to enhance the adhesion of silicon nitride to low-k fluorinated amorphous carbon using a silicon carbide adhesion promoter layer
JP2001338978A (ja) 2000-05-25 2001-12-07 Hitachi Ltd 半導体装置及びその製造方法
US6358842B1 (en) 2000-08-07 2002-03-19 Chartered Semiconductor Manufacturing Ltd. Method to form damascene interconnects with sidewall passivation to protect organic dielectrics
US7115531B2 (en) 2000-08-21 2006-10-03 Dow Global Technologies Inc. Organosilicate resins as hardmasks for organic polymer dielectrics in fabrication of microelectronic devices
US6451683B1 (en) 2000-08-28 2002-09-17 Micron Technology, Inc. Damascene structure and method of making
US6395632B1 (en) 2000-08-31 2002-05-28 Micron Technology, Inc. Etch stop in damascene interconnect structure and method of making
US6472306B1 (en) 2000-09-05 2002-10-29 Industrial Technology Research Institute Method of forming a dual damascene opening using CVD Low-K material and spin-on-polymer
US6380084B1 (en) * 2000-10-02 2002-04-30 Chartered Semiconductor Manufacturing Inc. Method to form high performance copper damascene interconnects by de-coupling via and metal line filling
SG137694A1 (en) * 2000-10-25 2007-12-28 Ibm Ultralow dielectric constant material as an intralevel or interlevel dieletric in a semiconductor device and electronic device containing the same
TW468241B (en) * 2000-11-14 2001-12-11 United Microelectronics Corp Method to improve adhesion of dielectric material of semiconductor
JP2002164428A (ja) * 2000-11-29 2002-06-07 Hitachi Ltd 半導体装置およびその製造方法
US6451712B1 (en) * 2000-12-18 2002-09-17 International Business Machines Corporation Method for forming a porous dielectric material layer in a semiconductor device and device formed
WO2002054484A2 (en) * 2001-01-03 2002-07-11 Dow Corning Corporation Metal ion diffusion barrier layers
US6383920B1 (en) 2001-01-10 2002-05-07 International Business Machines Corporation Process of enclosing via for improved reliability in dual damascene interconnects
US6710450B2 (en) * 2001-02-28 2004-03-23 International Business Machines Corporation Interconnect structure with precise conductor resistance and method to form same
US6677680B2 (en) 2001-02-28 2004-01-13 International Business Machines Corporation Hybrid low-k interconnect structure comprised of 2 spin-on dielectric materials
US6603204B2 (en) 2001-02-28 2003-08-05 International Business Machines Corporation Low-k interconnect structure comprised of a multilayer of spin-on porous dielectrics
CN1503704A (zh) 2001-04-16 2004-06-09 霍尼韦尔国际公司 分层堆栈及其生产方法
KR100416596B1 (ko) * 2001-05-10 2004-02-05 삼성전자주식회사 반도체 소자의 연결 배선 형성 방법
US6391757B1 (en) 2001-06-06 2002-05-21 United Microelectronics Corp. Dual damascene process
US6798043B2 (en) 2001-06-28 2004-09-28 Agere Systems, Inc. Structure and method for isolating porous low-k dielectric films
US6879046B2 (en) * 2001-06-28 2005-04-12 Agere Systems Inc. Split barrier layer including nitrogen-containing portion and oxygen-containing portion
JP4152619B2 (ja) * 2001-11-14 2008-09-17 株式会社ルネサステクノロジ 半導体装置およびその製造方法
US20030134499A1 (en) * 2002-01-15 2003-07-17 International Business Machines Corporation Bilayer HDP CVD / PE CVD cap in advanced BEOL interconnect structures and method thereof
US6806203B2 (en) * 2002-03-18 2004-10-19 Applied Materials Inc. Method of forming a dual damascene structure using an amorphous silicon hard mask
JP4340040B2 (ja) * 2002-03-28 2009-10-07 富士通マイクロエレクトロニクス株式会社 半導体装置の製造方法
JP3657921B2 (ja) * 2002-04-26 2005-06-08 株式会社東芝 半導体装置とその製造方法
US6764774B2 (en) * 2002-06-19 2004-07-20 International Business Machines Corporation Structures with improved adhesion to Si and C containing dielectrics and method for preparing the same
US6867125B2 (en) * 2002-09-26 2005-03-15 Intel Corporation Creating air gap in multi-level metal interconnects using electron beam to remove sacrificial material
US7023093B2 (en) * 2002-10-24 2006-04-04 International Business Machines Corporation Very low effective dielectric constant interconnect Structures and methods for fabricating the same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000079586A1 (en) * 1999-06-24 2000-12-28 Hitachi, Ltd. Production method for semiconductor integrated circuit device and semiconductor integrated circuit device
JP2001284454A (ja) * 2000-02-29 2001-10-12 Internatl Business Mach Corp <Ibm> マルチレベル共面相互接続構造
US20020164889A1 (en) * 2001-05-02 2002-11-07 Cheng-Yuan Tsai Method for improving adhesion of low k materials with adjacent layer

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11384429B2 (en) 2008-04-29 2022-07-12 Applied Materials, Inc. Selective cobalt deposition on copper surfaces
US11959167B2 (en) 2008-04-29 2024-04-16 Applied Materials, Inc. Selective cobalt deposition on copper surfaces
JP2010267971A (ja) * 2009-05-13 2010-11-25 Air Products & Chemicals Inc 窒素含有前駆物質を用いる誘電体バリアの堆積
JP2012190900A (ja) * 2011-03-09 2012-10-04 Sony Corp 半導体装置及びその製造方法

Also Published As

Publication number Publication date
TW200419714A (en) 2004-10-01
KR20050074996A (ko) 2005-07-19
WO2004044978A1 (en) 2004-05-27
AU2003279460A1 (en) 2004-06-03
US20040094839A1 (en) 2004-05-20
EP1561241A1 (en) 2005-08-10
US6917108B2 (en) 2005-07-12
CN1711635A (zh) 2005-12-21
TWI234231B (en) 2005-06-11
KR100773003B1 (ko) 2007-11-05
US20050023693A1 (en) 2005-02-03
JP2011061228A (ja) 2011-03-24
US7135398B2 (en) 2006-11-14
CN1314101C (zh) 2007-05-02

Similar Documents

Publication Publication Date Title
JP2006506806A (ja) ハイブリッド誘電体を備えた高信頼低誘電率相互接続構造
US6939797B2 (en) Advanced BEOL interconnect structures with low-k PE CVD cap layer and method thereof
CN100461352C (zh) 互连结构及其形成方法
US7541276B2 (en) Methods for forming dual damascene wiring for semiconductor devices using protective via capping layer
US7259090B2 (en) Copper damascene integration scheme for improved barrier layers
CN100399542C (zh) 内连线结构及其形成方法
JP2004146800A (ja) 相互接続構造の製造方法およびその構造
US9870944B2 (en) Back-end-of-line (BEOL) interconnect structure
JP2003045969A (ja) デュアルダマシン工程を利用した配線形成方法
US6927113B1 (en) Semiconductor component and method of manufacture
JP5400355B2 (ja) 半導体装置
US6774031B2 (en) Method of forming dual-damascene structure
US20080251929A1 (en) Semiconductor Device and Semiconductor Device Manufacturing Method
JP4558272B2 (ja) 低誘電率技術における銅バイア用のクロム接着層
US20060118955A1 (en) Robust copper interconnection structure and fabrication method thereof
KR100562630B1 (ko) 집적 회로에서의 구리 상호 접속부 형성 방법
US20070222076A1 (en) Single or dual damascene structure reducing or eliminating the formation of micro-trenches arising from lithographic misalignment
JP5047504B2 (ja) ビアキャッピング保護膜を使用する半導体素子のデュアルダマシン配線の製造方法
US20060110912A1 (en) Semiconductor devices with composite etch stop layers and methods of fabrication thereof

Legal Events

Date Code Title Description
A529 Written submission of copy of amendment under article 34 pct

Free format text: JAPANESE INTERMEDIATE CODE: A529

Effective date: 20050713

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20061023

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20061023

RD03 Notification of appointment of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7423

Effective date: 20090206

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20090914

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20100803

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20110111