JP2006505948A - ワン・トランジスタdramセル構造および製造方法 - Google Patents
ワン・トランジスタdramセル構造および製造方法 Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 210000000746 body region Anatomy 0.000 claims description 37
- 239000012212 insulator Substances 0.000 claims description 23
- 239000004065 semiconductor Substances 0.000 claims description 21
- 125000001475 halogen functional group Chemical group 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 abstract description 3
- 230000006870 function Effects 0.000 abstract description 2
- 238000002513 implantation Methods 0.000 description 37
- 239000007943 implant Substances 0.000 description 11
- 230000008901 benefit Effects 0.000 description 8
- 238000000034 method Methods 0.000 description 8
- 125000006850 spacer group Chemical group 0.000 description 7
- 239000000463 material Substances 0.000 description 4
- 229910052698 phosphorus Inorganic materials 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 150000002290 germanium Chemical class 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
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Abstract
Description
。最も一般的には、ゲート誘電体は熱成長酸化物である。本体16は半導体材料であり、現在最も一般的にはシリコンである。N型のドーパントは、典型的にはリンまたはヒ素である。
プ領域40を通じて生じるPN接合のターン・オン電圧に到達しないように選択される。したがって、衝突電離によって起こる電子/正孔対形成の間、正孔を捕集するためのダイオード電流が低く保持される。
6の中に延びることによって、領域76よりさらに先のゲート62の下に延びる。
Claims (6)
- 第1のドレイン/ソース領域と、第2のドレイン/ソース領域と、前記第1のドレイン/ソース領域および前記第2のドレイン/ソース領域の間の本体領域と、前記本体領域の上方のゲートとを有するトランジスタを有し、
前記本体領域に隣接する前記第1のドレイン/ソース領域の一部分のドーピング濃度は、前記本体領域に隣接する前記第2のドレイン/ソース領域の一部分のドーピング濃度と異なる、
ワン・トランジスタ・ダイナミック・ランダム・アクセス・メモリ(DRAM)・セル。 - 第1のドレイン/ソース領域と、第2のドレイン/ソース領域と、前記第1のドレイン/ソース領域および前記第2のドレイン/ソース領域の間の本体領域と、前記本体領域の上方のゲートとを有するトランジスタを有し、
前記第1のドレイン/ソース領域に直に隣接する前記本体領域の一区域のドーピング濃度は、前記第2のドレイン/ソース領域に直に隣接する前記本体領域の一区域と異なるドーピング濃度を有する、
ワン・トランジスタ・ダイナミック・ランダム・アクセス・メモリ(DRAM)・セル。 - 第1のドレイン/ソース領域と、第2のドレイン/ソース領域と、前記第1のドレイン/ソース領域および前記第2のドレイン/ソース領域の間の本体領域と、前記本体領域の上方のゲートとを有するトランジスタを有し、
前記第1のドレイン/ソース領域に直に隣接する前記本体領域の第1の区域のドーピング濃度は、前記第2のドレイン/ソース領域に直に隣接する前記本体領域の第2の区域と異なるドーピング濃度を有し、
前記本体領域に隣接する前記第1のドレイン/ソース領域の一部分のドーピング濃度は、前記本体領域に隣接する前記第2のドレイン/ソース領域の一部分のドーピング濃度と異なる、
ワン・トランジスタ・ダイナミック・ランダム・アクセス・メモリ(DRAM)・セル。 - ワン・トランジスタ・ダイナミック・ランダム・アクセス・メモリ(DRAM)・セルの製造方法であって、
基板上に形成された絶縁体と前記絶縁体上に形成された半導体層とを有するシリコン・オン・インシュレータ(SOI)半導体デバイスを設けるステップと、
前記半導体層に前記メモリ・セルの本体領域を形成するステップと、
前記本体領域の上方にゲートを形成するステップと、
前記本体領域に隣接する前記半導体層にて前記本体領域に対向する側に第1のドレイン/ソース領域および第2のドレイン/ソース領域を形成するステップと、
前記第1のドレイン/ソース領域に隣接する前記本体領域にハロー領域を形成するステップと、
前記ゲートの下に重なる前記第1のドレイン/ソース領域に高濃度ドープされた延長部を形成するステップと、
前記ゲートの下に重なる前記第2のドレイン/ソース領域に低濃度ドープされた延長部を形成するステップとから成る、製造方法。 - ワン・トランジスタ・ダイナミック・ランダム・アクセス・メモリ(DRAM)・セルの製造方法であって、
基板上に形成された絶縁体と前記絶縁体上に形成された半導体層とを有するシリコン・
オン・インシュレータ(SOI)半導体デバイスを設けるステップと、
前記半導体層に前記メモリ・セルの本体領域を形成するステップと、
前記本体領域の上方にゲートを形成するステップと、
前記本体領域に隣接する前記半導体層にて前記本体領域に対向する側に第1のドレイン/ソース領域および第2のドレイン/ソース領域を形成するステップと、
前記第1のドレイン/ソース領域に隣接しかつ前記ゲートに隣接する前記本体領域に第1のハロー領域を形成するステップと、
前記第2のドレイン/ソース領域に隣接しかつ前記絶縁体に隣接する前記本体領域に第2のハロー領域を形成するステップとから成る、製造方法。 - ワン・トランジスタ・ダイナミック・ランダム・アクセス・メモリ(DRAM)・セルの製造方法であって、
基板上に形成された絶縁体と前記絶縁体上に形成された半導体層とを有するシリコン・オン・インシュレータ(SOI)半導体デバイスを設けるステップであって、前記半導体層が表面を有する、設けるステップと、
前記半導体層に前記メモリ・セルの本体領域を形成するステップと、
前記本体領域の上方にて前記半導体層の前記表面の上にゲートを形成するステップと、
前記本体領域に隣接する前記半導体層にて前記本体領域に対向する側に第1のドレイン/ソース領域および第2のドレイン/ソース領域を形成するステップと、
前記第1のドレイン/ソース領域に隣接しかつ前記ゲートに隣接する前記本体領域に第1のハロー領域を形成するステップと、
前記第1のドレイン/ソース領域を高濃度ドープするステップと、
前記第2のドレイン/ソース領域の一部分を高濃度ドープするステップであって、前記部分は前記半導体層の前記表面の付近である、高濃度ドープするステップとから成る、製造方法。
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US10/290,904 US6861689B2 (en) | 2002-11-08 | 2002-11-08 | One transistor DRAM cell structure and method for forming |
PCT/US2003/026957 WO2004044990A1 (en) | 2002-11-08 | 2003-08-28 | One transistor dram cell structure and method for forming |
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JP2009021561A (ja) * | 2007-06-12 | 2009-01-29 | Semiconductor Energy Lab Co Ltd | キャパシタレスメモリ |
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EP1357603A3 (en) | 2002-04-18 | 2004-01-14 | Innovative Silicon SA | Semiconductor device |
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WO2004044990A1 (en) | 2004-05-27 |
WO2004044990A8 (en) | 2004-09-02 |
CN100546044C (zh) | 2009-09-30 |
US20040089890A1 (en) | 2004-05-13 |
JP4982046B2 (ja) | 2012-07-25 |
CN1695250A (zh) | 2005-11-09 |
TW200421605A (en) | 2004-10-16 |
AU2003260120A1 (en) | 2004-06-03 |
KR20050071665A (ko) | 2005-07-07 |
US6861689B2 (en) | 2005-03-01 |
TWI319621B (en) | 2010-01-11 |
EP1559141A1 (en) | 2005-08-03 |
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