JP2006351683A - 半導体装置および半導体装置の製造方法 - Google Patents
半導体装置および半導体装置の製造方法 Download PDFInfo
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- H01L2029/7858—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET having contacts specially adapted to the FinFET geometry, e.g. wrap-around contacts
Abstract
【解決手段】 半導体装置の製造方法は、リソグラフィで形成可能な最小ピッチ幅よりも狭いピッチ幅で配列され半導体材料から成る複数のFin50を絶縁層4上に形成し、複数のFinの側壁にゲート絶縁膜60を形成し、Finの配列方向に延び、Finとは電気的に絶縁され、かつFinに共通のゲート電極709を、ゲート絶縁膜上に形成し、ゲート電極をマスクとして用いて該ゲート電極の両側に延在するFinの部分に不純物を注入することによりソース・ドレイン層100を形成し、Finのゲート電極を挟んだ両側に絶縁膜を介して導電体材料を堆積することにより、複数のFinを接続することを具備する。
【選択図】 図7
Description
Yang-Kyu Choi et al. "A spacer Patterning Technology for Nanoscale CMOS" IEEE Transaction on Eledtron Devices, vol.49, No.3, March 2002, pp.436-441
図1から図7は、本発明に係る第1の実施形態に従ったFin型FETの製造方法の流れを示す図である。図1および図2は断面図であり、図3から図7は斜視図である。
図8および図9は、マルチSWTの流れを示す断面図である。図1、図2、図8および図9を参照して、マルチSWTを詳細に説明する。図1および図2までは第1の実施形態と同様である。ただし、図2の40は第1の側壁材料からなる第1の側壁パターンとする。第1の側壁材料は、例えば、ポリシリコン膜である。第1の側壁パターン40の形成後、さらに、第1の側壁パターン40とは異なる材料からなる第2の側壁材料を堆積する。第2の側壁材料は、例えば、約20nmの厚みのTEOS膜である。第2の側壁材料を異方的にエッチングすることによって、図8に示すように、第1の側壁パターン40のそれぞれの両側面に第2の側壁パターン130を形成する。
図10から図12は、本発明に係る第2の実施形態に従ったFin型FETの製造方法の流れを示す斜視図である。第2の実施形態は、ソース・ドレイン領域の形成工程において第1の実施形態と異なる。従って、第2の実施形態は、図5まで第1の実施形態と同様の方法で形成される。
図13は、本発明に係る実施形態に従ったFin型FETの斜視図である。第1および第2の実施形態ではSOI基板を用いていたが、第3の実施形態はバルクシリコン基板3を用いる。従って、シリコン基板3上にハードマスク用のシリコン窒化膜20を堆積する。シリコン窒化膜20に対してSWTまたはマルチSWTを適用することによって、リソグラフィで形成可能な最小ピッチ幅P0よりも狭いピッチ幅を有するハードマスクを形成する。このハードマスクを用いて、シリコン基板30をRIEでエッチングする。これにより、ピッチ幅P0よりも狭いピッチ幅を有するFin50が形成される。このとき、Fin50とFin50との間には、トレンチが形成される。このトレンチの下部にのみシリコン酸化膜5を充填する。これにより、STI(Shallow Trench Isolation)が形成される。トレンチの上部にはシリコン酸化膜が堆積されないので、図13に示すようにシリコン酸化膜5上にFin50が突出した構造になる。
図14(A)および図14(B)は、本発明に係る第4の実施形態に従ったFin型FETの斜視図である。第4の実施形態は、nMOSとpMOSとで異なる材料をゲート電極として用いている。第4の実施形態のその他の構成は、第1または第2の実施形態と同様でよい。
図15(A)および図15(B)は、本発明に係る第5の実施形態に従ったFin型FETの斜視図である。第5の実施形態は、ダマシンプロセスを用いてゲート電極にメタルゲートを採用している。第5の実施形態のその他の構成は、第2の実施形態と同様でよい。また、第5の実施形態の製造方法は、図10まで第2の実施形態の製造方法と同様でよい。
4 BOX層
6 SOI層
10 SOI基板
20 シリコン窒化膜
30 ダミーパターン
40 側壁パターン
50 Fin
60 ゲート絶縁膜
70 ゲート電極
80 ハードマスク
90 ゲート側壁膜
100 ソース・ドレイン層
110、130 ソース・ドレイン層
Claims (5)
- 半導体材料から成る複数のFinを絶縁層上に形成し、
前記複数のFinの側壁にゲート絶縁膜を形成し、
前記複数のFinの配列方向に延び、前記複数のFinとは電気的に絶縁され、かつ前記複数のFinに共通のゲート電極を、前記ゲート絶縁膜上に形成し、
少なくとも前記ゲート電極をマスクとして用いて該ゲート電極の両側に延在する前記複数のFinの各部分に不純物を注入することによりソース・ドレイン拡散層を形成し、
前記複数のFinのゲート電極を挟んだ両側に、絶縁膜を介して導電体材料を堆積することにより、前記複数のFinを接続することを具備した半導体装置の製造方法。 - 前記複数のFinを前記絶縁層上に形成するときに、
前記絶縁層上に半導体層を備えた半導体基板を準備し、
前記半導体層上に絶縁体から成るマスク材料を堆積し、
リソグラフィで形成可能な最小ピッチ幅で配列する複数のダミーパターンを前記マスク材料上に形成し、
前記ダミーパターン上に該ダミーパターンとは異なる材質の側壁材料を堆積し、
前記側壁材料を異方的にエッチングすることによって、前記ダミーパターンのそれぞれの両側面に側壁パターンを形成し、
前記側壁パターンを残存させつつ、前記ダミーパターンを選択的にエッチングし、
前記側壁パターンをマスクとして前記マスク材料をエッチングし、
前記マスク材料をマスクとして前記半導体層をエッチングすることによって前記複数のFinを形成することを特徴とする請求項1に記載の半導体装置の製造方法。 - 前記複数のFinを前記絶縁層上に形成するときに、
前記絶縁層上に半導体層を備えた半導体基板を準備し、
前記半導体層上に絶縁体から成るマスク材料を堆積し、
リソグラフィで形成可能な最小ピッチ幅で配列する複数のダミーパターンを前記マスク材料上に形成し、
前記ダミーパターン上に該ダミーパターンとは異なる材料からなる第1の側壁材料を堆積し、
前記第1の側壁材料を異方的にエッチングすることによって、前記ダミーパターンのそれぞれの両側面に第1の側壁パターンを形成し、
前記第1の側壁パターンを残存させつつ、前記ダミーパターンを選択的にエッチングし、
前記第1の側壁パターン上に前記第1の側壁材料とは異なる材料からなる第2の側壁材料を堆積し、
前記第2の側壁材料を異方的にエッチングすることによって、前記第1の側壁パターンのそれぞれの両側面に第2の側壁パターンを形成し、
前記第2の側壁パターンを残存させつつ、前記第1の側壁パターンを選択的にエッチングし、
前記第2の側壁パターンをマスクとして前記マスク材料をエッチングし、
前記マスク材料をマスクとして前記半導体層をエッチングすることによって前記複数のFinを形成することを特徴とする請求項1に記載の半導体装置の製造方法。 - 絶縁層と、
リソグラフィで形成可能な最小ピッチ幅よりも狭いピッチ幅で前記絶縁層上に配列され、半導体材料から成る複数のFinと、
前記複数のFinの側壁に設けられたゲート絶縁膜と、
前記複数のFinの配列方向に延び、前記複数のFinとは電気的に絶縁され、かつ前記複数のFinに共通のゲート電極と、
前記ゲート電極を挟んで両側にある前記複数のFinの部分に設けられたソース・ドレイン層と、
前記複数のFinの前記ソース・ドレイン層の上面または側面に接し、前記Fin同士を接続する金属または金属シリサイドを具備した半導体装置。 - 前記複数のFinのピッチ幅は、前記リソグラフィで形成可能な最小ピッチ幅の1/2、1/4、1/8・・・1/2n(nは自然数)のいずれかであることを特徴とする請求項4に記載の半導体装置。
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JP2005173606A JP4718908B2 (ja) | 2005-06-14 | 2005-06-14 | 半導体装置および半導体装置の製造方法 |
US11/451,318 US7608890B2 (en) | 2005-06-14 | 2006-06-13 | Semiconductor device and method of manufacturing semiconductor device |
US12/585,554 US8138031B2 (en) | 2005-06-14 | 2009-09-17 | Semiconductor device and method of manufacturing semiconductor device |
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US20070004117A1 (en) | 2007-01-04 |
US20100081240A1 (en) | 2010-04-01 |
US8138031B2 (en) | 2012-03-20 |
US7608890B2 (en) | 2009-10-27 |
JP4718908B2 (ja) | 2011-07-06 |
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