JP2006344896A - Lsiパッケージ及び回路基板 - Google Patents
Lsiパッケージ及び回路基板 Download PDFInfo
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- JP2006344896A JP2006344896A JP2005171210A JP2005171210A JP2006344896A JP 2006344896 A JP2006344896 A JP 2006344896A JP 2005171210 A JP2005171210 A JP 2005171210A JP 2005171210 A JP2005171210 A JP 2005171210A JP 2006344896 A JP2006344896 A JP 2006344896A
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- surface electrode
- circuit board
- lsi package
- pads
- bumps
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Abstract
回路基板にフリップチップ接続されているLSIパッケージの消費電力を低減する。
【解決手段】LSIパッケージ21は、信号を入出力するためのパッド22,…,22が所定の位置に設けられ、信号を入出力するためのパッド23,…,23が同パッド22,…,22に対応する位置に設けられているプリント基板24に対して、バンプ25,…,25を介してフリップチップ接続されている。バンプ25,…,25は、パッド22,…,22とパッド23,…,23の間に挟装されることによりキャパシタを構成するための誘電体材料で形成されている。このLSIパッケージ21では、パッド22,…,22とバンプ25,…,25とパッド23,…,23とで構成されるキャパシタを介して信号が入出力される。
【選択図】 図1
Description
同図に示すように、LSIパッケージ1は、信号を入出力するための複数のパッド(表面電極)2,…,2が所定の位置に設けられ、信号を入出力するための複数のパッド(表面電極)3,…,3が同パッド2,…,2に対応する位置に設けられているプリント基板4に対してフリップチップ接続するための半田バンプ5,…,5を有している。この場合、パッド2,…,2及びパッド3,…,3は、たとえば、直径が1mmの円柱状に形成され、同パッド2,…,2とパッド3,…,3との距離(すなわち、半田バンプ5の高さ)は、10μmに設定されている。また、半田バンプ5,…,5は、ほぼ球状となっている。
このプリント基板4では、同図8に示すように、パッド3に伝送路(パターン)11を介して容量性部品12の一方の端子及び抵抗部品13の一方の端子が接続され、同容量性部品12の他方の端子及び抵抗部品13の他方の端子がグラウンド(GND)に接続されている。伝送路11は、たとえば、特性インピーダンスが100Ω、伝搬遅延時間は7.5ns/m、及び線長が50cmとなっている。また、容量性部品12の容量は20pF、抵抗部品13の抵抗値が100Ωとなっている。
同図9に示すように、電流値は、最小値が−12mA、及び最大値が19.5mAであり、これらの差分は31.5mAとなっている。
特許文献1に記載されたバイパスコンデンサは、グリッドアレイタイプの電子部品とプリント基板との間に配されて電源電極と接地電極とに接続される誘電体材料で構成されている。このため、電子部品との間のインダクタンスがなくなり、同電子部品への給電が効率的に行われる。また、電子部品とプリント基板とは、基板装着用電極を介して接続されている。
すなわち、図7のLSIパッケージでは、消費電流の最小値と最大値との差分が31.5mAであり、比較的大きい。このため、消費電力の低減が困難であり、このLSIパッケージを携帯電話機などのような携帯用電子機器に用いた場合、バッテリの寿命が短いという問題点がある。また、消費電力が大きいため、発熱に対する対策も煩雑になるという問題点がある。
この例のLSIパッケージ21は、同図に示すように、信号を入出力するための複数のパッド(上部電極)22,…,22が所定の位置に設けられ、信号を入出力するための複数のパッド(下部電極)23,…,23が同パッド22,…,22に対応する位置に設けられているプリント基板24に対してフリップチップ接続するためのバンプ25,…,25を有している。この場合、パッド22,…,22及びパッド23,…,23は、たとえば、直径が1mmの円柱状に形成され、同パッド22,…,22とパッド23,…,23との距離(すなわち、バンプ25,…,25の高さ)は、10μmに設定されている。また、バンプ25,…,25は、ほぼ円柱状となっている。バンプ25,…,25は、パッド22,…,22とパッド23,…,23の間に挟装されることによりキャパシタを構成するための誘電体材料で形成されている。誘電体材料としては、たとえば、ポリイミドで不純物を増加したものや、薄膜セラミックが用いられ、比誘電率は、たとえば20となっている。LSIパッケージ21をプリント基板24に接続する場合、たとえば、所定の温度条件のもとでリフローにより行われる。
このプリント基板24では、同図2に示すように、パッド23に伝送路(パターン)31を介して容量性部品32の一方の端子及び抵抗部品33の一方の端子が接続され、同容量性部品32の他方の端子及び抵抗部品33の他方の端子がグラウンド(GND)に接続されている。伝送路31は、たとえば、特性インピーダンスが100Ω、伝搬遅延時間は7.5ns/m、及び線長が50cmとなっている。また、容量性部品32の容量は20pF、抵抗部品33の抵抗値が100Ωとなっている。
同図3に示すように、電流値は、最小値が−40μA、及び最大値が220μAであり、これらの電流差分は、0.26mAとなっている。この電流差分を従来のLSIパッケージ1の電流差分(31.5mA)と比較すると、121分の1の電流量となり、低電力化が実現する。すなわち、従来では、図7中のLSIパッケージ1とプリント基板4との間で入出力される信号に対応する電流が半田バンプ5を介して直接流れるようになっていたが、この実施例では、LSIパッケージ21とプリント基板24との間で入出力される信号に対応する電流がバンプ25を介して直接流れないため、消費電力が低減される。
この例のLSIパッケージ21Aでは、同図4(a),(b)に示すように、パッド22,…,22が設けられている領域以外の領域に、プリント基板24を接続して支えるための補強ピン26,…,26が設けられている。補強ピン26,…,26の材質は、プリント基板24を確実に支えるものであれば、任意のもので良い。このLSIパッケージ21Aでは、補強ピン26,…,26によりプリント基板24が確実に支えられるので、同プリント基板24の接続状態の信頼性が向上する。
この例のLSIパッケージ21Bでは、同図5に示すように、パッド22,…,22が設けられている領域以外の領域に、プリント基板24を接続して同プリント基板24に対する高さを調整するための高さ調整用部材27が設けられている。このLSIパッケージ21Bでは、高さ調整用部材27によりプリント基板24に対する高さが調整されるので、パッド22,…,22、バンプ25,…,25又はパッド23,…,23の高さを調整する必要がある場合でも、容易に対応できる。
この例の回路基板は、同図6に示すように、プリント基板24Aであり、信号を入出力するための複数のパッド(表面電極)23,…,23が所定の位置に設けられ、内層部に、当該基板24Aを構成する誘電体29,…,29をパッド23,…,23との間に挟装することによりキャパシタを構成するための複数のパッド(内部電極)30,…,30が設けられている。パッド30,…,30には、図示しないパターンが接続されている。また、パッド23,…,23には、半田バンプ28,…,28及びパッド22,…,22を介してLSIパッケージ21が接続されている。
たとえば、パッド22の形状は、円柱状に限らず、プリント基板23上のパターンに応じて多角柱状としても良い。また、上記第1乃至第3の実施例では、LSIパッケージ21,21A,21Bがプリント基板24にチップ・オン・ボード方式により接続されているが、同プリント基板24に代えて、半導体チップを設け、チップ・オン・チップ方式により接続しても、上記実施例とほぼ同様の作用、効果が得られる。また、誘電体材料で形成されているバンプ25は、たとえば多数の半導体チップを3次元的に接続してSIP(システム・イン・パッケージ)を構成する場合に用いても良い。
22,23 パッド(表面電極)
24 プリント基板(電子部品)
24A プリント基板(回路基板)
25 バンプ
26 補強ピン(支持用部材)
27 高さ調整用部材
29 誘電体
30 パッド(内部電極)
Claims (9)
- 信号を入出力するための第1の表面電極が所定の位置に設けられ、前記信号を入出力するための第2の表面電極が前記第1の表面電極に対応する位置に設けられている回路基板又は電子部品に対して接続するためのバンプが前記第1の表面電極上に形成されているLSIパッケージであって、
前記バンプは、
前記第1の表面電極と前記第2の表面電極との間に挟装されることによりキャパシタを構成するための誘電体材料により形成されていることを特徴とするLSIパッケージ。 - 前記第1の表面電極と各バンプと第2の表面電極とで構成される前記キャパシタを介して前記信号を入出力する構成とされていることを特徴とする請求項1記載のLSIパッケージ。
- 前記回路基板又は電子部品に対する当該LSIパッケージの接続は、フリップチップ接続であることを特徴とする請求項1又は2記載のLSIパッケージ。
- 前記第1の表面電極が設けられている領域以外の領域に、前記回路基板又は電子部品を接続して支えるための支持用部材が設けられていることを特徴とする請求項1、2又は3記載のLSIパッケージ。
- 前記第1の表面電極が設けられている領域以外の領域に、前記回路基板又は電子部品を接続して該回路基板又は電子部品に対する高さを調整するための高さ調整用部材が設けられていることを特徴とする請求項1、2又は3記載のLSIパッケージ。
- 請求項1乃至5のいずれか一に記載のLSIパッケージが実装されていることを特徴とする回路基板。
- 信号を入出力するための表面電極が所定の位置に設けられている回路基板であって、
当該基板の内層部に、当該基板を構成する誘電体を前記表面電極との間に挟装することによりキャパシタを構成するための内部電極が設けられていることを特徴とする回路基板。 - 前記表面電極と誘電体と内部電極とで構成される前記キャパシタを介して前記信号を入出力する構成とされていることを特徴とする請求項7記載の回路基板。
- 信号を入出力するための第1の表面電極が所定の位置に設けられ、前記信号を入出力するための第2の表面電極が前記第1の表面電極に対応する位置に設けられているLSIパッケージに対してフリップチップ接続するためのバンプが前記第1の表面電極上に形成されている回路基板であって、
前記バンプは、
前記第1の表面電極と前記第2の表面電極との間に挟装されることによりキャパシタを構成するための誘電体材料により形成されていることを特徴とする回路基板。
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JP2005171210A JP4632870B2 (ja) | 2005-06-10 | 2005-06-10 | Lsiパッケージ及び回路基板 |
TW095118572A TWI325170B (en) | 2005-06-10 | 2006-05-25 | Connecting structure, printed substrate, circuit, circuit package and method of forming connecting structure |
US11/444,447 US7554187B2 (en) | 2005-06-10 | 2006-06-01 | Connecting structure, printed substrate, circuit, circuit package and method of forming connecting structure |
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WO2009136468A1 (ja) * | 2008-05-09 | 2009-11-12 | パナソニック株式会社 | 半導体装置、およびその製造方法 |
JP2010177102A (ja) * | 2009-01-30 | 2010-08-12 | Molex Inc | 電気回路の接続構造および電気回路の接続方法 |
JP2011009742A (ja) * | 2009-06-25 | 2011-01-13 | Internatl Business Mach Corp <Ibm> | 集積回路チップ・パッケージ、構造および方法 |
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TWI395518B (zh) * | 2009-09-08 | 2013-05-01 | Compal Electronics Inc | 電路板疊合結構 |
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US5404265A (en) | 1992-08-28 | 1995-04-04 | Fujitsu Limited | Interconnect capacitors |
JPH0870079A (ja) | 1994-08-30 | 1996-03-12 | Hitachi Ltd | 半導体装置 |
JPH09102432A (ja) | 1995-10-05 | 1997-04-15 | Canon Inc | バイパスコンデンサ及びその形成方法 |
JP3990679B2 (ja) | 1996-11-08 | 2007-10-17 | 株式会社リコー | 半導体実装用回路基板を備えた半導体装置 |
JP3544902B2 (ja) | 1999-09-16 | 2004-07-21 | 株式会社東芝 | 半導体装置およびその製造方法 |
US6627998B1 (en) * | 2000-07-27 | 2003-09-30 | International Business Machines Corporation | Wafer scale thin film package |
US6663799B2 (en) * | 2000-09-28 | 2003-12-16 | Jsr Corporation | Conductive metal particles, conductive composite metal particles and applied products using the same |
JP3671351B2 (ja) | 2001-05-23 | 2005-07-13 | カシオ計算機株式会社 | 半導体装置並びにその製造方法および実装方法 |
JP2004095804A (ja) | 2002-08-30 | 2004-03-25 | Toppan Printing Co Ltd | 受動素子内蔵プリント配線板及びその製造方法 |
JP3808030B2 (ja) * | 2002-11-28 | 2006-08-09 | 沖電気工業株式会社 | 半導体装置及びその製造方法 |
US7327554B2 (en) * | 2003-03-19 | 2008-02-05 | Ngk Spark Plug Co., Ltd. | Assembly of semiconductor device, interposer and substrate |
JP2005045000A (ja) | 2003-07-22 | 2005-02-17 | Toppan Printing Co Ltd | 受動素子内蔵多層プリント配線板の製造方法 |
US7435627B2 (en) * | 2005-08-11 | 2008-10-14 | International Business Machines Corporation | Techniques for providing decoupling capacitance |
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WO2009136468A1 (ja) * | 2008-05-09 | 2009-11-12 | パナソニック株式会社 | 半導体装置、およびその製造方法 |
US8415794B2 (en) | 2008-05-09 | 2013-04-09 | Panasonic Corporation | Semiconductor device having stable signal transmission at high speed and high frequency |
JP5386481B2 (ja) * | 2008-05-09 | 2014-01-15 | パナソニック株式会社 | 半導体装置、およびその製造方法 |
JP2010177102A (ja) * | 2009-01-30 | 2010-08-12 | Molex Inc | 電気回路の接続構造および電気回路の接続方法 |
JP2011009742A (ja) * | 2009-06-25 | 2011-01-13 | Internatl Business Mach Corp <Ibm> | 集積回路チップ・パッケージ、構造および方法 |
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US20070080468A1 (en) | 2007-04-12 |
TW200733335A (en) | 2007-09-01 |
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