TWI325170B - Connecting structure, printed substrate, circuit, circuit package and method of forming connecting structure - Google Patents

Connecting structure, printed substrate, circuit, circuit package and method of forming connecting structure Download PDF

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Publication number
TWI325170B
TWI325170B TW095118572A TW95118572A TWI325170B TW I325170 B TWI325170 B TW I325170B TW 095118572 A TW095118572 A TW 095118572A TW 95118572 A TW95118572 A TW 95118572A TW I325170 B TWI325170 B TW I325170B
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TW
Taiwan
Prior art keywords
electrode
circuit
connection structure
electronic component
dielectric layer
Prior art date
Application number
TW095118572A
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English (en)
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TW200733335A (en
Inventor
Kamiya Hiroshi
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Nec System Technology Ltd
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Publication of TW200733335A publication Critical patent/TW200733335A/zh
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Publication of TWI325170B publication Critical patent/TWI325170B/zh

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
    • H05K1/162—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed capacitors
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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L24/72—Detachable connecting means consisting of mechanical auxiliary parts connecting the device, e.g. pressure contacts using springs or clips
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
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    • H05K2201/2036—Permanent spacer or stand-off in a printed circuit or printed circuit assembly

Description

1325170 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種電路封梦，争桩&丨 私吩王了裝，更特別關於積體電路板 與基板之間的連接結構。 【先前技術】 本發明係有關連接結構、印刷基板、電路封裝、以及 連接結構之形成方法。電路一般為大型積體電路（lsi )，印 刷基板一般為電路基板，而電路封裝則有關於lsi與電路 基板。另一方面，本發明可應用於移動式電子設備如行動 電視，以減少電池的耗損。 當電路元件如LSI嵌置於電路基板或半導體晶片上， 該些元件、基板、或晶片之表面電極一般係以打線接合的 技術連接，用以輸入/輸出訊號。常見的打線接合長度都相 當長，隨之提高的電感將劣化電阻-電感-電容（RLC)的特 性，並降低輸入/輸出的訊號速度。近來解決此問題的方法 包括板上晶片（chip-on-board ，C0B)、疊層晶片 (chip-〇n-chip)、及覆晶封裝（fHp_chip)等系統。覆晶封 裝係以凸塊（突起電極）連接電路（LSI)及電路基板（或半導 體晶片）。 在第7圖中’係習知技藝之電路如LSI採用C0B系統 的連接方式。電路1具有複數個銲墊2位於適當的位置以 輸入輸出訊號’與銲料凸塊5以覆晶封裝連線至印刷基板 4連線基板4具有複數個銲塾3，對應電路1之銲墊2， 並輸入/輪出訊號。在此例中，銲墊2、3之剖面為直徑i
7061-8069-PF 5 毫米之圓形，兩者間之距離（ ^ 0 , .3^, 枓凸塊5之厚度）為10微 木。此外，銲料凸塊5之立丨丨 勺i U做 及3之。丨l·面貫質上為圓形。 在第8圖中，印刷基板 13之一端接妯^ . 之電谷。卩伤12與電阻部份 而接地’兩者之另一端則藉 接至銲墊3。傳輸通道u之胜2u電性連 寺陡阻抗為1 0 0 Ω，傳輪#谁 時間為7.5奈秒/米，導線导μ… 得輸延遲 导磉長度為5 0公分。此外，雷玄
份12之電容為2〇 F， P 电I且邛伤13之電阻為I〇〇Q。 第9圖係第8圖之雷故彳, 的輸出端接上輸出緩衝器（未 圖不）作為輸出介面所測得$、、占如+ + 所利仵之扁耗電流。其縱軸為電流值， 橫軸為時間。由第9圖可渣埜恭目θ 木3圃J π楚發現取小電流為2 mA，最 大電流為19.5 mA，差距為315 “。 在 JP APPlication N〇. 1〇2432/1 997 中，描述 了一種 旁路電容，包括一介電層位於格狀陣列電子部份與印刷基 板之間。此旁路電容連接至電源電極與接地電極。综上所 述’此結構彳消除對應言亥電子部份之電《，幻吏電源能更 有放的提供電力至電子部份。此外，電子部份與印刷基板 係以電極連接以嵌置於基板上。 然而上述之電路具有許多缺點。舉例來說，第7圖之 電路1其消耗電流的極大值與極小值差異過大（如3丨.5 mA)。如此一來電路丄若應用於移動式電子設備如行動電視 時’將消耗更多電力同時縮短電池的使用時間。快速的電 力消耗亦會產生大量的熱，在散熱的設計上又是另外一個 問題。 JP Application No. 1 02432/1 997 的旁路電容與印刷
7061-8069-PF 6 ㊁板：以電極連接並嵌置於基板’以確認電極與基板導 Ή ’介電層連接至電源電極與接定電極。在接 兄月中’可了解此專利與本發明採 問題是不一樣的。 再一心'解决的 目前㈣—種新的封裝結構 決上述問題。 広以解 【發明内容】 為了提尚習知技蔹中洁紅讲夕办+ 發明提供“-中4耗過夕電流及散熱等問題，本 第=、—種連接結構’位於電路與電子元件之間，包括 極之間。 及"電層位於第-電極與第二電 明，供一種印刷基板，如上述之連線結構。 明，供一種電路’如上述之連線結構。 -電極；印刷基板=包括電路，具有上述之第 電#物於错 /、有上述之第二電極；以及上述之介 電層’位於第-電極與第二電極之間。 之，, 本發明亦提供一種連接沾 間，包括：第—電極；第-位於電路與電子元件之 電流流通於第-電極與第元件，以允許間接 本發明更提供—德、由> 電層於第-電極鱼第_雷表構之形成方法，包括形成介 畀弟一電極之間。 【實施方式】 本發明之覆晶封裝結構中 接。凸塊之材質為介電 冑路與印刷基板以凸塊連 '、，且印刷基板之内層部份可包
7061-8069-PF 括一内電極與介電材料。 [第一實施例] 第1圖係本發明第一實施例之連接結構剖面圖，電路 21具有複數個層狀銲墊22(又稱上電極或表面電極）位於 適當的位置以輸入/輸出訊號，以及凸塊25以覆晶封裝連 線至印刷基板24。印刷基板24具有複數個層狀銲墊23，
對應層狀銲墊22之位置並輸入/輸出訊號。 在此例十，銲墊22與23之剖面實質上為直徑ι毫米 之圓形，兩者間之距離（即凸塊之厚度）實質上為1〇微米。 此外，凸塊25之剖面實質上為圓形。在此必需說明的是 凸塊25及銲墊22與23之尺寸與形狀並不受實施例限制 本技藝人士自可依需要調整。
凸塊25為介電材料，可為聚亞醯胺或摻雜之聚亞酿胺 或陶兗薄膜，介電常數實質上大於4,較佳介於4至2〇之 間更佳"於15至20之間。連接電路21與印刷基板24 之凸塊25㈣《方法可為適當溫度下的再流動。 電路21的輸出/輸入訊號係經由鲜塾22、凸塊、以及 i干塾23形成之電容。此外，電路2ι之電㈣來自饋電線 路（power feed line)(未圖示）。 第2圖係第1圖之連接結構之電路圖。印刷基板24 中，電谷部份3 2與電阻邱々v <5 <3 电丨丑邛伤33之一端接地，另一端則藉 由傳輸通道31電性連接$啻6 逆按至電谷34。如第1圖所示，電容 34係由銲墊22、凸塊、以；^ 尼以及鲜墊23組成。傳輸通道31之 特性阻抗為1 0 0 D，偯絡M+ 得輸延遲時間為7.5奈秒/米，導線長
7061-8069-PF 8 度為5°公分。此夕卜，電容部份32之電容可為20 阻部份33之電阻可為議。電“為2。…電 (未圖V)::::圖之電路21其輸出端接上輸出緩衝器 流值，橫輪二Γ:所測得之消耗電流值。其縱轴為電 較，第9圖…差二二差距°.2“Α。與第9圖相 消耗電H 121倍，因此第3圖之 、4 於第9圖’第丨圖之連接結構明顯優於第7 圖之連接結構。差別在於第i圖之印刷基板Μ與電路a 之間輸入/輸出訊號並不似帛7圖之訊號直接流經録料凸 塊5,而是以間接電流的形式流經凸力25，因此可減 力的消耗。 如上所述，第一實施例之銲墊22、介電材料形成之凸 塊25、及銲墊23組成電容，使電流不能直接通過電路u 與印刷基板24之間，並減少電力消耗。綜上所述，第一實 施例之連接結構若應用於移動式電子設備如行動電視時， 可大幅延長電池使用的時間。此外’此連接結構產生的熱 較少，散熱方面的設計也可因此簡化。 [第二實施例] 第4A圖係本發明第二實施例之連接結構之平面圖，而 第4B圖係第4A圖中A-A方向之剖面圖。 在此實施例中’電路21A與印刷基板2 4間包含強化構 件（reinforcing pin)26，用以連接及支撐電路21與印刷 基板2 4。上述之強化構件係設置於鮮塾2 2以外的區域， 7061-8069-PF 9 1325170 ，組成為可支#印刷基板24的任何材料。由於強化構件 明顯的支撐住印刷基板24，連接結構的可靠性亦隨 善。 艰之改 [第三實施例] 一第5圖係本發明第三實施例之連接結構剖面圖，其中 高度控制構件27設置於銲墊22以外的區域，用以決^電 路21與印刷基板24之間的距離。由於高度控制構件、^的 存在，可輕易的控制及複製銲墊22、23及凸塊25的厚度。 [第四、五、六實施例] 又 第6Α圖係本發明第四實施例之連接結構剖面圖，印刷 基板24Α具有複數個銲墊23設置於適當的位置以輸入/輪 出訊號，以及複數個銲墊30以及介電層29位於内層部^ 以形成電容。該些銲墊30係以導電圖案（未圖示）電性連 接。此外，銲墊23藉由凸塊29及銲墊22連接至電路21。 第6B、6C圖分別為本發明第五、第六實施例之連接結 構的剖面圖。第6B圖之電路21其内層具有銲墊⑽及介^ 層29。而第2C圖之電路21其外侧具有銲墊3〇及介電岸 29。 曰 在印刷基板24A中，訊號經由銲墊23、介電層29、及 銲墊30組成之電容輸入/輸出。由於電流係以間接而非直 接的方式流經印刷基板24A與電路2〗之間，可因此減少電 力耗損。 在此必需說明的是，銲墊的形狀及尺寸並不限定於圓 形’可根據印刷基板上的圖案變化為多邊形。此夕卜，銲墊
7061-8069-PF 10 丄:325170 可為導電材質如金屬或多晶矽。 在上述之第一、二、三實施例中，電路21、2ia、或 21B可藉由C0B系統連接至印刷基板24。若將印刷基板24 換作半導體晶片，連接結構則由C0B系統改為疊層晶片系 統。 凸塊25亦可應用於其他系統如系統級封裝 Csystem-in-package)’其可將複數個半導體晶片連接成一 3D立體態樣。 凸塊25可為介電材料如氧化鈕（Ta2〇〇、鈦酸鋇 (BaTi〇3)、錯鈦酸鉛（PbZr〇3—pbTi〇3，ρζτ)、氟氧化矽 (Si〇xFy)、聚亞醯胺、4號抗燃-(ΝΕΜΑ所售之fr_4，為環 氧樹脂黏合之層狀玻璃樹脂，一般用於通訊設備、電腦、 電腦周邊、儀器、工業控制、汽車電子零件）、或5號抗燃 劑（FR-5 ’與FR-4類似，但在高溫下其機械強度較強）。 此外，雖然本發明實施例之凸塊主要為介電材料，但 仍可視情況混用銲料凸塊。而連接電路與印刷基板的方法 除了再流動以外，亦可應用其他技術如超音波系統。 雖然&塊係先形成於電路的一側後再連接至印刷基 板，但亦可先形成於印刷基板的一侧後再連接至電路，兩 種方式的功能完全一樣。 本發明主要應用係覆晶封袭的連接結構。本發明在行 動電子設備如行動電視或攜帶式訊息終端（p〇rtaMe ⑻则ation terminal)等應用有特別的好處，可大幅降低 電力耗損。 7061-8069-PF 11
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雖然本發明P i、，A 乂數個較佳實施例揭露如上，然其並北 用以限定本發明 八 4何所屬技術領域中具有通常知識者， 在不脫離本發明之牲 <楕神和範圍内，當可作任意之更動盥 飾，因此本發明夕扣— 又切，、潤 … 保護範圍當視後附之申請專利範圍所界 定者為準。 1^ 【圖式簡單說明】 圖； 圖； 輸出緩衝 之平面圖 第1圖係本發明第一實施例之連接結構剖3
第2圖係本”中第1圖之連接結構之電足 ”第3圖係本發明中第2圖之電路輸出端接_ 器作為輸出介面所測得之消耗電流值； 第4A、4B圖係本發明第二實施例之連接結4 與剖面圖； 第 第 剖面圖 5圖係本發明第 6 A - 6 C圖係本發 二實施例之連接結構剖面圖； 明第四、S、六實施例之連接結構
第7圖係習知技藝之連接結構的剖視圖； 第8圖係第7圖之連接結構的電路圖； 上輪出緩衝 。。第9圖係本發明中第8圖之電路輸出端接 益作為輸出介面所測得之消耗電流值。 【主要元件符號說明】 5 ~鲜料凸塊； 】、21、21A〜電路； 2' 3、22、23、30〜輝塾； 2 5〜凸塊；
7〇62-8〇69-PF 12 1325170 2 6〜強化構件； 27~高度控制構件； 11、31〜傳輸通道； 1 2、3 2〜電容部份； 1 3、3 3〜電阻部份； 29〜介電層； 34〜電容；
7061-8069-PF 13

Claims (1)

13^170 「α ——.~~8.12.10 严為/』月,t?日修⑻正替換寶 第0951〗8572號中文申請專利範圍修正本 9 十、申請專利範圍： 1. 一種連接結構，位於一電路與一電子元件之間，包 括： 一第一電極位於該電路上； 一第一電極位於該電子元件上，該第二電極包括該電 子元件之輸入/輪出末端； 其中該第-電極與該第二電極實質上重疊，該電路與 該電子几件彼此電性連接，且該電路與該電子元件之間不 _ 具有任何線路；以及 一介電層位於該第一電極與該第二電極之間，且該介 電層直接接觸該第一電極與該第二電極。 2·如申請專利範圍第】項所述之連接結構，其中一訊 號藉由該第-電極、該第.二電極、及該介電層輪入/輸出°。 3·如申請專利範圍第2項所述之連接結構，其中該訊 號包括一資訊運載訊號。 、
4·如申請專利範圍第1項所述之連接結構，並中該介 電層包括氧化组、鈦酸鋇、結欽酸錯、氟氧化石夕、聚亞醯 胺、FR 4(4號抗燃劑）、或FR 5(5號抗燃劑）。 5·如申請專利範圍第1 電層之介電常數實質上大於 之直徑實質上為1毫米，且 離實質上為1 〇微米。 項所述之連接結構，其中該介 4,該第一電極與該第二電極 該第一電極與該第二電極的距 項所述之連 •種印刷基板，包括申請專利範圍第 接結構。 7061-8069-PF1 7·種電路，包括申請專利範圍第1項所述之連接结 構。 8. —種電路封裝，包括： 一電路’具有申請專利範圍第1項所述之第一電極； 一印刷基板’具有申請專利範圍第1項所述之第二電 極；以及 申請專利範圍第1項所述之介電詹》 9. 如申請專利範圍第8項所述之電路封裝，其中該印 刷基板之内層部份包括該連接結構之該第二電極與該介電 層。 10. 如申請專利範圍第8項所述之電路封裝，其中該電 路之内層部份包括該連接結構之該第一電極與該介電層。 11. 如申請專利範圍第8項所述之電路封裝，其中該電' 路之外侧更包括該連接結構之該第一電極與該介電層。- 12. 如申請專利範圍第8項所述之電路封裝，更包括一 強化構件強化該印刷基板與該電路之間的連接。 13·如申請專利範圍第12項所述之電路封裝，其令該 春 強化構件設置於該第一電極以外的區域。 14. 如申請專利範圍第8項所述之電路封裝，更包括一 咼度控制構件，用以控制該印刷基板與該電路之間的距離。 15. 如申請專利範圍第項所述之電路封袭，其中該 南度控制構件設置於該第一電極以外的區域。 如申請專利範圍第8項所述之電路封裴，其中該印 刷基板與該電路之間的連接結構包括覆晶封裝連接結構。 7061-8069-PF] 15 丄325170 包括： ’該第二電極包括該 電極與該第二電極實 17· —種連接結構之形成方法 提供一第一電極於—電路上. 電子元件上 提供一第二電極於— 電子元件之輸入/輪出末端，且該第 質上重疊； 其中該電路與該電子元件彼此電性連接，且該電路與 該電子元件之間不具有任何線路； 形成一介電層於該第一電極與該第二電極之間；以及 使該介電層直接接觸該第一電極與該第二電極。 18. 如申請專利範圍第17項所述之連接結構之形成方 法’其中該；I電層包括氧化组、欽酸類、結敛酸錯、氟氧 -化矽、聚亞醯胺、FR 4(4號抗燃劑）、或FR 5(5號抗燃劑）。 19. 如申請專利範圍第17項所述之連接結構之形成方 法，其中該介電層形成一電容，以允許一間接電流流通於 該第一電極與該第二電極之間。
7061-8069-PF1 16
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Publication number Priority date Publication date Assignee Title
WO2009136468A1 (ja) * 2008-05-09 2009-11-12 パナソニック株式会社 半導体装置、およびその製造方法
JP5113101B2 (ja) * 2009-01-30 2013-01-09 モレックス インコーポレイテド 電気回路の接続構造および電気回路の接続方法
US8044512B2 (en) * 2009-06-25 2011-10-25 International Business Machines Corporation Electrical property altering, planar member with solder element in IC chip package
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Family Cites Families (13)

* Cited by examiner, † Cited by third party
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US5404265A (en) 1992-08-28 1995-04-04 Fujitsu Limited Interconnect capacitors
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JPH09102432A (ja) 1995-10-05 1997-04-15 Canon Inc バイパスコンデンサ及びその形成方法
JP3990679B2 (ja) 1996-11-08 2007-10-17 株式会社リコー 半導体実装用回路基板を備えた半導体装置
JP3544902B2 (ja) 1999-09-16 2004-07-21 株式会社東芝 半導体装置およびその製造方法
US6627998B1 (en) * 2000-07-27 2003-09-30 International Business Machines Corporation Wafer scale thin film package
US6663799B2 (en) * 2000-09-28 2003-12-16 Jsr Corporation Conductive metal particles, conductive composite metal particles and applied products using the same
JP3671351B2 (ja) 2001-05-23 2005-07-13 カシオ計算機株式会社 半導体装置並びにその製造方法および実装方法
JP2004095804A (ja) 2002-08-30 2004-03-25 Toppan Printing Co Ltd 受動素子内蔵プリント配線板及びその製造方法
JP3808030B2 (ja) * 2002-11-28 2006-08-09 沖電気工業株式会社 半導体装置及びその製造方法
US7327554B2 (en) * 2003-03-19 2008-02-05 Ngk Spark Plug Co., Ltd. Assembly of semiconductor device, interposer and substrate
JP2005045000A (ja) 2003-07-22 2005-02-17 Toppan Printing Co Ltd 受動素子内蔵多層プリント配線板の製造方法
US7435627B2 (en) * 2005-08-11 2008-10-14 International Business Machines Corporation Techniques for providing decoupling capacitance

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