JP2006324665A5 - - Google Patents

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Publication number
JP2006324665A5
JP2006324665A5 JP2006136747A JP2006136747A JP2006324665A5 JP 2006324665 A5 JP2006324665 A5 JP 2006324665A5 JP 2006136747 A JP2006136747 A JP 2006136747A JP 2006136747 A JP2006136747 A JP 2006136747A JP 2006324665 A5 JP2006324665 A5 JP 2006324665A5
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JP
Japan
Prior art keywords
offset
package
base
base plate
board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2006136747A
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English (en)
Japanese (ja)
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JP4402074B2 (ja
JP2006324665A (ja
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Publication date
Priority claimed from US11/383,403 external-priority patent/US7518224B2/en
Application filed filed Critical
Publication of JP2006324665A publication Critical patent/JP2006324665A/ja
Publication of JP2006324665A5 publication Critical patent/JP2006324665A5/ja
Application granted granted Critical
Publication of JP4402074B2 publication Critical patent/JP4402074B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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JP2006136747A 2005-05-16 2006-05-16 オフセット集積回路パッケージオンパッケージ積層システムおよびその製造方法 Active JP4402074B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US59488405P 2005-05-16 2005-05-16
US11/383,403 US7518224B2 (en) 2005-05-16 2006-05-15 Offset integrated circuit package-on-package stacking system

Publications (3)

Publication Number Publication Date
JP2006324665A JP2006324665A (ja) 2006-11-30
JP2006324665A5 true JP2006324665A5 (enExample) 2009-06-18
JP4402074B2 JP4402074B2 (ja) 2010-01-20

Family

ID=38038592

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006136747A Active JP4402074B2 (ja) 2005-05-16 2006-05-16 オフセット集積回路パッケージオンパッケージ積層システムおよびその製造方法

Country Status (4)

Country Link
US (1) US7518224B2 (enExample)
JP (1) JP4402074B2 (enExample)
KR (1) KR101076062B1 (enExample)
TW (1) TWI334639B (enExample)

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KR20090004171A (ko) * 2007-07-06 2009-01-12 삼성전자주식회사 반도체 패키지
US7812435B2 (en) * 2007-08-31 2010-10-12 Stats Chippac Ltd. Integrated circuit package-in-package system with side-by-side and offset stacking
US7872340B2 (en) * 2007-08-31 2011-01-18 Stats Chippac Ltd. Integrated circuit package system employing an offset stacked configuration
US8536692B2 (en) * 2007-12-12 2013-09-17 Stats Chippac Ltd. Mountable integrated circuit package system with mountable integrated circuit die
US8084849B2 (en) * 2007-12-12 2011-12-27 Stats Chippac Ltd. Integrated circuit package system with offset stacking
US7985628B2 (en) * 2007-12-12 2011-07-26 Stats Chippac Ltd. Integrated circuit package system with interconnect lock
US7781261B2 (en) * 2007-12-12 2010-08-24 Stats Chippac Ltd. Integrated circuit package system with offset stacking and anti-flash structure
JP5543071B2 (ja) * 2008-01-21 2014-07-09 ピーエスフォー ルクスコ エスエイアールエル 半導体装置およびこれを有する半導体モジュール
US8067828B2 (en) * 2008-03-11 2011-11-29 Stats Chippac Ltd. System for solder ball inner stacking module connection
US20090243069A1 (en) * 2008-03-26 2009-10-01 Zigmund Ramirez Camacho Integrated circuit package system with redistribution
US9293385B2 (en) * 2008-07-30 2016-03-22 Stats Chippac Ltd. RDL patterning with package on package system
US7785925B2 (en) * 2008-12-19 2010-08-31 Stats Chippac Ltd. Integrated circuit packaging system with package stacking and method of manufacture thereof
US7968995B2 (en) * 2009-06-11 2011-06-28 Stats Chippac Ltd. Integrated circuit packaging system with package-on-package and method of manufacture thereof
KR20120032293A (ko) * 2010-09-28 2012-04-05 삼성전자주식회사 반도체 패키지
US8508045B2 (en) * 2011-03-03 2013-08-13 Broadcom Corporation Package 3D interconnection and method of making same
US10163877B2 (en) * 2011-11-07 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. System in package process flow
KR102021077B1 (ko) * 2013-01-24 2019-09-11 삼성전자주식회사 적층된 다이 패키지, 이를 포함하는 시스템 및 이의 제조 방법
CN106663674B (zh) * 2014-04-30 2019-09-17 英特尔公司 具有模制化合物的集成电路组件
US9871007B2 (en) * 2015-09-25 2018-01-16 Intel Corporation Packaged integrated circuit device with cantilever structure
WO2017074391A1 (en) 2015-10-29 2017-05-04 Intel Corporation Guard ring design enabling in-line testing of silicon bridges for semiconductor packages
US10631410B2 (en) 2016-09-24 2020-04-21 Apple Inc. Stacked printed circuit board packages
US11508663B2 (en) * 2018-02-02 2022-11-22 Marvell Israel (M.I.S.L) Ltd. PCB module on package
CN114144875A (zh) 2019-06-10 2022-03-04 马维尔以色列(M.I.S.L.)有限公司 具有顶侧存储器模块的ic封装

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JP4601892B2 (ja) * 2002-07-04 2010-12-22 ラムバス・インコーポレーテッド 半導体装置および半導体チップのバンプ製造方法
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JP4408636B2 (ja) 2003-02-28 2010-02-03 三洋電機株式会社 回路装置およびその製造方法
TW576549U (en) 2003-04-04 2004-02-11 Advanced Semiconductor Eng Multi-chip package combining wire-bonding and flip-chip configuration
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US7420269B2 (en) * 2006-04-18 2008-09-02 Stats Chippac Ltd. Stacked integrated circuit package-in-package system
US7535086B2 (en) * 2006-08-03 2009-05-19 Stats Chippac Ltd. Integrated circuit package-on-package stacking system
US7635913B2 (en) * 2006-12-09 2009-12-22 Stats Chippac Ltd. Stacked integrated circuit package-in-package system
US7772683B2 (en) * 2006-12-09 2010-08-10 Stats Chippac Ltd. Stacked integrated circuit package-in-package system

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