JP2006120943A5 - - Google Patents

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Publication number
JP2006120943A5
JP2006120943A5 JP2004308558A JP2004308558A JP2006120943A5 JP 2006120943 A5 JP2006120943 A5 JP 2006120943A5 JP 2004308558 A JP2004308558 A JP 2004308558A JP 2004308558 A JP2004308558 A JP 2004308558A JP 2006120943 A5 JP2006120943 A5 JP 2006120943A5
Authority
JP
Japan
Prior art keywords
base material
resin base
chip
external connection
semiconductor chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2004308558A
Other languages
English (en)
Japanese (ja)
Other versions
JP2006120943A (ja
Filing date
Publication date
Application filed filed Critical
Priority to JP2004308558A priority Critical patent/JP2006120943A/ja
Priority claimed from JP2004308558A external-priority patent/JP2006120943A/ja
Priority to EP05255576A priority patent/EP1650798A3/en
Priority to US11/224,821 priority patent/US7312536B2/en
Priority to TW094131451A priority patent/TW200614900A/zh
Priority to KR1020050087299A priority patent/KR20060051422A/ko
Priority to CNB2005101315584A priority patent/CN100446225C/zh
Publication of JP2006120943A publication Critical patent/JP2006120943A/ja
Publication of JP2006120943A5 publication Critical patent/JP2006120943A5/ja
Pending legal-status Critical Current

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JP2004308558A 2004-10-22 2004-10-22 チップ内蔵基板及びその製造方法 Pending JP2006120943A (ja)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP2004308558A JP2006120943A (ja) 2004-10-22 2004-10-22 チップ内蔵基板及びその製造方法
EP05255576A EP1650798A3 (en) 2004-10-22 2005-09-12 A substrate having a built-in chip and external connection terminals on both sides and a method for manufacturing the same
US11/224,821 US7312536B2 (en) 2004-10-22 2005-09-13 Substrate having a built-in chip and external connection terminals on both sides and a method for manufacturing the same
TW094131451A TW200614900A (en) 2004-10-22 2005-09-13 A substrate having a built-in chip and external connection terminals on both sides and a method for manufacturing the same
KR1020050087299A KR20060051422A (ko) 2004-10-22 2005-09-20 내장 칩을 갖고 그 양측에 외부 접속 단자를 갖는 기판과그 제조 방법
CNB2005101315584A CN100446225C (zh) 2004-10-22 2005-09-21 具有内装芯片和两侧上的外部连接端子的基板及其制造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004308558A JP2006120943A (ja) 2004-10-22 2004-10-22 チップ内蔵基板及びその製造方法

Publications (2)

Publication Number Publication Date
JP2006120943A JP2006120943A (ja) 2006-05-11
JP2006120943A5 true JP2006120943A5 (enExample) 2007-11-01

Family

ID=35615238

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004308558A Pending JP2006120943A (ja) 2004-10-22 2004-10-22 チップ内蔵基板及びその製造方法

Country Status (6)

Country Link
US (1) US7312536B2 (enExample)
EP (1) EP1650798A3 (enExample)
JP (1) JP2006120943A (enExample)
KR (1) KR20060051422A (enExample)
CN (1) CN100446225C (enExample)
TW (1) TW200614900A (enExample)

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4428337B2 (ja) * 2005-12-02 2010-03-10 ソニー株式会社 半導体装置の製造方法
KR100770874B1 (ko) 2006-09-07 2007-10-26 삼성전자주식회사 매설된 집적회로를 구비한 다층 인쇄회로기판
KR100823699B1 (ko) * 2006-11-29 2008-04-21 삼성전자주식회사 플립칩 어셈블리 및 그 제조 방법
US8178982B2 (en) * 2006-12-30 2012-05-15 Stats Chippac Ltd. Dual molded multi-chip package system
JP2008277639A (ja) * 2007-05-02 2008-11-13 Casio Comput Co Ltd 半導体装置およびその製造方法
US9610758B2 (en) * 2007-06-21 2017-04-04 General Electric Company Method of making demountable interconnect structure
US9953910B2 (en) 2007-06-21 2018-04-24 General Electric Company Demountable interconnect structure
KR100929464B1 (ko) * 2007-12-21 2009-12-02 주식회사 동부하이텍 반도체칩, 이의 제조 방법 및 반도체칩 적층 패키지
JP4787296B2 (ja) * 2008-07-18 2011-10-05 Ｔｄｋ株式会社 半導体内蔵モジュール及びその製造方法
US8390083B2 (en) 2009-09-04 2013-03-05 Analog Devices, Inc. System with recessed sensing or processing elements
EP2580776A1 (en) * 2010-06-11 2013-04-17 Nec Corporation Method of redistributing functional element
JP5578962B2 (ja) * 2010-06-24 2014-08-27 新光電気工業株式会社 配線基板
US9407997B2 (en) 2010-10-12 2016-08-02 Invensense, Inc. Microphone package with embedded ASIC
JP2012134270A (ja) * 2010-12-21 2012-07-12 Shinko Electric Ind Co Ltd 半導体装置及びその製造方法
JP2012256675A (ja) * 2011-06-08 2012-12-27 Shinko Electric Ind Co Ltd 配線基板、半導体装置及びその製造方法
US9093416B2 (en) * 2011-11-28 2015-07-28 Infineon Technologies Ag Chip-package and a method for forming a chip-package
CN103137613B (zh) * 2011-11-29 2017-07-14 华进半导体封装先导技术研发中心有限公司 制备有源芯片封装基板的方法
US9730329B2 (en) 2011-11-29 2017-08-08 Institute of Microelectronics, Chinese Academy of Sciences Active chip package substrate and method for preparing the same
US9847462B2 (en) 2013-10-29 2017-12-19 Point Engineering Co., Ltd. Array substrate for mounting chip and method for manufacturing the same
WO2015087705A1 (ja) * 2013-12-10 2015-06-18 ソニー株式会社 半導体装置、固体撮像素子、撮像装置および電子機器、並びにそれらの製造方法
US9673171B1 (en) 2014-03-26 2017-06-06 STATS ChipPAC Pte. Ltd. Integrated circuit packaging system with coreless substrate and method of manufacture thereof
DE102014118462A1 (de) * 2014-12-11 2016-06-16 At&S Austria Technologie & Systemtechnik Aktiengesellschaft Semiflexible Leiterplatte mit eingebetteter Komponente
DE102014118464A1 (de) * 2014-12-11 2016-06-16 At&S Austria Technologie & Systemtechnik Aktiengesellschaft Leiterplatte mit einem asymmetrischen Schichtenaufbau
JP6430883B2 (ja) * 2015-04-10 2018-11-28 株式会社ジェイデバイス 半導体パッケージ及びその製造方法
US9666558B2 (en) 2015-06-29 2017-05-30 Point Engineering Co., Ltd. Substrate for mounting a chip and chip package using the substrate
US10068853B2 (en) * 2016-05-05 2018-09-04 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and method of fabricating the same
JP6705501B2 (ja) * 2016-05-25 2020-06-03 日立化成株式会社 封止構造体の製造方法
JP6908112B2 (ja) * 2017-06-30 2021-07-21 株式会社村田製作所 電子部品モジュール及びその製造方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3965277A (en) * 1972-05-09 1976-06-22 Massachusetts Institute Of Technology Photoformed plated interconnection of embedded integrated circuit chips
JP2580537B2 (ja) * 1994-06-27 1997-02-12 工業技術院長 シリカ球状粒子からなる三次元網状構造体
TW401632B (en) * 1998-03-26 2000-08-11 Fujitsu Ltd Resin molded semiconductor device and method of manufacturing semiconductor package
JP2000228467A (ja) * 1998-12-02 2000-08-15 Toshiba Corp 半導体封止用樹脂組成物及び半導体装置とその製造方法
US6348728B1 (en) 2000-01-28 2002-02-19 Fujitsu Limited Semiconductor device having a plurality of semiconductor elements interconnected by a redistribution layer
US20020110956A1 (en) * 2000-12-19 2002-08-15 Takashi Kumamoto Chip lead frames
TW511405B (en) * 2000-12-27 2002-11-21 Matsushita Electric Industrial Co Ltd Device built-in module and manufacturing method thereof
CA2350747C (en) * 2001-06-15 2005-08-16 Ibm Canada Limited-Ibm Canada Limitee Improved transfer molding of integrated circuit packages
JP3910045B2 (ja) * 2001-11-05 2007-04-25 シャープ株式会社 電子部品内装配線板の製造方法
US7154206B2 (en) * 2002-07-31 2006-12-26 Kyocera Corporation Surface acoustic wave device and method for manufacturing same
US7394663B2 (en) * 2003-02-18 2008-07-01 Matsushita Electric Industrial Co., Ltd. Electronic component built-in module and method of manufacturing the same

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