CN100446225C - 具有内装芯片和两侧上的外部连接端子的基板及其制造方法 - Google Patents

具有内装芯片和两侧上的外部连接端子的基板及其制造方法 Download PDF

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CN100446225C
CN100446225C CNB2005101315584A CN200510131558A CN100446225C CN 100446225 C CN100446225 C CN 100446225C CN B2005101315584 A CNB2005101315584 A CN B2005101315584A CN 200510131558 A CN200510131558 A CN 200510131558A CN 100446225 C CN100446225 C CN 100446225C
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substrate
resin piece
semiconductor chip
external connection
connection terminals
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CN1819160A (zh
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山野孝治
荒井直
町田洋弘
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Shinko Electric Industries Co Ltd
Shinko Electric Co Ltd
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Abstract

公开了一种具有内装半导体芯片的基板,包括:内装半导体芯片、将内装半导体芯片包含在其中的树脂件和外部连接端子。树脂件包含树脂和60%到90%重量比的球状填充物。

Description

具有内装芯片和两侧上的外部连接端子的基板及其制造方法
技术领域
本发明通常涉及一种具有内装芯片和两侧上的外部连接端子的基板及其制造方法。更具体地,本发明涉及一种内装半导体芯片,其中树脂件将半导体芯片包含在其中。
背景技术
近些年,半导体芯片在很大程度上变得更加紧凑,因此半导体芯片的尺寸变得更小。随着尺寸的变小,出现了一种其中埋入半导体芯片的基板,换句话说,具有内装芯片的基板。
图1为示出常规具有内装芯片的基板的图。如图1所示,具有内装芯片的基板由支撑板11、内装半导体芯片13、树脂件17、通道18、布线19、外部连接端子20、阻焊剂21、焊料球22和树脂层23构成。内装半导体芯片13由主体14和电极焊盘15构成。
支撑板11支撑设在支撑板11的表面11a上的结构(半导体芯片13、树脂件17及其它)。半导体主体14的未设置电极焊盘的一侧用粘结剂12粘结到支撑板11的表面11a。树脂件17设置在支撑板11上以覆盖半导体芯片13。设置在树脂件17中的每个通道18连接到相应的电极焊盘15并从树脂件17的表面17a露出。将在树脂件17的表面17a上形成的布线19分别连接到通道18和外部连接端子20。
为设置焊料球22而提供的外部连接端子20从阻焊剂21露出。露出外部连接端子20的阻焊剂21设置在树脂件17上以覆盖布线19。设置阻焊剂21是为了保护布线19以防止焊料球22接触布线19。焊料球22设置在外部连接端子20上。设置焊料球22是为了连接另一个基板。例如具有内装芯片的基板25。在支撑板11的下表面11b上形成树脂层23。树脂层23防止由支撑板11支撑的结构(半导体芯片13、树脂件17及其它)与支撑板11一起弯曲(例如参见专利文献1)。
【专利文献1】日本专利申请特许公开No.2001-217381
然而,常规的树脂件17在其玻璃转变温度附近的温度具有低弹性系数,并且在低于玻璃转变温度的温度其热膨胀系数又很高。因此,如上所述,即使在制造具有内装芯片的基板10以后,也必须保留支撑板11以支撑在支撑板11上的结构(半导体芯片13、树脂件17及其它)。而且,在支撑板11的下表面11b上必须设置树脂层23以防止由于树脂件17的变形而使具有内装芯片的基板10弯曲。因此,很难减小具有内装芯片的基板10的厚度,因为必须提供支撑板11和树脂层23。而且,在树脂件17的一侧上设置支撑板11和树脂层23,外部连接端子仅可以连接到树脂件17上没有设置支撑板11和树脂层23的另一侧。应该注意,“玻璃转变温度”是树脂的弹性系数垂直下降的温度。在玻璃转变温度下,树脂的结构从玻璃态转变为粘性态。
发明内容
本发明总的目的是提供一种具有内装芯片和两侧的外部连接端子的薄截面基板,以便附加具有内装芯片的另一个基板并连接其它基板,以及用于制造该基板的方法,它基本上避免了由相关技术的限制和缺点引起的一个或多个问题。
本发明的特征和优点将在下面的分部分的说明中被示出,并从描述和附图中变得显而易见,或者根据在说明书中的教导通过实践本发明而掌握。通过在说明书中以完整、清楚、简明和准确的术语具体提出具有内装芯片和在两侧上的外部连接端子的基板,以使在本领域具有普通技能的人员能够实现本发明,将认识到和获得本发明的目的以及其它结构和优点。为了获得根据本发明的目的的这些和其它优点,本发明提供一种具有内装芯片的基板,包括:内装半导体芯片、将内装半导体芯片包含在其中的树脂件和外部连接端子,其中树脂件包含树脂和60%到90%重量比的球状填充物。
根据上述的本发明,通过使用包含树脂和60%到90%重量比的球状填充物的树脂件,可以获得下面的具有内装芯片的基板,其中与常规的树脂件相比,在玻璃转变温度附近的温度弹性系数变高,并且在低于玻璃转变温度的温度热膨胀系数变低,这样可以防止树脂件的弯曲。因此不必设置支撑板和树脂层,而它们对于具有内装芯片的常规基板是需要的,因此,可以减小具有内装芯片的基板的厚度。应该注意,“玻璃转变温度”是树脂的弹性系数垂直下降的温度。
根据本发明的另一个方案,具有内装芯片的基板由在玻璃转变温度附近的温度具有1GPa到3GPa的弹性系数的树脂件构成。
根据上述的本发明,通过在玻璃转变温度附近的温度具有1GPa到3GPa的弹性系数的树脂件可以防止树脂件的弯曲,该弹性系数大于常规树脂件的弹性系数。
根据本发明的另一个方案,具有内装芯片的基板由在低于玻璃转变温度的温度具有大约10ppm到15ppm的热膨胀系数的树脂件构成。
根据上述发明,热膨胀系数保持在10ppm到15ppm,它在比玻璃转变温度更低的温度低于常规树脂件的热膨胀系数;因此保持小的热变形以便在树脂件受热时防止树脂件弯曲。
根据本发明的另一个方案,具有内装芯片的基板包括在树脂件的两侧上设置外部连接端子。
根据上述的发明,因为在具有内装芯片的基板上不必设置支撑板,所以可以在树脂件的两侧设置外部连接端子。所以,具有内装芯片的基板可以在一侧上安装具有内装芯片的另一个基板,在另一侧连接到第三个基板(例如主板)。
根据本发明的另一个方案,具有内装芯片的基板由具有连接到外部连接端子的电极焊盘的半导体芯片构成。当Al用作电极焊盘的材料时,在电极焊盘上进行锌酸盐处理以在电极焊盘上形成Ni层。
根据本发明,当Al用作电极焊盘的材料时,在电极焊盘上进行锌酸盐处理。因此,防止了电极焊盘再氧化,这样在电极焊盘上容易形成Ni层。当在电极焊盘上形成开口部分以设置通道时,Ni层可以用作阻止膜,由此,防止电极焊盘被损坏。
根据本发明的另一个方案,一种用于制造基板的方法,该基板包括半导体芯片、其中包含半导体芯片的树脂件和外部连接端子,其中树脂件包含树脂和60%到90%重量比的球状填充物,包括下列步骤:在支撑板上设置半导体芯片,在支撑板上设置树脂件以覆盖半导体芯片,以及除去支撑板。
根据上述的本发明,通过使用树脂和60%到90%重量比的球状填充物,与常规的树脂相比,在玻璃转变温度附近的温度的弹性系数变高,并且在低于玻璃转变温度的温度热膨胀系数变低;因此控制了树脂件的弯曲,并且不必设置支撑板和树脂层。因此可以减小具有内装芯片的基板的厚度。
根据本发明的另一个方案,该用于制造具有内装芯片基板的方法进一步包括下列步骤:形成穿透树脂件的穿透的通道,在树脂件的一侧形成第一外部连接端子,其中第一外部连接端子与穿透的通道电连接,以及在树脂件的另一侧形成第二外部连接端子,其中第二外部连接端子与穿透的通道电连接。
根据上述的发明,通过在具有内装芯片的基板的一侧形成与穿透的通道电连接的第一外部连接端子,并且通过在具有内装芯片的基板的另一侧形成与穿透的通道电连接的第二外部连接端子,并且进一步通过在具有内装芯片的基板上安装另一个具有内装芯片的基板,在其上安装具有内装芯片的另一个基板的具有内装芯片的基板可以与第三个基板连接。
根据本发明,可以获得具有内装芯片的基板和用于制造该基板的方法,其中具有内装芯片的基板的厚度减小,并且在具有内装芯片的基板上安装另一个具有内装芯片的基板,由此,具有内装芯片的基板可以进一步安装在另一个基板上(例如主板)。
附图说明
结合附图,本发明的其它目的和进一步特征将更加明显,其中:
图1是示出具有内装芯片的基板的图;
图2是根据本发明的实施方式的具有内装芯片的基板的横截面图;
图3是示出根据本发明的实施方式的具有内装芯片的基板的制造工艺的图;
图4是示出根据本发明的实施方式的具有内装芯片的基板的制造工艺的图;
图5是示出根据本发明的实施方式的具有内装芯片的基板的制造工艺的图;
图6是示出根据本发明的实施方式的具有内装芯片的基板的制造工艺的图;
图7是示出根据本发明的实施方式的具有内装芯片的基板的制造工艺的图;
图8是示出根据本发明的实施方式的具有内装芯片的基板的制造工艺的图;
图9是示出根据本发明的实施方式的具有内装芯片的基板的制造工艺的图;
图10是示出根据本发明的实施方式的具有内装芯片的基板的制造工艺的图;
图11是示出根据本发明的实施方式的具有内装芯片的基板的制造工艺的图;
图12是示出根据本发明的实施方式的具有内装芯片的基板的制造工艺的图;
图13是示出根据本发明的实施方式的具有内装芯片的基板的制造工艺的图;
图14是示出根据本发明的实施方式的具有内装芯片的基板的制造工艺的图;
图15是示出根据本发明的实施方式的具有内装芯片的基板的制造工艺的图;
图16是示出根据本发明的实施方式的具有内装芯片的基板的制造工艺的图;
图17是示出根据本发明的实施方式的具有内装芯片的基板的制造工艺的图;
图18是示出根据本发明的实施方式的具有内装芯片的基板的制造工艺的图。
具体实施方式
下面参考附图描述本发明的实施例。
【实施例】
首先参考图2具体描述具有根据本发明的实施方式的内装芯片的基板30。图2是根据本发明的实施方式的具有内装芯片的基板的横截面图。具有内装芯片的基板30由半导体芯片33、树脂件31、通道41、穿透的通道44、布线46、阻焊剂48和61、Ni/Au层50和55、第一外部连接端子53、第二外部连接端子54和焊料球59构成。
半导体芯片33由半导体芯片主体34和电极焊盘37构成。在半导体芯片主体34的一侧上设置电极焊盘37。作为用于电极焊盘37的材料,例如可以使用Al。在电极焊盘37上形成Ni层38。当Al用作电极焊盘37的材料时,在电极焊盘37上进行锌酸盐处理,在处理后,形成Ni层38。Ni层38用作阻止膜,以形成用于在电极焊盘37上设置通道41的开口部分71(图5)。Ni层38的厚度例如为5到10微米。而且,通过在电极焊盘37上设置Ni层38,当形成开口部分71时可以阻止电极焊盘37被损坏。
锌酸盐处理是在Al上镀锌,这很容易氧化,以便阻止Al再氧化。因此,通过在由Al构成的电极焊盘37上进行锌酸盐处理,以便阻止电极焊盘37再氧化,可以提高在电极焊盘37上形成的金属层(在本实施方式中,Ni层38)与电极焊盘37的粘结力。
设置图2所示的半导体芯片33,以使半导体芯片主体34的电极焊盘37附着在其上的一侧为上侧。而且,树脂件31覆盖半导体芯片主体34的上侧(设置电极焊盘37的一侧)、半导体芯片主体34的侧面和电极焊盘37。
包含半导体芯片33的树脂件31为具有内装芯片的基板30的基础材料。树脂件31由树脂和60%到90%重量比的球状填充物构成。作为球状填充物的材料,例如可以使用SiO2。球状填充物材料的直径为例如1到5微米。作为与球状填充物混和的树脂,可以使用例如环氧树脂,包括环氧树脂和聚酰胺亚胺(PAI)树脂的混和树脂,和聚酰胺亚胺(PAI)树脂。
因此,通过使用具有60到90%重量比的球状填充物的树脂件31,与常规的树脂件17比较,在玻璃转变温度附近的温度的弹性系数变高,并且在低于玻璃转变温度的温度热膨胀系数变低,因此可以控制树脂件31的弯曲,且不必设置支撑板11和树脂层23,而它们对于具有内装芯片的常规基板10是需要的。因此,可以减小具有内装芯片的基板30的厚度。而且,因为树脂被球状填充物高度填充,树脂件31的流动性和在硬化之后的树脂件31的表面光洁度提高,在半导体芯片33和树脂件31之间没有间隙,因此可以将半导体芯片33准确地埋入树脂件31中。而且,当在树脂件31上形成开口部分71(如图5所示)来形成通道41时,并且当在树脂件31上形成通孔72(如图5所示)来形成穿透的通道44时,激光和蚀刻处理提高了开口部分71和通孔72的加工精度。
在玻璃转变温度附近的温度通过将树脂件31的弹性系数保持在1GPa到3GPa的范围内(在玻璃转变温度附近的温度常规树脂件的弹性系数小于1GPa),当外力作用于具有内装芯片的基板时,可以防止具有内装芯片的基板变形(包括弯曲)。
在低于玻璃转变温度的温度通过将具有内装芯片的基板的热膨胀系数保持在10ppm到15ppm的范围内(在低于玻璃转变温度的温度常规树脂件17的热膨胀系数大约为100ppm,且在各自的x、y、z方向可以观察到分散),在具有内装芯片的基板30的制造工艺中,当对具有内装芯片的基板30上进行热处理时,可以防止具有内装芯片的基板30经历热变形(包括弯曲)。而且,与常规的树脂件17比较,可以减小在x、y、z方向上树脂件31热膨胀系数的分散。应该注意,单词“ppm”是“每百万份数”的缩写。
根据本实施方式,环氧树脂用作树脂,SiO2用作球状填充物,由此,树脂件31由环氧树脂和作为球状填充物的85%重量比的SiO2构成,并且这样测量弹性系数和热膨胀系数。结果,获得了2GPa的弹性系数(当在230℃的温度测量时)和12ppm的热膨胀系数。应该注意,动态粘度弹性测量装置(DMA)用于测量上面的弹性系数,热机械分析装置(TMA)用于测量热膨胀系数(当在210℃下的温度测量时)。而且,用于测量的树脂件31的玻璃转变温度为215℃,在这种情况下,“在玻璃转变温度附近的温度”是200到215℃。
根据上面测量的结果,通过使用本实施方式的树脂件31,在玻璃转变温度附近的温度的弹性系数可以提高到大于常规树脂件17的弹性系数,在低于玻璃转变温度的温度热膨胀系数可以减小到低于常规树脂件17的热膨胀系数。
设置在树脂件31中的通道41由籽晶层43和铜层42构成。作为籽晶层43,例如,可以使用通过无电镀方法和CVD方法形成的Cu层。而且,至于Cu层42,例如,可以通过无电镀方法形成Cu层42。至于通道41,通道41的一边通过Ni层38与电极焊盘37电连接,通道41的另一边与布线46连接。
用于穿透树脂件31的穿透的通道44由籽晶层43和Cu层42构成。从树脂件31的上表面31a露出的穿透的通道44的边缘与布线46连接。
通过第一外部连接端子53,布线46连接通道41和穿透的通道44。通过布线46,第一外部连接端子53与通道41和穿透的通道44电连接。与布线46成为一体的第一外部连接端子53由例如Cu层构成。
设置具有露出第一外部连接端子53的开口部分49的阻焊剂48,以便覆盖树脂件31的上表面31a和布线46。阻焊剂48用作对布线46的保护。
在第一外部连接端子53上设置的Ni/Au层50由Ni层51和Au层52构成。Ni/Au层50防止包含在第一外部连接层53中的Cu扩散,并改善与焊料球59的粘着(附图被省略)。Ni/Au层50与具有内装芯片的另一基板100连接。Ni层51的厚度例如为3微米,Au层52的厚度例如为0.1微米。而且,可以通过例如无电镀方法形成Au层52和Ni层51。
如上所述,根据本实施方式的具有内装芯片的基板30使用树脂件31,其中使用球状填充物高度填充树脂件31,在玻璃转变温度附近的温度的弹性系数是高的,且在低于玻璃转变温度的温度热膨胀系数是低的。这样,不必在具有内装芯片的基板30上设置支撑板(附图被省略)来支撑其中包含半导体芯片33的树脂件31。因此,如图2所示,从树脂件31的下表面31b露出的穿透的通道44的边缘可以连接到焊料球59。从树脂件31的下表面31b露出的穿透的通道44的边缘为第二外部连接端子54。通过焊料球59,外部连接端子54将连接到另一个基板,例如母板。
因此,在具有内装芯片的基板30中,在树脂件31的上表面31a(树脂件31的一侧)上设置第一外部连接端子53,在树脂件31的下表面31b(树脂件31的另一侧)上设置第二外部连接端子,这样将具有内装芯片的另一基板100安装在具有内装芯片的基板30上,并且安装其它具有内装芯片的基板100的具有内装芯片的基板30可以与另一个基板连接(例如母板)。
设置具有露出第二外部连接端子54的开口部分58的阻焊剂61以覆盖树脂件31的下表面31b和半导体芯片33的下边缘。在第二外部连接端子54上设置的Ni/Au层55由Ni层56和Au层57构成。Ni/Au层55防止包含在第二外部连接端子54中的Cu扩散入焊料球59,并改善了与焊料球59的粘着。焊料球59连接到Au层57。Ni层56的厚度例如为3微米,Au层57的厚度例如为0.1微米。而且,可以通过例如无电镀方法形成Ni层56和Au层57。
如上所述,通过使用具有60%到90%重量比的球状填充物的树脂件31,与常规树脂件17相比,在玻璃转变温度附近的温度的弹性系数变高,且在低于玻璃转变温度的温度下热膨胀系数变低,由此,可以减小具有内装芯片的基板30的厚度。而且,在树脂件31的上表面31a(树脂件31的一侧)上设置第一外部连接端子53,在树脂件31的下表面31b(树脂件31的另一侧)上设置第二外部连接端子;这样将具有内装芯片的其它基板100安装在具有内装芯片的基板30上,并且安装其它具有内装芯片的基板100的具有内装芯片的基板30可以与另一个基板连接(例如母板)。
接下来参考图3至18具体描述制造具有内装芯片的基板30的方法。图3-18是示出根据本发明的实施方式的具有内装芯片的基板的制造工艺的图。
首先,如图3所示,在预先进行锌酸盐处理的电极焊盘37(用Al作材料)上形成Ni层38。在由Al构成的电极焊盘37上进行锌酸盐处理,由此,使电极焊盘免受再氧化,以便改善在电极焊盘37和在电极焊盘37上形成的金属层(在本实施方式中,Ni层38)之间的粘着。当通过激光处理在树脂件31中形成开口部分71而用于设置通道41时,Ni层38用作阻止膜。
在上述工艺之后,在半导体芯片主体34的侧面不设置电极焊盘37的地方涂布粘结剂65,半导体芯片33粘结在设置铜箔67的支撑板66上(半导体芯片提供步骤)。当形成通孔72用于设置穿透的通道44时,铜箔67用作阻止膜。
接下来,如图4所示,由环氧树脂和作为球状填充物的60%到90%重量比的SiO2构成的膜树脂件31与设置在支撑板66和铜箔67上的半导体芯片33层叠,并且根据需要,通过加压和加热使树脂件31硬化(树脂件提供步骤)。树脂件31的厚度M1例如为70微米。
接下来,如图5所示,形成穿透树脂件31的通孔72和露出Ni层38的开口部分71。开口部分71用于设置通道41。通孔72用于设置穿透的通道44。通孔72的直径为例如50微米。而且,穿透的通道44的直径为例如100微米。此外,当通过激光处理形成开口部分71和通孔72时,铜箔67和Ni层38用作阻止层。
接下来,如图6所示,形成在树脂件31的上侧31a上的开口部分71、通孔72和籽晶层43。作为籽晶层43,例如,可以使用通过无电镀方法和CVD方法形成的Cu层(厚度为1到2微米)。
接下来,如图7所示,籽晶层43用作电源,根据电解电镀方法用Cu层42填充开口部分71和通孔72。将电解电镀进行两次。因此,进行两次电解电镀是为了防止在埋入开口部分71和通孔72的Cu层42中的空洞(不良埋设)。
接下来,如图8所示,通过抛光打磨附件和CMP装置将在树脂件31上的Cu层42磨平。因此,在开口部分71中形成包括籽晶层43和Cu层42的通道41,并且在通孔72中形成包括籽晶层43和Cu层42的穿透的通道44(穿透的通道形成步骤)。
接下来,如图9所示,在图8示出的结构上形成具有开口部分75的干膜抗蚀剂74。开口部分75露出形成布线46的部分46A和形成第一外部连接端子53的部分53A。在形成干膜抗蚀剂74之后,根据电解电镀方法生长在开口部分75上的层,形成连接到相应的通道41和穿透的通道44的布线46,并且形成第一外部连接端子53以便与布线46成为一体(第一外部连接端子形成步骤)。在形成布线46和第一外部连接端子53之后,通过抗蚀剂腐蚀处理腐蚀干抗蚀剂膜74。
接下来,如图10所示,在籽晶层43上设置具有露出第一外部连接端子53的开口部分78的干膜抗蚀剂77以便覆盖布线46。然后,如图11所示,通过在从开口部分78露出的第一外部连接端子53上依次形成Ni层51和Au层52,形成Ni/Au层50。在形成Ni/Au层50之后通过抗蚀剂腐蚀处理腐蚀干膜抗蚀剂77。
接下来,如图12所示,形成干膜抗蚀剂81以覆盖布线46和Ni/Au层50。然后,如图13所示,通过蚀刻腐蚀在树脂件31的上表面31a上形成的籽日晶层43,以便露出树脂件31的上表面31a。在腐蚀籽晶层43后,通过抗蚀剂腐蚀处理腐蚀干膜抗蚀剂81。
接下来,如图14所示,在布线46和树脂件31上形成具有露出Ni/Au层50的开口部分49的阻焊剂48。然后,如图15所示,除去支撑板66(支撑板除去步骤)。可以通过例如抛光打磨的方法除去支撑板66。接下来,如图16所示,除去铜箔67。因此,露出第二外部连接端子54和树脂件31的下表面31b(第二外部连接端子形成步骤)。可以通过例如使用CMP装置打磨铜箔67的方法除去铜箔67。
接下来,如图17所示,形成具有露出第二外部连接端子54的开口部分58的阻焊剂61。然后,根据无电镀方法,依次层叠Ni层56和Au层57以形成Ni/Au层55。
因此,如图18所示,通过在Au层57上设置焊料球59,制造具有内装芯片的基板30。应该注意,具有根据本实施方式的内装芯片的基板30由焊料球59和阻焊剂61构成;然而,焊料球59和阻焊剂61的使用是可选择的,因此根据需要设置焊料球59和阻焊剂61。
如上所述,通过制造具有包含树脂件31的内装芯片的基板30,该树脂件31由树脂和60%到90%重量比的球状填充物构成,与常规的树脂件17相比,在玻璃转变温度附近的温度的弹性系数变高,并且在低于玻璃转变温度的温度热膨胀系数变低,因而不必设置支撑板66和在支撑板66上的树脂层。因此可以省去支撑板66以减小具有内装芯片的基板30的厚度。而且,因为不必设置支撑板66,所以可以在树脂件31的两面31a和31b上设置外部连接端子(第一和第二外部连接端子53和54)。所以,可以在具有内装芯片的基板30上安装具有内装芯片的另一个基板100,并且安装另一个基板100的具有内装芯片的基板30可以连接到另一个基板(例如母板)。
此外,本发明不限于这些实施方式,但在不脱离本发明的范围的情况下可以进行各种变化和修改。应该注意,可通过蚀刻形成开口部分71和通孔72。
根据本发明,可以减小具有内装芯片的基板的厚度。而且本发明可以用于具有内装芯片的基板,通过在树脂件的两侧设置外部连接端子,该基板比常规基板可以连接更多的基板(例如母板)。本发明也可以用于上述基板的制造方法。

Claims (7)

1.一种具有内装半导体芯片的基板,其特征在于包括:
内装半导体芯片;
将所述的内装半导体芯片包含在其中的树脂件;以及
外部连接端子;其中
所述的树脂件包含树脂和60%到90%重量比的球状填充物,
所述外部连接端子提供在所述树脂件的上下主表面上。
2.如权利要求1所述的具有内装半导体芯片的基板,其中
所述的树脂件在玻璃转变温度具有1GPa到3GPa的弹性系数。
3.如权利要求1所述的具有内装半导体芯片的基板,其中
所述的树脂件在低于玻璃转变温度的温度具有10ppm到15ppm的热膨胀系数。
4.如权利要求1所述的具有内装半导体芯片的基板,其中
在所述的树脂件的两侧设置所述的外部连接端子。
5.如权利要求1所述的具有内装半导体芯片的基板,其中
所述内装半导体芯片具有连接到所述的外部连接端子的电极焊盘;以及
Al用作所述的电极焊盘的材料,并且在所述的电极焊盘上进行锌酸盐处理以在所述的电极焊盘上形成Ni层。
6.一种用于制造具有内装半导体芯片的基板的方法,该基板包括内装半导体芯片、将所述的内装半导体芯片包含在其中的树脂件和外部连接端子,其中所述的树脂件包含树脂和60%到90%重量比的球状填充物,其特征在于包括下列步骤:
在支撑板上设置所述的内装半导体芯片;
在所述的支撑板上设置所述的树脂件以覆盖所述的内装半导体芯片;以及
除去所述的支撑板。
7.如权利要求6所述的用于制造具有内装半导体芯片的基板的方法,进一步包括下列步骤:
形成穿透所述的树脂件的穿透的通道;
在所述的树脂件的一侧形成第一外部连接端子,其中所述的第一外部连接端子与所述的穿透的通道电连接;以及
在所述的树脂件的另一侧形成第二外部连接端子,其中所述的第二外部连接端子与所述的穿透的通道电连接。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106057749A (zh) * 2015-04-10 2016-10-26 株式会社吉帝伟士 半导体封装件及其制造方法

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4428337B2 (ja) * 2005-12-02 2010-03-10 ソニー株式会社 半導体装置の製造方法
KR100770874B1 (ko) 2006-09-07 2007-10-26 삼성전자주식회사 매설된 집적회로를 구비한 다층 인쇄회로기판
KR100823699B1 (ko) * 2006-11-29 2008-04-21 삼성전자주식회사 플립칩 어셈블리 및 그 제조 방법
US8178982B2 (en) * 2006-12-30 2012-05-15 Stats Chippac Ltd. Dual molded multi-chip package system
JP2008277639A (ja) * 2007-05-02 2008-11-13 Casio Comput Co Ltd 半導体装置およびその製造方法
US9610758B2 (en) 2007-06-21 2017-04-04 General Electric Company Method of making demountable interconnect structure
US9953910B2 (en) * 2007-06-21 2018-04-24 General Electric Company Demountable interconnect structure
KR100929464B1 (ko) * 2007-12-21 2009-12-02 주식회사 동부하이텍 반도체칩, 이의 제조 방법 및 반도체칩 적층 패키지
JP4787296B2 (ja) 2008-07-18 2011-10-05 Tdk株式会社 半導体内蔵モジュール及びその製造方法
US8390083B2 (en) 2009-09-04 2013-03-05 Analog Devices, Inc. System with recessed sensing or processing elements
EP2580776A1 (en) * 2010-06-11 2013-04-17 Nec Corporation Method of redistributing functional element
JP5578962B2 (ja) * 2010-06-24 2014-08-27 新光電気工業株式会社 配線基板
US9407997B2 (en) 2010-10-12 2016-08-02 Invensense, Inc. Microphone package with embedded ASIC
JP2012134270A (ja) * 2010-12-21 2012-07-12 Shinko Electric Ind Co Ltd 半導体装置及びその製造方法
JP2012256675A (ja) * 2011-06-08 2012-12-27 Shinko Electric Ind Co Ltd 配線基板、半導体装置及びその製造方法
US9093416B2 (en) * 2011-11-28 2015-07-28 Infineon Technologies Ag Chip-package and a method for forming a chip-package
CN103137613B (zh) * 2011-11-29 2017-07-14 华进半导体封装先导技术研发中心有限公司 制备有源芯片封装基板的方法
US9730329B2 (en) 2011-11-29 2017-08-08 Institute of Microelectronics, Chinese Academy of Sciences Active chip package substrate and method for preparing the same
US9847462B2 (en) 2013-10-29 2017-12-19 Point Engineering Co., Ltd. Array substrate for mounting chip and method for manufacturing the same
WO2015087705A1 (ja) * 2013-12-10 2015-06-18 ソニー株式会社 半導体装置、固体撮像素子、撮像装置および電子機器、並びにそれらの製造方法
US9673171B1 (en) 2014-03-26 2017-06-06 STATS ChipPAC Pte. Ltd. Integrated circuit packaging system with coreless substrate and method of manufacture thereof
DE102014118462A1 (de) * 2014-12-11 2016-06-16 At&S Austria Technologie & Systemtechnik Aktiengesellschaft Semiflexible Leiterplatte mit eingebetteter Komponente
DE102014118464A1 (de) * 2014-12-11 2016-06-16 At&S Austria Technologie & Systemtechnik Aktiengesellschaft Leiterplatte mit einem asymmetrischen Schichtenaufbau
US9666558B2 (en) 2015-06-29 2017-05-30 Point Engineering Co., Ltd. Substrate for mounting a chip and chip package using the substrate
US10068853B2 (en) * 2016-05-05 2018-09-04 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and method of fabricating the same
KR20230165396A (ko) * 2016-05-25 2023-12-05 가부시끼가이샤 레조낙 봉지 구조체 및 그의 제조 방법, 및 봉지재
CN110800102B (zh) 2017-06-30 2023-08-15 株式会社村田制作所 电子部件模块及其制造方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5656250A (en) * 1994-06-27 1997-08-12 Jiro Hiraishi, Director-General, Agency Of Industrial Science And Technology Three-dimensional network structure comprising spherical silica particles and method of producing same
US6166433A (en) * 1998-03-26 2000-12-26 Fujitsu Limited Resin molded semiconductor device and method of manufacturing semiconductor package
US6255739B1 (en) * 1998-12-02 2001-07-03 Kabushiki Kaisha Toshiba Semiconductor device
US20040113215A1 (en) * 2002-07-31 2004-06-17 Kyocera Corporation Surface acoustic wave device and method for manufacturing same

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3965277A (en) * 1972-05-09 1976-06-22 Massachusetts Institute Of Technology Photoformed plated interconnection of embedded integrated circuit chips
US6348728B1 (en) 2000-01-28 2002-02-19 Fujitsu Limited Semiconductor device having a plurality of semiconductor elements interconnected by a redistribution layer
US20020110956A1 (en) * 2000-12-19 2002-08-15 Takashi Kumamoto Chip lead frames
TW511405B (en) * 2000-12-27 2002-11-21 Matsushita Electric Ind Co Ltd Device built-in module and manufacturing method thereof
CA2350747C (en) * 2001-06-15 2005-08-16 Ibm Canada Limited-Ibm Canada Limitee Improved transfer molding of integrated circuit packages
JP3910045B2 (ja) * 2001-11-05 2007-04-25 シャープ株式会社 電子部品内装配線板の製造方法
US7394663B2 (en) * 2003-02-18 2008-07-01 Matsushita Electric Industrial Co., Ltd. Electronic component built-in module and method of manufacturing the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5656250A (en) * 1994-06-27 1997-08-12 Jiro Hiraishi, Director-General, Agency Of Industrial Science And Technology Three-dimensional network structure comprising spherical silica particles and method of producing same
US6166433A (en) * 1998-03-26 2000-12-26 Fujitsu Limited Resin molded semiconductor device and method of manufacturing semiconductor package
US6255739B1 (en) * 1998-12-02 2001-07-03 Kabushiki Kaisha Toshiba Semiconductor device
US20040113215A1 (en) * 2002-07-31 2004-06-17 Kyocera Corporation Surface acoustic wave device and method for manufacturing same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106057749A (zh) * 2015-04-10 2016-10-26 株式会社吉帝伟士 半导体封装件及其制造方法

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