TW200614900A - A substrate having a built-in chip and external connection terminals on both sides and a method for manufacturing the same - Google Patents

A substrate having a built-in chip and external connection terminals on both sides and a method for manufacturing the same

Info

Publication number
TW200614900A
TW200614900A TW094131451A TW94131451A TW200614900A TW 200614900 A TW200614900 A TW 200614900A TW 094131451 A TW094131451 A TW 094131451A TW 94131451 A TW94131451 A TW 94131451A TW 200614900 A TW200614900 A TW 200614900A
Authority
TW
Taiwan
Prior art keywords
built
external connection
connection terminals
substrate
chip
Prior art date
Application number
TW094131451A
Other languages
English (en)
Inventor
Takaharu Yamano
Tadashi Arai
Yoshihiro Machida
Original Assignee
Shinko Electric Ind Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Ind Co filed Critical Shinko Electric Ind Co
Publication of TW200614900A publication Critical patent/TW200614900A/zh

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Classifications

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    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
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    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
TW094131451A 2004-10-22 2005-09-13 A substrate having a built-in chip and external connection terminals on both sides and a method for manufacturing the same TW200614900A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004308558A JP2006120943A (ja) 2004-10-22 2004-10-22 チップ内蔵基板及びその製造方法

Publications (1)

Publication Number Publication Date
TW200614900A true TW200614900A (en) 2006-05-01

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TW094131451A TW200614900A (en) 2004-10-22 2005-09-13 A substrate having a built-in chip and external connection terminals on both sides and a method for manufacturing the same

Country Status (6)

Country Link
US (1) US7312536B2 (zh)
EP (1) EP1650798A3 (zh)
JP (1) JP2006120943A (zh)
KR (1) KR20060051422A (zh)
CN (1) CN100446225C (zh)
TW (1) TW200614900A (zh)

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KR100823699B1 (ko) * 2006-11-29 2008-04-21 삼성전자주식회사 플립칩 어셈블리 및 그 제조 방법
US8178982B2 (en) 2006-12-30 2012-05-15 Stats Chippac Ltd. Dual molded multi-chip package system
JP2008277639A (ja) * 2007-05-02 2008-11-13 Casio Comput Co Ltd 半導体装置およびその製造方法
US9610758B2 (en) * 2007-06-21 2017-04-04 General Electric Company Method of making demountable interconnect structure
US9953910B2 (en) 2007-06-21 2018-04-24 General Electric Company Demountable interconnect structure
KR100929464B1 (ko) * 2007-12-21 2009-12-02 주식회사 동부하이텍 반도체칩, 이의 제조 방법 및 반도체칩 적층 패키지
JP4787296B2 (ja) * 2008-07-18 2011-10-05 Ｔｄｋ株式会社 半導体内蔵モジュール及びその製造方法
US8390083B2 (en) * 2009-09-04 2013-03-05 Analog Devices, Inc. System with recessed sensing or processing elements
JP2013528318A (ja) * 2010-06-11 2013-07-08 日本電気株式会社 機能素子の再配線方法
JP5578962B2 (ja) * 2010-06-24 2014-08-27 新光電気工業株式会社 配線基板
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US7312536B2 (en) 2007-12-25
EP1650798A2 (en) 2006-04-26
JP2006120943A (ja) 2006-05-11
CN100446225C (zh) 2008-12-24
US20060087045A1 (en) 2006-04-27
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