JP2006253430A - 半導体装置およびその製造方法 - Google Patents

半導体装置およびその製造方法 Download PDF

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Publication number
JP2006253430A
JP2006253430A JP2005068362A JP2005068362A JP2006253430A JP 2006253430 A JP2006253430 A JP 2006253430A JP 2005068362 A JP2005068362 A JP 2005068362A JP 2005068362 A JP2005068362 A JP 2005068362A JP 2006253430 A JP2006253430 A JP 2006253430A
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JP
Japan
Prior art keywords
wiring board
semiconductor chip
wire
substrate
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2005068362A
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English (en)
Japanese (ja)
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JP2006253430A5 (enExample
Inventor
Hirotaka Nishizawa
裕孝 西沢
Tamaki Wada
環 和田
Kenji Osawa
賢治 大沢
Junichiro Osako
潤一郎 大迫
Michiaki Sugiyama
道昭 杉山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Technology Corp
Original Assignee
Renesas Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Technology Corp filed Critical Renesas Technology Corp
Priority to JP2005068362A priority Critical patent/JP2006253430A/ja
Priority to TW095105771A priority patent/TW200731140A/zh
Priority to CNA2006100568496A priority patent/CN1832166A/zh
Priority to KR1020060022185A priority patent/KR20060097661A/ko
Priority to US11/371,929 priority patent/US7352588B2/en
Publication of JP2006253430A publication Critical patent/JP2006253430A/ja
Priority to US12/037,588 priority patent/US20080153205A1/en
Publication of JP2006253430A5 publication Critical patent/JP2006253430A5/ja
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49855—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers for flat-cards, e.g. credit cards
    • A—HUMAN NECESSITIES
    • A47—FURNITURE; DOMESTIC ARTICLES OR APPLIANCES; COFFEE MILLS; SPICE MILLS; SUCTION CLEANERS IN GENERAL
    • A47G—HOUSEHOLD OR TABLE EQUIPMENT
    • A47G25/00—Household implements used in connection with wearing apparel; Dress, hat or umbrella holders
    • A47G25/14—Clothing hangers, e.g. suit hangers
    • A47G25/20—Clothing hangers, e.g. suit hangers with devices for preserving the shape of the clothes
    • A—HUMAN NECESSITIES
    • A47—FURNITURE; DOMESTIC ARTICLES OR APPLIANCES; COFFEE MILLS; SPICE MILLS; SUCTION CLEANERS IN GENERAL
    • A47G—HOUSEHOLD OR TABLE EQUIPMENT
    • A47G25/00—Household implements used in connection with wearing apparel; Dress, hat or umbrella holders
    • A47G25/14—Clothing hangers, e.g. suit hangers
    • A47G25/48—Hangers with clamps or the like, e.g. for trousers or skirts
    • A47G25/50—Hooks on hangers for supporting trousers or skirts
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/0772—Physical layout of the record carrier
    • G06K19/07732—Physical layout of the record carrier the record carrier having a housing or construction similar to well-known portable memory devices, such as SD cards, USB or memory sticks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01057—Lanthanum [La]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/145—Arrangements wherein electric components are disposed between and simultaneously connected to two planar printed circuit boards, e.g. Cordwood modules

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Theoretical Computer Science (AREA)
  • Credit Cards Or The Like (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
JP2005068362A 2005-03-11 2005-03-11 半導体装置およびその製造方法 Withdrawn JP2006253430A (ja)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP2005068362A JP2006253430A (ja) 2005-03-11 2005-03-11 半導体装置およびその製造方法
TW095105771A TW200731140A (en) 2005-03-11 2006-02-21 A semiconductor device and a method for manufacturing the same
CNA2006100568496A CN1832166A (zh) 2005-03-11 2006-03-09 半导体器件及其制造方法
KR1020060022185A KR20060097661A (ko) 2005-03-11 2006-03-09 반도체 장치 및 그 제조 방법
US11/371,929 US7352588B2 (en) 2005-03-11 2006-03-10 Semiconductor device and a method for manufacturing the same
US12/037,588 US20080153205A1 (en) 2005-03-11 2008-02-26 Semiconductor device and a method for manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005068362A JP2006253430A (ja) 2005-03-11 2005-03-11 半導体装置およびその製造方法

Publications (2)

Publication Number Publication Date
JP2006253430A true JP2006253430A (ja) 2006-09-21
JP2006253430A5 JP2006253430A5 (enExample) 2008-04-24

Family

ID=36971628

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005068362A Withdrawn JP2006253430A (ja) 2005-03-11 2005-03-11 半導体装置およびその製造方法

Country Status (5)

Country Link
US (2) US7352588B2 (enExample)
JP (1) JP2006253430A (enExample)
KR (1) KR20060097661A (enExample)
CN (1) CN1832166A (enExample)
TW (1) TW200731140A (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2021009998A (ja) * 2019-07-02 2021-01-28 オリエント セミコンダクター エレクトロニクス，リミテッドＯｒｉｅｎｔ Ｓｅｍｉｃｏｎｄｕｃｔｏｒ Ｅｌｅｃｔｒｏｎｉｃｓ，Ｌｉｍｉｔｅｄ 半導体パッケージおよびその製造方法
JP7166527B2 (ja) 2016-11-04 2022-11-08 スマート パッケージング ソリューションズ チップカード用電子モジュールの製造方法

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JP4886308B2 (ja) * 2005-09-16 2012-02-29 株式会社東芝 Ｕｓｂメモリ装置
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KR20100109243A (ko) * 2009-03-31 2010-10-08 삼성전자주식회사 반도체 패키지
TWM362572U (en) * 2009-04-13 2009-08-01 Phytrex Technology Corp Signal convertor
USD686214S1 (en) * 2011-07-28 2013-07-16 Lifenexus, Inc. Smartcard with iChip contact pad
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US8649820B2 (en) 2011-11-07 2014-02-11 Blackberry Limited Universal integrated circuit card apparatus and related methods
EP2605188A1 (fr) 2011-12-14 2013-06-19 Gemalto SA Procédé de fabrication de cartes à puce
EP2608114A1 (fr) * 2011-12-19 2013-06-26 Gemalto SA Procédé de fabrication d'un module à puce de circuit intégré protégé par pastille
US8936199B2 (en) 2012-04-13 2015-01-20 Blackberry Limited UICC apparatus and related methods
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USD729808S1 (en) * 2013-03-13 2015-05-19 Nagrastar Llc Smart card interface
TWD164807S (zh) * 2013-08-06 2014-12-11 璨圓光電股份有限公司 半導體發光元件之部分
CN104021415A (zh) * 2014-06-27 2014-09-03 南通富士通微电子股份有限公司 电子标签
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USD780763S1 (en) * 2015-03-20 2017-03-07 Nagrastar Llc Smart card interface
USD864968S1 (en) 2015-04-30 2019-10-29 Echostar Technologies L.L.C. Smart card interface
USD783621S1 (en) * 2015-08-25 2017-04-11 Samsung Electronics Co., Ltd. Memory card
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CN109948767B (zh) * 2018-02-01 2024-08-09 华为技术有限公司 存储卡和终端
FR3094137A1 (fr) * 2019-03-20 2020-09-25 Stmicroelectronics (Grenoble 2) Sas Boîtier électronique comportant des pistes contactant des fils
CN112242388A (zh) * 2019-07-18 2021-01-19 华泰电子股份有限公司 半导体封装件及其制法
CN111863739B (zh) * 2020-07-29 2022-04-08 深圳市邦测检测技术有限公司 一种rf射频通信模块及其制造方法
EP4084063A1 (en) * 2021-04-30 2022-11-02 Infineon Technologies Austria AG Semiconductor module with bond wire loop exposed from a moulded body and method for fabricating the same
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7166527B2 (ja) 2016-11-04 2022-11-08 スマート パッケージング ソリューションズ チップカード用電子モジュールの製造方法
JP2021009998A (ja) * 2019-07-02 2021-01-28 オリエント セミコンダクター エレクトロニクス，リミテッドＯｒｉｅｎｔ Ｓｅｍｉｃｏｎｄｕｃｔｏｒ Ｅｌｅｃｔｒｏｎｉｃｓ，Ｌｉｍｉｔｅｄ 半導体パッケージおよびその製造方法

Also Published As

Publication number Publication date
KR20060097661A (ko) 2006-09-14
US20060205280A1 (en) 2006-09-14
CN1832166A (zh) 2006-09-13
TW200731140A (en) 2007-08-16
US7352588B2 (en) 2008-04-01
US20080153205A1 (en) 2008-06-26

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