JP2006054017A - メモリディジット線のキャパシタ支持によるプレチャージ - Google Patents
メモリディジット線のキャパシタ支持によるプレチャージ Download PDFInfo
- Publication number
- JP2006054017A JP2006054017A JP2004236245A JP2004236245A JP2006054017A JP 2006054017 A JP2006054017 A JP 2006054017A JP 2004236245 A JP2004236245 A JP 2004236245A JP 2004236245 A JP2004236245 A JP 2004236245A JP 2006054017 A JP2006054017 A JP 2006054017A
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- circuit
- capacitor
- node
- conductive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 title claims abstract description 74
- 230000015654 memory Effects 0.000 title claims abstract description 31
- 238000000034 method Methods 0.000 claims abstract description 36
- 230000004044 response Effects 0.000 claims description 4
- 238000012546 transfer Methods 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 11
- 238000004088 simulation Methods 0.000 description 4
- 238000013459 approach Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000004513 sizing Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4094—Bit-line management or control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
- Electronic Switches (AREA)
- Logic Circuits (AREA)
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2004236245A JP2006054017A (ja) | 2004-08-13 | 2004-08-13 | メモリディジット線のキャパシタ支持によるプレチャージ |
| US10/958,936 US7177213B2 (en) | 2004-08-13 | 2004-10-05 | Capacitor supported precharging of memory digit lines |
| US11/642,810 US7423923B2 (en) | 2004-08-13 | 2006-12-19 | Capacitor supported precharging of memory digit lines |
| US12/228,459 US7663952B2 (en) | 2004-08-13 | 2008-08-12 | Capacitor supported precharging of memory digit lines |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2004236245A JP2006054017A (ja) | 2004-08-13 | 2004-08-13 | メモリディジット線のキャパシタ支持によるプレチャージ |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2006054017A true JP2006054017A (ja) | 2006-02-23 |
| JP2006054017A5 JP2006054017A5 (enExample) | 2007-09-27 |
Family
ID=35799774
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2004236245A Pending JP2006054017A (ja) | 2004-08-13 | 2004-08-13 | メモリディジット線のキャパシタ支持によるプレチャージ |
Country Status (2)
| Country | Link |
|---|---|
| US (3) | US7177213B2 (enExample) |
| JP (1) | JP2006054017A (enExample) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006054017A (ja) * | 2004-08-13 | 2006-02-23 | Micron Technology Inc | メモリディジット線のキャパシタ支持によるプレチャージ |
| US8282667B2 (en) * | 2009-06-05 | 2012-10-09 | Entellus Medical, Inc. | Sinus dilation catheter |
| US8872247B2 (en) * | 2009-11-04 | 2014-10-28 | Micron Technology, Inc. | Memory cells having a folded digit line architecture |
| US9224464B2 (en) * | 2014-02-10 | 2015-12-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Memory circuit and related method |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63183686A (ja) * | 1987-01-26 | 1988-07-29 | Nec Corp | デイジツト線バランスレベル補正方法 |
| JPS63308792A (ja) * | 1987-06-10 | 1988-12-16 | Mitsubishi Electric Corp | 半導体記憶装置 |
| JPH023162A (ja) * | 1988-06-15 | 1990-01-08 | Nec Ic Microcomput Syst Ltd | 半導体記憶装置 |
| JPH02128395A (ja) * | 1988-11-08 | 1990-05-16 | Nec Ic Microcomput Syst Ltd | 半導体記憶装置 |
Family Cites Families (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US107932A (en) * | 1870-10-04 | Improvement in meat and vegetable slicers | ||
| KR890004762B1 (ko) * | 1986-11-21 | 1989-11-25 | 삼성전자 주식회사 | 고성능 디램을 위한 센스 증폭기 |
| JPH01171194A (ja) * | 1987-12-25 | 1989-07-06 | Nec Ic Microcomput Syst Ltd | 半導体記憶装置 |
| KR100203142B1 (ko) | 1996-06-29 | 1999-06-15 | 김영환 | 디램 |
| US5754486A (en) * | 1997-02-28 | 1998-05-19 | Micron Technology, Inc. | Self-test circuit for memory integrated circuits |
| US5856949A (en) * | 1997-03-07 | 1999-01-05 | Advanced Micro Devices, Inc. | Current sense amplifier for RAMs |
| US6094734A (en) * | 1997-08-22 | 2000-07-25 | Micron Technology, Inc. | Test arrangement for memory devices using a dynamic row for creating test data |
| JP2000195268A (ja) * | 1998-10-19 | 2000-07-14 | Toshiba Corp | 半導体記憶装置 |
| KR100355222B1 (ko) * | 1998-12-28 | 2003-02-19 | 삼성전자 주식회사 | 빠른감지속도와높은전원전압마진을갖는전류감지증폭기 |
| KR100299522B1 (ko) * | 1999-06-28 | 2001-11-01 | 박종섭 | 고속 센스 증폭기 |
| JP2001319472A (ja) * | 2000-05-10 | 2001-11-16 | Toshiba Corp | 半導体記憶装置 |
| US6304505B1 (en) * | 2000-05-22 | 2001-10-16 | Micron Technology Inc. | Differential correlated double sampling DRAM sense amplifier |
| JP3874655B2 (ja) | 2001-12-06 | 2007-01-31 | 富士通株式会社 | 半導体記憶装置、及び半導体記憶装置のデータアクセス方法 |
| US6587367B1 (en) * | 2002-03-19 | 2003-07-01 | Texas Instruments Incorporated | Dummy cell structure for 1T1C FeRAM cell array |
| JP2006054017A (ja) * | 2004-08-13 | 2006-02-23 | Micron Technology Inc | メモリディジット線のキャパシタ支持によるプレチャージ |
-
2004
- 2004-08-13 JP JP2004236245A patent/JP2006054017A/ja active Pending
- 2004-10-05 US US10/958,936 patent/US7177213B2/en not_active Expired - Lifetime
-
2006
- 2006-12-19 US US11/642,810 patent/US7423923B2/en not_active Expired - Lifetime
-
2008
- 2008-08-12 US US12/228,459 patent/US7663952B2/en not_active Expired - Lifetime
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63183686A (ja) * | 1987-01-26 | 1988-07-29 | Nec Corp | デイジツト線バランスレベル補正方法 |
| JPS63308792A (ja) * | 1987-06-10 | 1988-12-16 | Mitsubishi Electric Corp | 半導体記憶装置 |
| JPH023162A (ja) * | 1988-06-15 | 1990-01-08 | Nec Ic Microcomput Syst Ltd | 半導体記憶装置 |
| JPH02128395A (ja) * | 1988-11-08 | 1990-05-16 | Nec Ic Microcomput Syst Ltd | 半導体記憶装置 |
Also Published As
| Publication number | Publication date |
|---|---|
| US20060034113A1 (en) | 2006-02-16 |
| US7663952B2 (en) | 2010-02-16 |
| US7177213B2 (en) | 2007-02-13 |
| US20090003038A1 (en) | 2009-01-01 |
| US20070097764A1 (en) | 2007-05-03 |
| US7423923B2 (en) | 2008-09-09 |
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