JP2005523575A - Mram加工におけるトンネル接合部キャップ層、トンネル接合部ハードマスク、およびトンネル接合部スタック種膜の材質の組み合わせ - Google Patents
Mram加工におけるトンネル接合部キャップ層、トンネル接合部ハードマスク、およびトンネル接合部スタック種膜の材質の組み合わせ Download PDFInfo
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Abstract
Description
本発明のいくつかの好ましい実施形態では、抵抗記憶素子に対するエッチング加工を最適化する、材質の組み合わせを提供することにより、複数の技術的利点が得られる。好ましい上記一実施形態では、例えば窒化タングステン(WN)といった材料を、MRAM装置のトンネル接合部ハードマスク、またはキャップ層(cap layer)、および/またはトンネル接合部スタック種膜(tunnel junction stack seed layer)に対して使用する。
上記した本発明の特徴点をより明確にするために、以下に、添付図を用いた説明を行う。
図1は、記憶セルにアクセスするために各記憶セルの下にワード線、および上にビット線が配置されている、アレイ状に配置された磁気スタック記憶セルを有する従来技術のMRAM装置の斜視図である。
図2は、図1に示すMRAM装置の平面図である。
図3は、MRAM装置の断面図である。
図4〜図6は、本発明の実施形態に基づいたさまざまな製造段階のMRAM装置の断面図である。
図7は、ハードマスクを除去した本発明の実施形態の断面図である。
図8は、第1導電線上に酸化物層のないMRAM構造における、本発明の実施形態の交差点の断面図である。
従来技術のMRAM加工手順(process flows)および材質について説明し、続いて、本発明の好ましい実施形態およびそれぞれの有利な点について説明する。
磁気スタックの合計の厚みは、例えば数十ナノメートルである。交差点MRAM構造では、磁気スタックは、通常、2つの金属配線面の交差部(例えば、ある角度をなして配され、異なる方向へ延びている金属2(M2)層と金属3(M3)層との交差部)に配置されている。磁気スタックの上部および底部は、通常、M(n)およびM(n+1)配線層導電線とそれぞれ接触している。
導電線12および22は、メモリアレイ(memory array)10のワード線およびビット線として機能する。磁気スタック14の順序を逆にしてもよい。例えば、絶縁層18の上側にハード層20、下側にソフト層16を配してもよい。また、ワード線12およびビット線22は、磁気スタック14の上側・下側のいずれに配置されていてもよい。FETのようにMRAMを設計するために、例えば、酸化物層(図示せず)を、第1導電線12の間、または第2導電線22の間に配置してもよく、この酸化物層をパターン化してビアホールを形成してもよい。このビアホールは、磁気スタック14を電界効果トランジスタ(FET)と連結する導体充填するために用いられる。
上記のキャップ層またはハードマスク層は、WNを含んでおり、このWNの利点は、酸化環境に対して安定性があり、ハードマスク開口RIEプロセスに対して優れたエッチング選択性を有している点である。
第1絶縁層124を、リソグラフィーによってパターン化し、反応性イオンエッチング(RIE)によって、トレンチ(trenches)を形成する。このトレンチに、第1導電線112が形成されることになる。例えば、このトレンチの幅は、0.2μmであり、深さは、0.4〜0.6μmである。
Claims (27)
- 抵抗半導体記憶装置の製造方法において、
基材を準備するステップと、
上記基材の上に第1層間誘電体を形成するステップと、
上記第1層間誘電体の中に複数の第1導電線を配置するステップと、
上記第1導電線上に種膜を形成するステップと、
上記種膜上に第1磁気層を形成するステップと、
上記第1磁気スタック上にトンネル障壁層を形成するステップと、
上記トンネル障壁上に第2磁気層を堆積するステップと、
上記第2磁気スタック層上にキャップ層を堆積するステップと、
上記キャップ層上にハードマスク材質を堆積するステップと、
ハードマスクを形成するために上記ハードマスク材質をパターン化するステップと、
上記キャップ層、第2磁気層、トンネル障壁層をパターン化して複数のトンネル接合部を形成するために、上記パターン化されたハードマスクを用いるステップとを含み、
キャップ層を堆積するステップ、ハードマスク材質を堆積するステップ、または種膜を堆積するステップの少なくとも1つが、WNを堆積するステップを含む、抵抗半導体記憶装置の製造方法。 - 上記キャップ層を堆積するステップが、WNを堆積するステップを含み、
上記ハードマスク材質を堆積するステップが、導電性窒化物を堆積するステップを含む、請求項1に記載の方法。 - 上記ハードマスク材質を堆積するステップが、WNを堆積するステップを含み、
上記キャップ層を堆積するステップが、導電性窒化物を堆積するステップを含む、請求項1に記載の方法。 - 上記第1磁気スタック層をパターン化するステップと、
トンネル接合部絶縁材質を上記複数のトンネル接合部の間に堆積するステップとをさらに含む、請求項1に記載の方法。 - 上記トンネル接合部絶縁材質を堆積するステップが、Si3N4またはSiO2を堆積するステップを含む、請求項4に記載の方法。
- 上記トンネル接合部絶縁材質上に第2層間誘電体を堆積するステップをさらに含む、請求項4に記載の方法。
- 上記第2層間誘電体を堆積するステップが、SiO2または有機誘電体材質を堆積するステップを含む、請求項6に記載の方法。
- 上記キャップ層をパターン化した後に、上記ハードマスク材質を除去するステップをさらに含む、請求項1に記載の方法。
- ハードマスク材質を堆積するステップが、約200〜2000Åの導電材質を堆積するステップを含み、
上記キャップ層を堆積するステップが、約75〜250Åの材質を堆積するステップを含む、請求項1に記載の方法。 - 上記抵抗半導体記憶装置が、磁気ランダムアクセスメモリ(MRAM)装置を含む、請求項1に記載の方法。
- 上記第1導電線上に酸化物を堆積するステップをさらに含み、この酸化物上に上記の種膜を形成し、この酸化物を電界効果トランジスタと接続する、請求項1に記載の方法。
- ハードマスクを形成するために上記ハードマスク材質をパターン化するステップが、
上記ハードマスク上にレジストを堆積するステップと、
上記レジストをパターン化するステップと、
上記ハードマスク材質の領域が露出するように上記レジストの一部を除去するステップと、
上記ハードマスク材質をパターン化し、上記ハードマスクを形成するために、上記レジストを用いるステップと、
を含む、請求項1に記載の方法。 - 請求項1に記載の方法によって製造された、抵抗半導体記憶装置。
- 複数の第1導電線と、
上記第1導電線の少なくとも一部分の上に配置された種膜と、
上記種膜上に配置された第1磁気層と、
上記第1磁気層上に配置されたトンネル障壁と、
上記トンネル障壁上に配置された第2磁気層と、
上記第2磁気層上に配置されたキャップ層と、
を含み、上記種膜および上記キャップ層の少なくとも1つはWNを含む、抵抗半導体記憶装置。 - 上記キャップ層が、約75〜250Åの材質を含む、請求項15に記載の抵抗半導体記憶装置。
- 上記キャップ層上に配置されたハードマスク材質をさらに含み、上記ハードマスク材質または上記キャップ層の少なくとも1つが、WNを含む、請求項15に記載の抵抗半導体記憶装置。
- 上記ハードマスク材質が、約200〜2000Åの材質を含む、請求項17に記載の抵抗半導体記憶装置。
- 上記ハードマスク材質がWNを含み、上記キャップ層が導電性窒化物を含む、請求項17に記載の抵抗半導体記憶装置。
- 上記ハードマスク材質が導電性窒化物を含み、上記キャップ層がWNを含む、請求項17に記載の抵抗半導体記憶装置。
- 上記種膜がWNを含む、請求項17に記載の抵抗半導体記憶装置。
- 上記抵抗半導体記憶装置が、磁気ランダムアクセスメモリ(MRAM)装置を含み、上記種膜、第1磁気層、トンネル障壁および第2磁気層が、磁気トンネル接合部(MTJ)を形成するようにパターン化されている、請求項15に記載の抵抗半導体記憶装置。
- 上記MTJ上に配置された複数の第2導電線をさらに含む、請求項22に記載の抵抗半導体記憶装置。
- 上記第1導電線の真下に配置された基材と、
上記基材上に配置された第1層間誘電体と、
上記複数のMTJ間の上記第1層間誘電体上に配置された、トンネル接合部絶縁材質と、
上記トンネル接合部絶縁材質上に配置された第2層間誘電体と、
をさらに含み、
上記第1層間誘電体の内部に上記第1導電線が形成され、
上記第2層間誘電体の内部に上記第2導電線が形成されている、
請求項23に記載の抵抗半導体記憶装置。 - 上記トンネル接合部絶縁材質を堆積するステップが、Si3N4またはSiO2を堆積するステップを含み、
上記第2層間誘電体を堆積するステップが、SiO2または有機誘電体材質を堆積するステップを含む、請求項15に記載の抵抗半導体記憶装置。 - 上記第1導電線上に配置された酸化物をさらに含み、該酸化物上に上記種膜が形成されており、該酸化物が電界効果トランジスタと接続されている、請求項15に記載の抵抗半導体記憶装置。
- 上記キャップ層がWNを含む、請求項15に記載の抵抗半導体記憶装置。
- 上記種膜がWNを含む、請求項15に記載の抵抗半導体記憶装置。
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US10/124,950 US6815248B2 (en) | 2002-04-18 | 2002-04-18 | Material combinations for tunnel junction cap layer, tunnel junction hard mask and tunnel junction stack seed layer in MRAM processing |
PCT/EP2003/004095 WO2003088253A1 (en) | 2002-04-18 | 2003-04-17 | Material combinations for tunnel junction cap layer, tunnel junction hard mask and tunnel junction stack seed layer in mram processing |
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US (1) | US6815248B2 (ja) |
EP (1) | EP1495470B1 (ja) |
JP (1) | JP2005523575A (ja) |
KR (1) | KR100727710B1 (ja) |
CN (1) | CN100444280C (ja) |
DE (1) | DE60301344T2 (ja) |
TW (1) | TWI243378B (ja) |
WO (1) | WO2003088253A1 (ja) |
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WO2003088253A1 (en) | 2003-10-23 |
TWI243378B (en) | 2005-11-11 |
DE60301344T2 (de) | 2006-06-08 |
TW200405337A (en) | 2004-04-01 |
CN100444280C (zh) | 2008-12-17 |
US6815248B2 (en) | 2004-11-09 |
US20030199104A1 (en) | 2003-10-23 |
CN1647206A (zh) | 2005-07-27 |
EP1495470A1 (en) | 2005-01-12 |
DE60301344D1 (de) | 2005-09-22 |
KR100727710B1 (ko) | 2007-06-13 |
EP1495470B1 (en) | 2005-08-17 |
KR20050000518A (ko) | 2005-01-05 |
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