JP2005509288A5 - - Google Patents

Download PDF

Info

Publication number
JP2005509288A5
JP2005509288A5 JP2003543072A JP2003543072A JP2005509288A5 JP 2005509288 A5 JP2005509288 A5 JP 2005509288A5 JP 2003543072 A JP2003543072 A JP 2003543072A JP 2003543072 A JP2003543072 A JP 2003543072A JP 2005509288 A5 JP2005509288 A5 JP 2005509288A5
Authority
JP
Japan
Prior art keywords
plug
conductivity type
forming
capacitor
insulating layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2003543072A
Other languages
English (en)
Japanese (ja)
Other versions
JP2005509288A (ja
Filing date
Publication date
Priority claimed from US09/986,167 external-priority patent/US6794238B2/en
Application filed filed Critical
Publication of JP2005509288A publication Critical patent/JP2005509288A/ja
Publication of JP2005509288A5 publication Critical patent/JP2005509288A5/ja
Pending legal-status Critical Current

Links

JP2003543072A 2001-11-07 2002-11-06 周辺トランジスタに対するメタライズコンタクトの形成方法 Pending JP2005509288A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/986,167 US6794238B2 (en) 2001-11-07 2001-11-07 Process for forming metallized contacts to periphery transistors
PCT/US2002/035425 WO2003041127A2 (en) 2001-11-07 2002-11-06 Process for forming metallized contacts to periphery transistors

Publications (2)

Publication Number Publication Date
JP2005509288A JP2005509288A (ja) 2005-04-07
JP2005509288A5 true JP2005509288A5 (enExample) 2005-12-22

Family

ID=25532149

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003543072A Pending JP2005509288A (ja) 2001-11-07 2002-11-06 周辺トランジスタに対するメタライズコンタクトの形成方法

Country Status (7)

Country Link
US (2) US6794238B2 (enExample)
EP (1) EP1442474A2 (enExample)
JP (1) JP2005509288A (enExample)
KR (1) KR100529769B1 (enExample)
CN (1) CN1610969B (enExample)
AU (1) AU2002348172A1 (enExample)
WO (1) WO2003041127A2 (enExample)

Families Citing this family (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001080318A1 (fr) * 2000-04-14 2001-10-25 Fujitsu Limited Dispositif semi-conducteur et procede de fabrication
US6794238B2 (en) * 2001-11-07 2004-09-21 Micron Technology, Inc. Process for forming metallized contacts to periphery transistors
FR2832854B1 (fr) * 2001-11-28 2004-03-12 St Microelectronics Sa Fabrication de memoire dram et de transistor mos
JP2004128395A (ja) * 2002-10-07 2004-04-22 Renesas Technology Corp 半導体装置及び半導体装置の製造方法
TW583754B (en) * 2002-12-02 2004-04-11 Nanya Technology Corp Bitline structure for DRAMs and method of fabricating the same
US7476945B2 (en) * 2004-03-17 2009-01-13 Sanyo Electric Co., Ltd. Memory having reduced memory cell size
KR101054341B1 (ko) * 2004-04-30 2011-08-04 삼성전자주식회사 유기 발광 표시 장치 및 이의 제조 방법
KR100626378B1 (ko) * 2004-06-25 2006-09-20 삼성전자주식회사 반도체 장치의 배선 구조체 및 그 형성 방법
US7772108B2 (en) * 2004-06-25 2010-08-10 Samsung Electronics Co., Ltd. Interconnection structures for semiconductor devices and methods of forming the same
KR100653701B1 (ko) * 2004-08-20 2006-12-04 삼성전자주식회사 반도체 소자의 작은 비아 구조체 형성방법 및 이를 사용한상변화 기억 소자의 제조방법
US7605033B2 (en) * 2004-09-01 2009-10-20 Micron Technology, Inc. Low resistance peripheral local interconnect contacts with selective wet strip of titanium
US7445996B2 (en) * 2005-03-08 2008-11-04 Micron Technology, Inc. Low resistance peripheral contacts while maintaining DRAM array integrity
US7859112B2 (en) * 2006-01-13 2010-12-28 Micron Technology, Inc. Additional metal routing in semiconductor devices
JP4573784B2 (ja) * 2006-03-08 2010-11-04 Ｏｋｉセミコンダクタ株式会社 半導体装置の製造方法
JP2012089744A (ja) * 2010-10-21 2012-05-10 Elpida Memory Inc 半導体装置の製造方法
KR102235612B1 (ko) 2015-01-29 2021-04-02 삼성전자주식회사 일-함수 금속을 갖는 반도체 소자 및 그 형성 방법
CN106298788B (zh) * 2015-06-12 2019-07-02 中芯国际集成电路制造(上海)有限公司 存储器结构及其形成方法
US10109674B2 (en) 2015-08-10 2018-10-23 Qualcomm Incorporated Semiconductor metallization structure
KR102634947B1 (ko) 2016-08-18 2024-02-07 삼성전자주식회사 수직형 메모리 장치 및 그 제조 방법
EP3507808B1 (en) 2016-08-31 2024-12-11 Micron Technology, Inc. Memory arrays
US10355002B2 (en) 2016-08-31 2019-07-16 Micron Technology, Inc. Memory cells, methods of forming an array of two transistor-one capacitor memory cells, and methods used in fabricating integrated circuitry
US10115438B2 (en) 2016-08-31 2018-10-30 Micron Technology, Inc. Sense amplifier constructions
WO2018044456A1 (en) 2016-08-31 2018-03-08 Micron Technology, Inc. Memory cells and memory arrays
WO2018044454A1 (en) 2016-08-31 2018-03-08 Micron Technology, Inc. Memory cells and memory arrays
WO2018044457A1 (en) 2016-08-31 2018-03-08 Micron Technology, Inc. Memory cells and memory arrays
WO2018044453A1 (en) 2016-08-31 2018-03-08 Micron Technology, Inc. Memory cells and memory arrays
WO2018132250A1 (en) 2017-01-12 2018-07-19 Micron Technology, Inc. Memory cells, arrays of two transistor-one capacitor memory cells, methods of forming an array of two transistor-one capacitor memory cells, and methods used in fabricating integrated circuitry
WO2019021098A1 (en) * 2017-07-26 2019-01-31 Semiconductor Energy Laboratory Co., Ltd. SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
CN109427786B (zh) * 2017-08-21 2021-08-17 联华电子股份有限公司 半导体存储装置及其制作工艺
EP3676835A4 (en) 2017-08-29 2020-08-19 Micron Technology, Inc. MEMORY CIRCUITS
US10964590B2 (en) * 2017-11-15 2021-03-30 Taiwan Semiconductor Manufacturing Co., Ltd. Contact metallization process
US10566334B2 (en) * 2018-05-11 2020-02-18 Micron Technology, Inc. Methods used in forming integrated circuitry including forming first, second, and third contact openings
KR102775519B1 (ko) * 2019-03-26 2025-03-06 에스케이하이닉스 주식회사 반도체 메모리 장치 및 그 제조방법
EP4024456A4 (en) 2020-08-14 2023-01-04 Changxin Memory Technologies, Inc. SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURE THEREOF
CN114078778B (zh) * 2020-08-14 2024-07-23 长鑫存储技术有限公司 半导体结构及其制备方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2682455B2 (ja) 1994-07-07 1997-11-26 日本電気株式会社 半導体記憶装置およびその製造方法
US6008084A (en) * 1998-02-27 1999-12-28 Vanguard International Semiconductor Corporation Method for fabricating low resistance bit line structures, along with bit line structures exhibiting low bit line to bit line coupling capacitance
US5858831A (en) 1998-02-27 1999-01-12 Vanguard International Semiconductor Corporation Process for fabricating a high performance logic and embedded dram devices on a single semiconductor chip
KR100284737B1 (ko) * 1998-03-26 2001-03-15 윤종용 고유전율의유전막을갖는반도체장치의커패시터제조방법
JP3701469B2 (ja) * 1998-06-12 2005-09-28 株式会社ルネサステクノロジ 半導体集積回路装置の製造方法
KR100276390B1 (ko) * 1998-08-10 2000-12-15 윤종용 반도체 메모리 장치 및 그의 제조 방법
US5893734A (en) * 1998-09-14 1999-04-13 Vanguard International Semiconductor Corporation Method for fabricating capacitor-under-bit line (CUB) dynamic random access memory (DRAM) using tungsten landing plug contacts
FR2800199B1 (fr) 1999-10-21 2002-03-01 St Microelectronics Sa Fabrication de memoire dram
US6534809B2 (en) * 1999-12-22 2003-03-18 Agilent Technologies, Inc. Hardmask designs for dry etching FeRAM capacitor stacks
US6436763B1 (en) * 2000-02-07 2002-08-20 Taiwan Semiconductor Manufacturing Company Process for making embedded DRAM circuits having capacitor under bit-line (CUB)
US6294426B1 (en) * 2001-01-19 2001-09-25 Taiwan Semiconductor Manufacturing Company Method of fabricating a capacitor under bit line structure with increased capacitance without increasing the aspect ratio for a dry etched bit line contact hole
US6794238B2 (en) * 2001-11-07 2004-09-21 Micron Technology, Inc. Process for forming metallized contacts to periphery transistors

Similar Documents

Publication Publication Date Title
JP2005509288A5 (enExample)
US6794238B2 (en) Process for forming metallized contacts to periphery transistors
JP5476619B2 (ja) Ｓｏｉ型トランジスタを用いたメモリアレイ
TWI570782B (zh) 金屬氧化半導體電容器、製造其之方法以及使用其之半導體裝置
US9640587B2 (en) Semiconductor integrated circuit device having vertical channel and method of manufacturing the same
KR100734495B1 (ko) 반도체 장치
KR100467027B1 (ko) 수직 트랜지스터로 구성된 에스램 소자 및 그 제조방법
CN109494192B (zh) 半导体元件以及其制作方法
US5307310A (en) Semiconductor memory having stacked capacitors and MOS transistors
US6657265B2 (en) Semiconductor device and its manufacturing method
JPH10242422A5 (enExample)
US20150364381A1 (en) Method of manufacturing 3d semiconductor integrated circuit device
US10553591B2 (en) Semiconductor memory device
US7569893B2 (en) Method of fabricating semiconductor device and semiconductor device fabricated thereby
KR960009039A (ko) 반도체집적회로장치의 제조방법
KR100607174B1 (ko) 반도체 기판의 주 표면 아래로 연장된 플러그 콘택홀들을갖는 반도체 장치들 및 그 제조 방법들
US7598542B2 (en) SRAM devices and methods of fabricating the same
CN113629009A (zh) 半导体硅化钴膜层的制造方法、半导体器件及存储器
TWI523235B (zh) 半導體裝置及其製造方法
JPH0493069A (ja) 半導体記憶装置
KR20070001419A (ko) 반도체 소자 제조 방법
TW346678B (en) Method for producing memory cell array
KR20020024376A (ko) 반도체장치의 콘택 형성방법
KR20050122728A (ko) 반도체 소자 제조 방법
JP2004006874A (ja) 半導体装置及び半導体装置の製造方法