JP2005502202A - 電子デバイスおよび製造方法 - Google Patents

電子デバイスおよび製造方法 Download PDF

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Publication number
JP2005502202A
JP2005502202A JP2003525884A JP2003525884A JP2005502202A JP 2005502202 A JP2005502202 A JP 2005502202A JP 2003525884 A JP2003525884 A JP 2003525884A JP 2003525884 A JP2003525884 A JP 2003525884A JP 2005502202 A JP2005502202 A JP 2005502202A
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JP
Japan
Prior art keywords
compound
spin
groove
substrate
solvent
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JP2003525884A
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English (en)
Japanese (ja)
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JP2005502202A5 (enExample
Inventor
エンディシュ，デニス
レヴァート，ジョセフ
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Honeywell International Inc
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Honeywell International Inc
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Application filed by Honeywell International Inc filed Critical Honeywell International Inc
Publication of JP2005502202A publication Critical patent/JP2005502202A/ja
Publication of JP2005502202A5 publication Critical patent/JP2005502202A5/ja
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02134—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material comprising hydrogen silsesquioxane, e.g. HSQ
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
    • H01L21/02211—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Formation Of Insulating Films (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Polyoxymethylene Polymers And Polymers With Carbon-To-Carbon Bonds (AREA)
  • Physical Vapour Deposition (AREA)
JP2003525884A 2001-08-29 2002-08-23 電子デバイスおよび製造方法 Withdrawn JP2005502202A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/943,237 US20030054616A1 (en) 2001-08-29 2001-08-29 Electronic devices and methods of manufacture
PCT/US2002/026780 WO2003021636A2 (en) 2001-08-29 2002-08-23 Electronic devices and methods of manufacture

Publications (2)

Publication Number Publication Date
JP2005502202A true JP2005502202A (ja) 2005-01-20
JP2005502202A5 JP2005502202A5 (enExample) 2005-12-22

Family

ID=25479290

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003525884A Withdrawn JP2005502202A (ja) 2001-08-29 2002-08-23 電子デバイスおよび製造方法

Country Status (8)

Country Link
US (1) US20030054616A1 (enExample)
EP (1) EP1421615A2 (enExample)
JP (1) JP2005502202A (enExample)
KR (1) KR20040033000A (enExample)
CN (1) CN1579016A (enExample)
AU (1) AU2002326737A1 (enExample)
TW (1) TW569340B (enExample)
WO (1) WO2003021636A2 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017092457A (ja) * 2015-10-23 2017-05-25 三星エスディアイ株式会社Samsung SDI Co., Ltd. 膜構造物の製造方法およびパターン形成方法

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI320214B (en) * 2002-08-22 2010-02-01 Method of forming a trench isolation structure
US7348281B2 (en) * 2003-09-19 2008-03-25 Brewer Science Inc. Method of filling structures for forming via-first dual damascene interconnects
JP2005150500A (ja) * 2003-11-18 2005-06-09 Toshiba Corp 半導体装置および半導体装置の製造方法
JP2005166700A (ja) 2003-11-28 2005-06-23 Toshiba Corp 半導体装置及びその製造方法
KR100562302B1 (ko) * 2003-12-27 2006-03-22 동부아남반도체 주식회사 멀티 화학액 처리 단계를 이용한 랜덤 폴리머 제거 방법
US7924778B2 (en) * 2005-08-12 2011-04-12 Nextel Communications Inc. System and method of increasing the data throughput of the PDCH channel in a wireless communication system
WO2012137675A1 (ja) * 2011-04-06 2012-10-11 コニカミノルタホールディングス株式会社 有機エレクトロルミネッセンス素子の製造方法及び有機エレクトロルミネッセンス素子
KR102021484B1 (ko) * 2014-10-31 2019-09-16 삼성에스디아이 주식회사 막 구조물 제조 방법, 막 구조물, 및 패턴형성방법
KR101907499B1 (ko) * 2015-11-20 2018-10-12 삼성에스디아이 주식회사 막 구조물 제조 방법 및 패턴형성방법
KR102015406B1 (ko) * 2016-01-25 2019-08-28 삼성에스디아이 주식회사 막 구조물 제조 방법 및 패턴형성방법
TWI713679B (zh) * 2017-01-23 2020-12-21 聯華電子股份有限公司 互補式金氧半導體元件及其製作方法
KR102112737B1 (ko) * 2017-04-28 2020-05-19 삼성에스디아이 주식회사 막 구조물 제조 방법 및 패턴형성방법

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US4510176A (en) * 1983-09-26 1985-04-09 At&T Bell Laboratories Removal of coating from periphery of a semiconductor wafer
US4732785A (en) * 1986-09-26 1988-03-22 Motorola, Inc. Edge bead removal process for spin on films
US5296330A (en) * 1991-08-30 1994-03-22 Ciba-Geigy Corp. Positive photoresists containing quinone diazide photosensitizer, alkali-soluble resin and tetra(hydroxyphenyl) alkane additive
JP2951504B2 (ja) * 1992-06-05 1999-09-20 シャープ株式会社 シリル化平坦化レジスト及び平坦化方法並びに集積回路デバイスの製造方法
JP3740207B2 (ja) * 1996-02-13 2006-02-01 大日本スクリーン製造株式会社 基板表面に形成されたシリカ系被膜の膜溶解方法
US5866481A (en) * 1996-06-07 1999-02-02 Taiwan Semiconductor Manufacturing Company Ltd. Selective partial curing of spin-on-glass by ultraviolet radiation to protect integrated circuit dice near the wafer edge
TW438860B (en) * 1996-11-20 2001-06-07 Japan Synthetic Rubber Co Ltd Curable resin composition and cured products
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US6194283B1 (en) * 1997-10-29 2001-02-27 Advanced Micro Devices, Inc. High density trench fill due to new spacer fill method including isotropically etching silicon nitride spacers
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017092457A (ja) * 2015-10-23 2017-05-25 三星エスディアイ株式会社Samsung SDI Co., Ltd. 膜構造物の製造方法およびパターン形成方法

Also Published As

Publication number Publication date
KR20040033000A (ko) 2004-04-17
TW569340B (en) 2004-01-01
WO2003021636A3 (en) 2003-11-06
WO2003021636A2 (en) 2003-03-13
EP1421615A2 (en) 2004-05-26
CN1579016A (zh) 2005-02-09
US20030054616A1 (en) 2003-03-20
WO2003021636B1 (en) 2003-12-04
AU2002326737A1 (en) 2003-03-18

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