JP2005322934A - マルチチップ・パッケージ - Google Patents
マルチチップ・パッケージ Download PDFInfo
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- JP2005322934A JP2005322934A JP2005136634A JP2005136634A JP2005322934A JP 2005322934 A JP2005322934 A JP 2005322934A JP 2005136634 A JP2005136634 A JP 2005136634A JP 2005136634 A JP2005136634 A JP 2005136634A JP 2005322934 A JP2005322934 A JP 2005322934A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
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- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48464—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
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- H01L2924/14—Integrated circuits
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Microelectronics & Electronic Packaging (AREA)
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
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Abstract
【解決手段】 パッケージ基板104と、パッケージ基板104上に形成された第1および第2の半導体ダイ202A、202Bであって、高速シリアル通信プロトコル404A、404Bを介して互いに通信するように構成されたものである第1および第2の半導体ダイとを含んでなるマルチチップ・パッケージ100を提供する。
【選択図】 図1
Description
102 カプセル層
104 基板
106 外部相互接続構造
108A,108B 隠れ線
202A,202B,202A−1,202B−1,202A−2,202B−2,202A−3,202B−3 半導体ダイ
204A,204B,206A,206B 内部相互接続構造
208 金属パッド
210A,210B ダイ取り付けエポキシ層
302 金属パッド
402A プロセッサ回路
404A,404B インタフェース回路
406 通信リンク
408A,408B 通信リンク
410B 入出力回路
412A アナログ回路
412B デジタル回路
Claims (10)
- パッケージ基板と、
該パッケージ基板上に形成された第1および第2の半導体ダイであって、高速シリアル通信プロトコルを介して互いに通信するように構成されたものである第1および第2の半導体ダイと
を含んでなるマルチチップ・パッケージ。 - 前記第1および第2の半導体ダイを前記パッケージ基板に相互接続するための複数の相互接続構造をさらに含む請求項1に記載のマルチチップ・パッケージ。
- 前記パッケージ基板は、前記第1および第2の半導体ダイの間で高速のシリアル通信を実行する一組の導体配線路を含むものである請求項1に記載のマルチチップ・パッケージ。
- 前記第1および第2の半導体ダイは、少なくとも毎秒1ギガビット(Gb/s)のレートで高速シリアル通信プロトコルを介して互いに通信させるように構成されたものである請求項1に記載のマルチチップ・パッケージ。
- 前記第1および第2の半導体ダイは、少なくとも毎秒10ギガビット(Gb/s)のレートで高速シリアル通信プロトコルを介して互いに通信させるように構成されたものである請求項1に記載のマルチチップ・パッケージ。
- 前記マルチチップ・パッケージは計算システムであり、前記第1の半導体ダイは該計算システムのプロセッサ回路を含み、前記第2の半導体ダイは該計算システムのメモリ回路と入出力回路とを含むものである請求項1に記載のマルチチップ・パッケージ。
- 前記マルチチップ・パッケージは計算システムであり、前記第1の半導体ダイは該計算システムのプロセッサ回路およびメモリ回路を含み、前記第2の半導体ダイは該計算システムの入出力回路を含むものである請求項1に記載のマルチチップ・パッケージ。
- 前記マルチチップ・パッケージは計算システムであり、前記第1の半導体ダイは該計算システムの実質的に全てのデジタル回路を含み、前記第2の半導体ダイは該計算システムの実質的に全てのアナログ回路を含むものである請求項1に記載のマルチチップ・パッケージ。
- 前記マルチチップ・パッケージは計算システムであり、前記第1の半導体ダイは第1のシリコン処理技術により形成された回路を含み、前記第2の半導体ダイは第2のシリコン処理技術により形成された回路を含み、前記第1の処理技術は前記第2の処理技術とは異なるものである請求項1に記載のマルチチップ・パッケージ。
- マルチチップ・パッケージ内に計算システムを形成する方法であって、
パッケージ基板を配設するステップと、
前記計算システムと第1の高速シリアル入出力インタフェースとのための第1組の回路を含む第1の集積回路を形成するステップと、
前記計算システムと第2の高速シリアル入出力インタフェースとのための第2組の回路を含む第2の集積回路を形成するステップと、
前記第1および第2の集積回路を前記パッケージ基板に取り付けるステップと、
前記第1のインタフェースと前記第2のインタフェースとの間の高速シリアル通信を行なう導電配線路を前記パッケージ基板内に形成するステップと
を含んでなる方法。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/841,741 US7342310B2 (en) | 2004-05-07 | 2004-05-07 | Multi-chip package with high-speed serial communications between semiconductor die |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2005322934A true JP2005322934A (ja) | 2005-11-17 |
Family
ID=35238718
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005136634A Pending JP2005322934A (ja) | 2004-05-07 | 2005-05-09 | マルチチップ・パッケージ |
Country Status (2)
Country | Link |
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US (2) | US7342310B2 (ja) |
JP (1) | JP2005322934A (ja) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4986114B2 (ja) * | 2006-04-17 | 2012-07-25 | ルネサスエレクトロニクス株式会社 | 半導体集積回路及び半導体集積回路の設計方法 |
US7615412B2 (en) * | 2006-09-18 | 2009-11-10 | Faraday Technology Corp. | System in package (SIP) integrated circuit and packaging method thereof |
EP2000936A1 (en) * | 2007-05-29 | 2008-12-10 | Gemplus | Electronic token comprising several microprocessors and method of managing command execution on several microprocessors |
US8399973B2 (en) | 2007-12-20 | 2013-03-19 | Mosaid Technologies Incorporated | Data storage and stackable configurations |
CN101834177B (zh) * | 2010-05-20 | 2011-11-16 | 锐迪科科技有限公司 | Soc芯片器件 |
US8832511B2 (en) * | 2011-08-15 | 2014-09-09 | Taiwan Semiconductor Manufacturing Co., Ltd. | Built-in self-test for interposer |
KR20130019290A (ko) * | 2011-08-16 | 2013-02-26 | 삼성전자주식회사 | 유니버설 인쇄 회로 기판 및 그것을 포함하는 메모리 카드 |
KR20170016047A (ko) * | 2015-08-03 | 2017-02-13 | 에스케이하이닉스 주식회사 | 플래나 스택된 반도체칩들을 포함하는 반도체 패키지 |
DE112015006944B4 (de) * | 2015-09-25 | 2023-03-23 | Intel Corporation | Einrichtung, System und Verfahren zum Ermöglichen einer Kommunikation über eine Verbindung mit einer Vorrichtung außerhalb einer Baugruppe |
US9692448B1 (en) | 2016-09-22 | 2017-06-27 | Qualcomm Incorporated | Split chip solution for die-to-die serdes |
US11625245B2 (en) * | 2018-09-28 | 2023-04-11 | Intel Corporation | Compute-in-memory systems and methods |
CN112542442A (zh) * | 2020-12-25 | 2021-03-23 | 南京蓝洋智能科技有限公司 | 一种低成本多芯片高速高带宽互连结构 |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08167703A (ja) * | 1994-10-11 | 1996-06-25 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法、ならびにメモリコアチップ及びメモリ周辺回路チップ |
JPH10289976A (ja) * | 1997-04-09 | 1998-10-27 | Lucent Technol Inc | マルチチップモジュール |
JP2001160001A (ja) * | 1999-12-03 | 2001-06-12 | Fujitsu Ltd | 半導体集積回路及びチップ間記憶部同期化方法 |
JP2002229695A (ja) | 2000-12-08 | 2002-08-16 | Agilent Technol Inc | 集積回路を含む装置及びそれによる処理方法 |
JP2003198356A (ja) * | 2001-12-25 | 2003-07-11 | Hitachi Ltd | 半導体チップおよび集積回路 |
JP2005159111A (ja) * | 2003-11-27 | 2005-06-16 | Matsushita Electric Ind Co Ltd | マルチチップ型半導体装置 |
Family Cites Families (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US122503A (en) * | 1872-01-02 | Improvement in dirt-scrapers | ||
US189903A (en) * | 1877-04-24 | Improvement in the methods of mounting show-cards, maps | ||
US5121390A (en) * | 1990-03-15 | 1992-06-09 | International Business Machines Corporation | Integrated data link controller with synchronous link interface and asynchronous host processor interface |
US5799208A (en) * | 1996-04-03 | 1998-08-25 | United Microelectronics Corporation | Apparatus for data communication between universal asynchronous receiver/transmitter (UART) modules and transceivers in a chip set by selectively connecting a common bus between multiplexer/demultiplexer units |
US6492719B2 (en) * | 1999-07-30 | 2002-12-10 | Hitachi, Ltd. | Semiconductor device |
EP1145132A3 (en) | 1998-07-01 | 2002-08-21 | QUALCOMM Incorporated | Improved inter-device serial bus protocol |
US20040230668A1 (en) * | 1998-08-06 | 2004-11-18 | Jason Carnahan | Modular presentation device for use with PDA's and Smartphones |
JP2002124626A (ja) | 2000-10-16 | 2002-04-26 | Hitachi Ltd | 半導体装置 |
CN1284082C (zh) * | 2001-01-19 | 2006-11-08 | 株式会社日立制作所 | 电子电路装置 |
US7336729B2 (en) | 2001-03-01 | 2008-02-26 | Broadcom Corporation | Digital signal processing based de-serializer |
US6472747B2 (en) * | 2001-03-02 | 2002-10-29 | Qualcomm Incorporated | Mixed analog and digital integrated circuits |
US6404648B1 (en) * | 2001-03-30 | 2002-06-11 | Hewlett-Packard Co. | Assembly and method for constructing a multi-die integrated circuit |
US6882034B2 (en) | 2001-08-29 | 2005-04-19 | Micron Technology, Inc. | Routing element for use in multi-chip modules, multi-chip modules including the routing element, and methods |
US20030043726A1 (en) * | 2001-09-04 | 2003-03-06 | Freeman Robert D. | Focus stop for limiting actuator assembly focus travel |
GB2385984B (en) * | 2001-11-07 | 2006-06-28 | Micron Technology Inc | Semiconductor package assembly and method for electrically isolating modules |
US6910092B2 (en) | 2001-12-10 | 2005-06-21 | International Business Machines Corporation | Chip to chip interface for interconnecting chips |
US7191371B2 (en) | 2002-04-09 | 2007-03-13 | Internatioanl Business Machines Corporation | System and method for sequential testing of high speed serial link core |
US7844747B2 (en) | 2002-06-05 | 2010-11-30 | Stmicroelectronics, Inc. | Performance tuning using encoded performance parameter information |
US7391824B2 (en) * | 2003-05-22 | 2008-06-24 | Intel Corporation | High-speed serial link receiver with centrally controlled offset cancellation and method |
JP4381779B2 (ja) * | 2003-11-17 | 2009-12-09 | 株式会社ルネサステクノロジ | マルチチップモジュール |
US7124222B2 (en) * | 2003-12-16 | 2006-10-17 | 1X1 Mobile, Ltd. | Control system and method for a communications interface |
JP2006172122A (ja) * | 2004-12-15 | 2006-06-29 | Toshiba Corp | カード状記憶装置 |
KR100723486B1 (ko) * | 2005-05-12 | 2007-05-30 | 삼성전자주식회사 | 심/딤 구조를 가지는 메모리 모듈 및 메모리 시스템 |
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2004
- 2004-05-07 US US10/841,741 patent/US7342310B2/en active Active
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2005
- 2005-05-09 JP JP2005136634A patent/JP2005322934A/ja active Pending
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2008
- 2008-01-10 US US11/972,602 patent/US7537960B2/en not_active Expired - Fee Related
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08167703A (ja) * | 1994-10-11 | 1996-06-25 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法、ならびにメモリコアチップ及びメモリ周辺回路チップ |
JPH10289976A (ja) * | 1997-04-09 | 1998-10-27 | Lucent Technol Inc | マルチチップモジュール |
JP2001160001A (ja) * | 1999-12-03 | 2001-06-12 | Fujitsu Ltd | 半導体集積回路及びチップ間記憶部同期化方法 |
JP2002229695A (ja) | 2000-12-08 | 2002-08-16 | Agilent Technol Inc | 集積回路を含む装置及びそれによる処理方法 |
JP2003198356A (ja) * | 2001-12-25 | 2003-07-11 | Hitachi Ltd | 半導体チップおよび集積回路 |
JP2005159111A (ja) * | 2003-11-27 | 2005-06-16 | Matsushita Electric Ind Co Ltd | マルチチップ型半導体装置 |
Also Published As
Publication number | Publication date |
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US20050248036A1 (en) | 2005-11-10 |
US7537960B2 (en) | 2009-05-26 |
US20080113471A1 (en) | 2008-05-15 |
US7342310B2 (en) | 2008-03-11 |
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