JP2005174426A - 選択可能メモリワード線の不活性化 - Google Patents

選択可能メモリワード線の不活性化 Download PDF

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Publication number
JP2005174426A
JP2005174426A JP2003411053A JP2003411053A JP2005174426A JP 2005174426 A JP2005174426 A JP 2005174426A JP 2003411053 A JP2003411053 A JP 2003411053A JP 2003411053 A JP2003411053 A JP 2003411053A JP 2005174426 A JP2005174426 A JP 2005174426A
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JP
Japan
Prior art keywords
signal
receiving
node
pulse
word line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2003411053A
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English (en)
Japanese (ja)
Other versions
JP2005174426A5 (OSRAM
Inventor
Yoshinori Fujiwara
ヨシノリ フジワラ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Technology Inc
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Priority to JP2003411053A priority Critical patent/JP2005174426A/ja
Priority to US10/759,388 priority patent/US7196964B2/en
Publication of JP2005174426A publication Critical patent/JP2005174426A/ja
Publication of JP2005174426A5 publication Critical patent/JP2005174426A5/ja
Priority to US11/705,974 priority patent/US7403444B2/en
Pending legal-status Critical Current

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)
JP2003411053A 2003-12-09 2003-12-09 選択可能メモリワード線の不活性化 Pending JP2005174426A (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2003411053A JP2005174426A (ja) 2003-12-09 2003-12-09 選択可能メモリワード線の不活性化
US10/759,388 US7196964B2 (en) 2003-12-09 2004-01-15 Selectable memory word line deactivation
US11/705,974 US7403444B2 (en) 2003-12-09 2007-02-13 Selectable memory word line deactivation

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2003411053A JP2005174426A (ja) 2003-12-09 2003-12-09 選択可能メモリワード線の不活性化

Publications (2)

Publication Number Publication Date
JP2005174426A true JP2005174426A (ja) 2005-06-30
JP2005174426A5 JP2005174426A5 (OSRAM) 2007-02-01

Family

ID=34631850

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003411053A Pending JP2005174426A (ja) 2003-12-09 2003-12-09 選択可能メモリワード線の不活性化

Country Status (2)

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US (2) US7196964B2 (OSRAM)
JP (1) JP2005174426A (OSRAM)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9489989B2 (en) 2010-06-22 2016-11-08 Taiwan Semiconductor Manufacturing Company, Ltd. Voltage regulators, memory circuits, and operating methods thereof
US8648959B2 (en) 2010-11-11 2014-02-11 DigitalOptics Corporation Europe Limited Rapid auto-focus using classifier chains, MEMS and/or multiple object focusing
KR102067755B1 (ko) 2013-02-12 2020-01-17 삼성전자주식회사 불휘발성 메모리 장치 및 그것의 제어 방법
JP2023140166A (ja) * 2022-03-22 2023-10-04 キオクシア株式会社 半導体記憶装置

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2737293B2 (ja) * 1989-08-30 1998-04-08 日本電気株式会社 Ｍｏｓ型半導体記憶装置
US5202855A (en) * 1991-01-14 1993-04-13 Motorola, Inc. DRAM with a controlled boosted voltage level shifting driver
JPH0628861A (ja) * 1992-07-07 1994-02-04 Oki Electric Ind Co Ltd 半導体記憶装置
US5293342A (en) * 1992-12-17 1994-03-08 Casper Stephen L Wordline driver circuit having an automatic precharge circuit
US5596521A (en) * 1994-01-06 1997-01-21 Oki Electric Industry Co., Ltd. Semiconductor memory with built-in cache
JPH08510080A (ja) * 1994-03-09 1996-10-22 フィリップス エレクトロニクス ネムローゼ フェンノートシャップ 漸増的なワードラインの活性化によるｉ▲下ｄｄｑ▼試験可能なメモリ
JP2720812B2 (ja) * 1995-03-17 1998-03-04 日本電気株式会社 半導体記憶装置
JPH10241361A (ja) * 1997-02-25 1998-09-11 Toshiba Corp 半導体記憶装置
DE69822368T2 (de) * 1997-05-30 2004-11-18 Fujitsu Ltd., Kawasaki Halbleiterspeicherschaltung mit einem Selektor für mehrere Wortleitungen, und Prüfverfahren dafür
JP4008072B2 (ja) * 1997-08-21 2007-11-14 富士通株式会社 半導体記憶装置
JPH1186596A (ja) * 1997-09-08 1999-03-30 Mitsubishi Electric Corp 半導体記憶装置
JP3478749B2 (ja) * 1999-02-05 2003-12-15 インターナショナル・ビジネス・マシーンズ・コーポレーション 連想メモリ（ｃａｍ）のワードマッチラインのプリチャージ回路および方法
JP2001126473A (ja) * 1999-10-29 2001-05-11 Oki Electric Ind Co Ltd ワード線リセット回路を含むメモリ回路及びワード線のリセット方法
JP2001291832A (ja) * 2000-04-07 2001-10-19 Nec Microsystems Ltd 半導体メモリ装置
JP4157269B2 (ja) * 2000-06-09 2008-10-01 株式会社東芝 半導体記憶装置
US6469941B2 (en) * 2000-12-29 2002-10-22 Stmicroelectronics, Inc. Apparatus and method for pumping memory cells in a memory
DE10146185B4 (de) * 2001-09-19 2006-11-02 Infineon Technologies Ag Verfahren zum Betrieb eines Halbleiterspeichers und Halbleiterspeicher
KR100634412B1 (ko) * 2004-09-02 2006-10-16 삼성전자주식회사 향상된 프로그램 특성을 갖는 불 휘발성 메모리 장치
KR100642759B1 (ko) * 2005-01-28 2006-11-10 삼성전자주식회사 선택적 리프레쉬가 가능한 반도체 메모리 디바이스

Also Published As

Publication number Publication date
US7196964B2 (en) 2007-03-27
US20050122826A1 (en) 2005-06-09
US7403444B2 (en) 2008-07-22
US20070140038A1 (en) 2007-06-21

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