JP2004320018A5 - - Google Patents

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Publication number
JP2004320018A5
JP2004320018A5 JP2004114863A JP2004114863A JP2004320018A5 JP 2004320018 A5 JP2004320018 A5 JP 2004320018A5 JP 2004114863 A JP2004114863 A JP 2004114863A JP 2004114863 A JP2004114863 A JP 2004114863A JP 2004320018 A5 JP2004320018 A5 JP 2004320018A5
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JP
Japan
Prior art keywords
interconnect
integrated circuit
levels
circuit device
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2004114863A
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English (en)
Japanese (ja)
Other versions
JP5258142B2 (ja
JP2004320018A (ja
Filing date
Publication date
Priority claimed from US10/675,258 external-priority patent/US7566964B2/en
Application filed filed Critical
Publication of JP2004320018A publication Critical patent/JP2004320018A/ja
Publication of JP2004320018A5 publication Critical patent/JP2004320018A5/ja
Application granted granted Critical
Publication of JP5258142B2 publication Critical patent/JP5258142B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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JP2004114863A 2003-04-10 2004-04-09 銅技術相互接続構造を使用する集積回路デバイス用のアルミニウム・パッド電力バスおよび信号ルーティング技術 Expired - Fee Related JP5258142B2 (ja)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US46250403P 2003-04-10 2003-04-10
US60/462504 2003-04-10
US10/675258 2003-09-30
US10/675,258 US7566964B2 (en) 2003-04-10 2003-09-30 Aluminum pad power bus and signal routing for integrated circuit devices utilizing copper technology interconnect structures

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2011236296A Division JP2012054588A (ja) 2003-04-10 2011-10-27 銅技術相互接続構造を使用する集積回路デバイス用のアルミニウム・パッド電力バスおよび信号ルーティング技術

Publications (3)

Publication Number Publication Date
JP2004320018A JP2004320018A (ja) 2004-11-11
JP2004320018A5 true JP2004320018A5 (enExample) 2007-05-31
JP5258142B2 JP5258142B2 (ja) 2013-08-07

Family

ID=32096363

Family Applications (2)

Application Number Title Priority Date Filing Date
JP2004114863A Expired - Fee Related JP5258142B2 (ja) 2003-04-10 2004-04-09 銅技術相互接続構造を使用する集積回路デバイス用のアルミニウム・パッド電力バスおよび信号ルーティング技術
JP2011236296A Pending JP2012054588A (ja) 2003-04-10 2011-10-27 銅技術相互接続構造を使用する集積回路デバイス用のアルミニウム・パッド電力バスおよび信号ルーティング技術

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP2011236296A Pending JP2012054588A (ja) 2003-04-10 2011-10-27 銅技術相互接続構造を使用する集積回路デバイス用のアルミニウム・パッド電力バスおよび信号ルーティング技術

Country Status (5)

Country Link
US (1) US7566964B2 (enExample)
JP (2) JP5258142B2 (enExample)
KR (1) KR101084957B1 (enExample)
GB (2) GB2427074B (enExample)
TW (1) TWI344685B (enExample)

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US7335536B2 (en) 2005-09-01 2008-02-26 Texas Instruments Incorporated Method for fabricating low resistance, low inductance interconnections in high current semiconductor devices
US8319343B2 (en) * 2005-09-21 2012-11-27 Agere Systems Llc Routing under bond pad for the replacement of an interconnect layer
US7952206B2 (en) * 2005-09-27 2011-05-31 Agere Systems Inc. Solder bump structure for flip chip semiconductor devices and method of manufacture therefore
US8552560B2 (en) * 2005-11-18 2013-10-08 Lsi Corporation Alternate pad structures/passivation inegration schemes to reduce or eliminate IMC cracking in post wire bonded dies during Cu/Low-K BEOL processing
TWI288463B (en) * 2006-04-26 2007-10-11 Siliconware Precision Industries Co Ltd Semiconductor package substrate and semiconductor package having the substrate
US7888257B2 (en) * 2007-10-10 2011-02-15 Agere Systems Inc. Integrated circuit package including wire bonds
EP2195837A1 (en) * 2007-10-31 2010-06-16 Agere Systems Inc. Bond pad support structure for semiconductor device
US20100289132A1 (en) * 2009-05-13 2010-11-18 Shih-Fu Huang Substrate having embedded single patterned metal layer, and package applied with the same, and methods of manufacturing of the substrate and package
US20110084372A1 (en) * 2009-10-14 2011-04-14 Advanced Semiconductor Engineering, Inc. Package carrier, semiconductor package, and process for fabricating same
US8786062B2 (en) * 2009-10-14 2014-07-22 Advanced Semiconductor Engineering, Inc. Semiconductor package and process for fabricating same
US8569894B2 (en) 2010-01-13 2013-10-29 Advanced Semiconductor Engineering, Inc. Semiconductor package with single sided substrate design and manufacturing methods thereof
TWI411075B (zh) 2010-03-22 2013-10-01 日月光半導體製造股份有限公司 半導體封裝件及其製造方法
US8753917B2 (en) * 2010-12-14 2014-06-17 International Business Machines Corporation Method of fabricating photoconductor-on-active pixel device
JP2013229455A (ja) * 2012-04-26 2013-11-07 Renesas Electronics Corp 半導体装置および半導体装置の製造方法
US20220293661A1 (en) * 2021-03-11 2022-09-15 Raytheon Company Offset vertical interconnect and compression post for 3d-integrated electrical device

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US5719448A (en) 1989-03-07 1998-02-17 Seiko Epson Corporation Bonding pad structures for semiconductor integrated circuits
JPH05226584A (ja) * 1992-02-12 1993-09-03 Yamaha Corp 集積回路装置
US5436412A (en) * 1992-10-30 1995-07-25 International Business Machines Corporation Interconnect structure having improved metallization
JPH0831820A (ja) * 1994-07-19 1996-02-02 Sony Corp 半導体装置
US6331482B1 (en) * 1996-06-26 2001-12-18 Micron Technology, Inc. Method of VLSI contact, trench, and via filling using a germanium underlayer with metallization
US6130161A (en) * 1997-05-30 2000-10-10 International Business Machines Corporation Method of forming copper interconnections with enhanced electromigration resistance and reduced defect sensitivity
JP3660799B2 (ja) * 1997-09-08 2005-06-15 株式会社ルネサステクノロジ 半導体集積回路装置の製造方法
US6448650B1 (en) * 1998-05-18 2002-09-10 Texas Instruments Incorporated Fine pitch system and method for reinforcing bond pads in semiconductor devices
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US6225207B1 (en) 1998-10-01 2001-05-01 Applied Materials, Inc. Techniques for triple and quadruple damascene fabrication
US6018187A (en) * 1998-10-19 2000-01-25 Hewlett-Packard Cmpany Elevated pin diode active pixel sensor including a unique interconnection structure
US6261944B1 (en) 1998-11-24 2001-07-17 Vantis Corporation Method for forming a semiconductor device having high reliability passivation overlying a multi-level interconnect
TW445616B (en) * 1998-12-04 2001-07-11 Koninkl Philips Electronics Nv An integrated circuit device
US6756295B2 (en) 1998-12-21 2004-06-29 Megic Corporation Chip structure and process for forming the same
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TW426980B (en) * 1999-01-23 2001-03-21 Lucent Technologies Inc Wire bonding to copper
JP2000216184A (ja) * 1999-01-25 2000-08-04 Sanyo Electric Co Ltd 半導体装置およびその製造方法
US20020000665A1 (en) * 1999-04-05 2002-01-03 Alexander L. Barr Semiconductor device conductive bump and interconnect barrier
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US6107185A (en) * 1999-04-29 2000-08-22 Advanced Micro Devices, Inc. Conductive material adhesion enhancement in damascene process for semiconductors
US6204165B1 (en) 1999-06-24 2001-03-20 International Business Machines Corporation Practical air dielectric interconnections by post-processing standard CMOS wafers
US6410435B1 (en) * 1999-10-01 2002-06-25 Agere Systems Guardian Corp. Process for fabricating copper interconnect for ULSI integrated circuits
US6451681B1 (en) * 1999-10-04 2002-09-17 Motorola, Inc. Method of forming copper interconnection utilizing aluminum capping film
US6198170B1 (en) * 1999-12-16 2001-03-06 Conexant Systems, Inc. Bonding pad and support structure and method for their fabrication
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US6798073B2 (en) * 2001-12-13 2004-09-28 Megic Corporation Chip structure and process for forming the same
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US20030218259A1 (en) * 2002-05-21 2003-11-27 Chesire Daniel Patrick Bond pad support structure for a semiconductor device
JP2004111796A (ja) * 2002-09-20 2004-04-08 Hitachi Ltd 半導体装置
US6717270B1 (en) * 2003-04-09 2004-04-06 Motorola, Inc. Integrated circuit die I/O cells

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