CN103915412B - 用于集成电路的金属布线结构 - Google Patents

用于集成电路的金属布线结构 Download PDF

Info

Publication number
CN103915412B
CN103915412B CN201310131778.1A CN201310131778A CN103915412B CN 103915412 B CN103915412 B CN 103915412B CN 201310131778 A CN201310131778 A CN 201310131778A CN 103915412 B CN103915412 B CN 103915412B
Authority
CN
China
Prior art keywords
metal
pad
layer
trace
overlapping
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201310131778.1A
Other languages
English (en)
Other versions
CN103915412A (zh
Inventor
庄其达
庄曜群
陈志华
郭正铮
陈承先
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN103915412A publication Critical patent/CN103915412A/zh
Application granted granted Critical
Publication of CN103915412B publication Critical patent/CN103915412B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157Partial encapsulation or coating
    • H01L23/3192Multilayer coating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528Geometry or layout of the interconnection structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02233Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body not in direct contact with the bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/023Redistribution layers [RDL] for bonding areas
    • H01L2224/0237Disposition of the redistribution layers
    • H01L2224/02375Top view
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/03Manufacturing methods
    • H01L2224/038Post-treatment of the bonding area
    • H01L2224/0382Applying permanent coating, e.g. in-situ coating
    • H01L2224/03826Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/03Manufacturing methods
    • H01L2224/039Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H01L2224/03912Methods of manufacturing bonding areas involving a specific sequence of method steps the bump being used as a mask for patterning the bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05005Structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05005Structure
    • H01L2224/05008Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05005Structure
    • H01L2224/05009Bonding area integrally formed with a via connection of the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/0502Disposition
    • H01L2224/05022Disposition the internal layer being at least partially embedded in the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05075Plural internal layers
    • H01L2224/05078Plural internal layers being disposed next to each other, e.g. side-to-side arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124Aluminium [Al] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166Titanium [Ti] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05541Structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/05571Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05575Plural external layers
    • H01L2224/0558Plural external layers being stacked
    • H01L2224/05582Two-layer coating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/114Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146Plating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/1147Manufacturing methods using a lift-off mask
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1301Shape
    • H01L2224/13012Shape in top view
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13075Plural core members
    • H01L2224/1308Plural core members being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13075Plural core members
    • H01L2224/1308Plural core members being stacked
    • H01L2224/13083Three-layer arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111Tin [Sn] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144Gold [Au] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13155Nickel [Ni] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13164Palladium [Pd] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16135Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818Bonding techniques
    • H01L2224/81801Soldering or alloying
    • H01L2224/81815Reflow soldering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本发明公开了一种器件包括衬底,位于衬底上方的金属焊盘,以及与所述金属焊盘电断开的金属迹线。金属焊盘和金属迹线相互齐平。钝化层包括与所述金属焊盘的边缘部分重叠的部分。金属柱覆盖在金属焊盘上方并且与所述金属焊盘电断开。金属迹线具有与所述金属柱重叠的部分。本发明还公开了一种用于集成电路的金属布线结构。

Description

用于集成电路的金属布线结构
技术领域
本发明涉及半导体技术领域,更具体地,涉及一种用于集成电路的金属布线结构。
背景技术
集成电路不夸张地由数百万的有源器件(诸如晶体管和电容器)组成。首先这些器件彼此分离,然后互连以形成功能电路。典型的互连结构包括横向互连件,诸如金属线(布线),和垂直互连件,诸如通孔和接触件。
在互连结构的顶上形成连接件结构。连接件结构包括在相应的芯片的表面上形成并暴露出相应芯片的表面的接合焊盘或金属凸块。电连接件通过接合焊盘或金属凸块制成以将芯片连接至封装衬底或另一管芯。电连接件可以通过引线接合或倒装芯片接合制成。
一种类型的连接件结构包括铝焊盘,将其电连接至相应的下面的互连件结构。形成钝化层和聚合物层,并且钝化层和聚合物层的部分覆盖铝焊盘的边缘部分。形成凸块下金属化层(UBM)并延伸到钝化层和聚合物层中的开口内。可以在UBM上形成焊球。
发明内容
为了解决现有技术中所存在的问题,根据本发明的一个方面,提供了一种器件,包括:
衬底;
金属焊盘,位于所述衬底上方;
第一金属迹线,与所述金属焊盘电断开,其中,所述金属焊盘和所述第一金属迹线相互齐平;
钝化层,包括与所述金属焊盘的边缘部分重叠的部分;以及
金属柱,覆盖在所述金属焊盘上方并且电连接至所述金属焊盘,其中,所述第一金属迹线包括与所述金属柱重叠的一部分。
在可选实施例中,所述器件还包括覆盖在所述金属柱上方并且与所述金属柱接触的焊帽。
在可选实施例中,所述器件还包括凸块下金属化层(UBM),所述UBM包括:与所述钝化层的所述部分齐平并且与所述金属焊盘的顶面接触的第一部分;以及,与所述钝化层的所述部分重叠的第二部分。
在可选实施例中,所述金属焊盘包含铝和铜。
在可选实施例中,所述器件还包括与所述金属焊盘电断开的第二金属迹线,其中,所述第一金属迹线和所述第二金属迹线位于所述金属焊盘的相对侧,并且所述第二金属迹线包括与所述金属柱重叠的第一部分和不与所述金属柱重叠的第二部分。
在可选实施例中,所述器件还包括位于所述钝化层上方和位于所述金属柱的一部分下方的聚合物层,其中,所述金属柱通过所述聚合物层中的开口电连接至所述金属焊盘。
在可选实施例中,所述第一金属迹线具有彼此相对的第一边缘和第二边缘,并且所述第一边缘和所述第二边缘均包括与所述金属柱重叠的部分。
根据本发明的另一方面,还提供了一种器件,包括:
衬底;
金属焊盘,位于所述衬底上方;
第一金属迹线,与所述金属焊盘断开,其中,所述金属焊盘和所述第一金属迹线相互齐平;
聚合物层,包括与所述金属焊盘的边缘部分重叠的部分;
凸块下金属化层(UBM),所述第一金属迹线包括与所述UBM重叠的第一部分以及不与所述UBM重叠的第二部分,并且所述UBM包括:
第一部分,覆盖在所述金属焊盘上方并且与所述金属焊盘接触,其中,所述UBM的第一部分穿透所述聚合物层;和
第二部分,覆盖在所述聚合物层上方;
焊料区,覆盖在所述UBM上方并且电连接至所述UBM;以及
第二金属迹线,连接至所述焊料区,其中,所述焊料区与所述第二金属迹线的底面和侧壁接触。
在可选实施例中,所述器件还包括覆盖在所述UBM上方并且与所述UBM接触的非回流焊的金属柱,其中,所述非回流焊的金属柱位于所述UBM和所述焊料区之间,并且与所述UBM和所述焊料区接触。
在可选实施例中,所述UBM包括在器件管芯中,并且所述第二金属迹线包括在封装衬底中。
在可选实施例中,所述器件还包括与所述焊料区重叠的所述第一金属迹线的第一部分。
在可选实施例中,所述金属焊盘包括铝和铜。
在可选实施例中,所述器件还包括与所述金属焊盘电断开的第三金属迹线,其中,所述第一金属迹线和所述第三金属迹线位于所述金属焊盘的相对侧,并且所述第三金属迹线包括与所述UBM重叠的第一部分以及不与所述UBM重叠的第二部分。
在可选实施例中,所述器件还包括位于所述聚合物层下方并且与所述金属焊盘的边缘部分重叠的钝化层。
根据本发明的又一方面,还提供了一种器件,包括:
衬底;
含铝焊盘,位于所述衬底上方;
第一金属迹线,与所述含铝焊盘断开,其中,所述含铝焊盘和所述第一金属迹线相互齐平;
钝化层,覆盖所述含铝焊盘的边缘部分;
聚合物层,位于所述钝化层上方并且覆盖所述含铝焊盘的边缘部分;
凸块下金属化层(UBM),包括延伸入所述钝化层和所述聚合物层内以接触所述含铝焊盘的第一部分以及与所述聚合物层重叠的第二部分;以及
金属柱,位于所述UBM上方,所述金属柱的边缘与所述UBM的相应边缘对准,并且所述第一金属迹线包括与所述UBM的一部分和所述金属柱的一部分垂直对准的部分。
在可选实施例中,所述第一金属迹线具有彼此相对的第一边缘和第二边缘,并且所述第一边缘和所述第二边缘均包括与所述金属柱重叠的部分。
在可选实施例中,所述第一金属迹线具有彼此相对的第一边缘和第二边缘,并且所述第一边缘包括与所述金属柱重叠的部分,而所述第二边缘不与所述金属柱重叠。
在可选实施例中,所述钝化层和所述聚合物层还与所述第一金属迹线重叠。
在可选实施例中,所述器件还包括与所述含铝焊盘断开的第二金属迹线,其中,所述第一金属迹线和所述第二金属迹线位于所述含铝焊盘的相对侧,并且所述第二金属迹线包括与所述UBM重叠的第一部分和不与所述UBM重叠的第二部分。
在可选实施例中,所述器件还包括位于所述金属柱上方的焊帽。
附图说明
为了更好地理解实施例及其优点,现在将参考结合附图所进行的以下描述,其中:
图1A是根据一些示例性实施例的包括连接件结构的器件的截面图;
图1B是根据一些可选的实施例的包括连接件结构的器件的截面图;
图2A示出图1A中的结构的俯视图;
图2B示出图1B中的结构的俯视图;
图3示出图1中的器件至封装衬底的接合;和
图4示出根据可选实施例的包括焊球的器件的截面图。
具体实施方式
下面详细论述本发明的实施例的制造和使用。然而,应该理解,本发明的实施例提供了许多可以在各种具体环境中实现的可应用的发明构思。所论述的具体实施例是说明性的,而不用于限制本发明的范围。
根据各个示例性实施例提供了包括连接件结构的器件。论述了实施例的多种变化。在各个附图和示例性实施例中,相同的参考标号用于表示相同的元件。
图1A示出根据示例性实施例的封装元件20的截面图。在一些实施例中,封装元件是20是器件管芯。根据这些实施例,半导体衬底30可以是块状硅衬底或绝缘体上硅衬底。可选地,包括III族、IV族和V族元素的其他半导体材料也可以包含在半导体衬底30内。在半导体衬底30的表面30A形成集成电路32。集成电路32可以包括在其中的互补金属氧化物半导体(CMOS)器件。在可选的实施例中,封装元件20是中间管芯、封装衬底等。在封装元件20是中间管芯的实施例中,封装元件20不包括在其中的诸如晶体管的有源器件。在一些实施例中,封装元件20可以包括诸如电阻器和电容器的无源器件,或不包括无源器件。
在封装元件20是器件管芯的实施例中,封装元件20还可以包括位于半导体衬底30上方的层间电介质(ILD)33,和位于ILD33上方的互连结构34。互连结构34包括介电层(或电介质层)38,及形成在介电层38中的金属线35和通孔36。在一些实施例中,介电层38由低k介电材料形成。举例来说,低k介电材料的介电常数(k值)可以小于约2.8,或小于约2.5。金属线35和通孔36可以由铜、铜合金或其他含金属的导电材料形成。可以使用单镶嵌和/或双镶嵌工艺形成金属线35和通孔36。
在互连结构34上方形成金属焊盘40,并且可以通过互连结构34中的金属线35和通孔36电连接至电路32。金属焊盘40可以是铝焊盘或铝铜焊盘。例如,金属焊盘40可以包含介于约1%和约100%(在此情况下,金属焊盘40为铝焊盘)之间的铝,和小于约1%的铜。在一些实施例中,位于金属焊盘40下面并且接触金属焊盘40的金属部件36是金属线。在可选的实施例中,位于金属焊盘40下面并且接触金属焊盘40的金属部件36是金属通孔。
除了金属焊盘40之外,在与金属焊盘40同一水平处还形成金属迹线140。金属焊盘40和金属迹线140由相同的材料形成,并且可以同时形成,例如通过沉积铝铜层,然后图案化铝铜层以形成金属焊盘40和金属迹线140。金属焊盘40与金属迹线140电断开。结果,在封装元件20的操作期间,金属焊盘40可以具有与金属迹线140的电压电平不同的电压电平。
形成钝化层42以覆盖金属焊盘40的边缘部分。通过钝化层42中的开口暴露出金属焊盘40的中心部分。钝化层42可以由无孔材料形成。在一些实施例中,钝化层42是包括氧化硅层(未示出)和位于氧化硅层上方的氮化硅层(未示出)的复合层。在可选的实施例中,钝化层42包括未掺杂的硅酸盐玻璃(USG)、氮氧化硅等。虽然示出一层钝化层42,但可以具有多于一层的钝化层。
在钝化层42上方形成聚合物层46并且覆盖钝化层42。聚合物层46可以包含诸如环氧树脂、聚酰亚胺、苯并环丁烯(BCB)和聚苯并恶唑(PBO)等的聚合物。图案化聚合物层46以形成开口,金属焊盘40通过开口暴露出来。
在金属焊盘40上方形成凸块下金属化层(UBM)48。UBM48包括位于聚合物层46上方的第一部分,和延伸到聚合物层46和钝化层42中的开口内以接触金属焊盘40的第二部分。在一些实施例中,UBM48包括钛层和由铜或铜合金形成的种子层。
根据一些实施例,在UBM48上方形成金属柱50,并且其与UBM48具有共同的端部。例如,金属柱50的边缘中的每一个与UBM48相应的边缘对准。因此,金属柱50的横向尺寸还等于UBM48的相应的横向尺寸。UBM48可以与金属柱50物理接触。在一些示例性实施例中,金属柱50由在回流焊工艺中不熔化的(一种或多种)非回流焊(non-reflowable)的金属形成。例如,金属柱50可以由铜或铜合金形成。金属柱50的顶面50A高于聚合物层46的顶面46A。
除了示出的金属柱50之外,还可以具有其他金属层,诸如形成在金属柱50上的金属层52,其中金属层52可以包括镍层、钯层、金层或它们的多层。在这些实施例中,金属层52还可以被认为是金属柱50的一部分。还可以在金属层52上方形成焊帽54,其中焊帽54可以由Sn-Ag合金、Sn-Cu合金、Sn-Ag-Cu合金等形成,并且可以是无铅焊帽或含铅焊帽。
在一些示例性实施例中,UBM48、金属柱50和金属层52的形成包括实施物理汽相沉积(PVD)以形成均厚UBM层(未示出,其中UBM48是UBM层的一部分),然后在均厚UBM层上方形成掩模层并图案化该掩模层(未示出)。掩模层可以是光刻胶或干膜。然后在掩模层的开口中形成金属柱50、金属层52和焊帽54,其中均厚UBM层通过开口暴露出来。示例性形成工艺包括镀层。在金属柱50、金属层52和焊帽54形成之后,去除掩模层。去除UBM层的没有被图案化的掩模层覆盖的部分,从而留下未被去除的金属柱50、金属层52和焊帽54。可以实施回流,从而焊帽54具有圆形顶面。
UBM48和金属柱50与金属焊盘40的至少一部分重叠,并且还可以与整个金属焊盘40重叠(参照图2A)。金属迹线140在UNM48和金属柱50下面延伸。因此,每一金属迹线140中的一部分被UBM48和金属柱50重叠。每一金属迹线140具有相对边缘140A和140B。在一些实施例中,UBM48和金属柱50与一根或多根金属迹线140的边缘140A和140B重叠。在可选的实施例中,UBM48和金属柱50可以与边缘140A重叠,并且不与一根金属迹线140的边缘140B的任何部分重叠。
图2A示出图1A中的结构的俯视图,其中图1A中的截面图从图2A中的平面剖切线1A-1A获得。图2A表明金属迹线140可以包括与UBM48和金属柱50重叠的部分140’。此外,金属迹线140还可以包括与UBM48和金属柱50不重叠的部分140”。在示出的俯视图中,UBM48和金属柱50具有圆形俯视形状。在可选的实施例中,UBM48和金属柱50还具有其他俯视形状,诸如椭圆、矩形、六边形、八边形等。类似地,虽然金属焊盘40示出具有八边形俯视形状。在可选的实施例中,金属焊盘40还可以具有其他俯视形状,诸如圆形、椭圆、矩形、六边形等。
而且,在一些实施例中,如图2A中,金属迹线140中的每一根包括与相应的UBM48和金属柱50不重叠的两个端部140”。在可选的实施例中,金属迹线140中的一根或多根可以具有没有被相应的UBM48和金属柱50覆盖的单个端部140”,如图2B所示,其中金属迹线140中的相应的一根也被标记为140A。
图1B示出图2B中示出的结构的截面图,其中该截面图从图2B中的平面剖切线2A-2A获得。图1B中的结构类似于图1A中的结构,除了金属线或通孔36’位于金属迹线140中的一根下面并且与其连接。金属线/通孔36’还与UBM48和金属柱50重叠。
可以理解,虽然在图2A和图2B中两根金属迹线140在UBM48和金属柱50中的每一个下面延伸,然而在UBM48和金属柱50中的每一个下面延伸的金属迹线140的数量可以是诸如一、三、四、五或更大的任何整数。
图3示出金属柱50与封装元件60的金属迹线62的接合。在一些实施例中,通过铜柱导线直连(Bump-On-Trace,BOT)接合方案实施接合。根据一些实施例,封装元件60可以是封装衬底,其可以是层压衬底或增层式衬底。例如,封装元件60可以包括多层介电层,以及嵌入介电层中的金属线和通孔(未示出)。在可选实施例中,封装元件60是器件管芯、封装件、中间管芯等。在通过BOT接合方案实施接合的实施例中,将焊料区54接合到金属迹线62的表面62A和侧壁表面62B并且与金属迹线62的表面62A和侧壁表面62B接触。在这些实施例中,金属迹线62可以具有均匀宽度,其中金属迹线62的与焊料区域54接触的部分的宽度可以与金属迹线62的不与焊料区域54接触的部分的宽度相同。
在一些实施例中,封装元件60包括将连接件70电连接至金属迹线62的金属线(或金属焊盘)66和通孔68,其中连接件70和金属迹线62位于封装元件60的相对侧上。连接件70可以是焊球、金属柱、或包括金属柱和焊帽的复合金属连接件。金属线66和通孔68可以布线为通过多层介电层72(其可以是有机介电层或非有机介电层)。
在图1和图3示出的实施例中,非回流焊金属柱50位于UBM48上方。在可选的实施例中,如图4所示,焊球64形成在UBM48上方并且与UBM48接触。这些实施例基本上与图1和图3中示出的实施例相同,除了焊球64替代金属柱50和上覆的金属层52和焊帽54(图1A和图1B)(如果有的话)。在这些实施例中,金属迹线140在焊球64下面延伸并且与焊球64重叠。此外,焊球64可以与金属迹线140中的一根或两根的边缘140A和140B中的一个或两个重叠。
在实施例中,通过允许金属迹线140在UBM48以及上覆的金属柱50(图1A和图1B)或焊球64(图4)下面延伸,相比于不允许金属迹线在UBM、金属柱和焊球下面布线的常规结构,金属迹线140的布线灵活性增加。由于具有改善的布线灵活性,可以在芯片上设置更多的金属迹线,和/或可以保留更多的芯片面积以加入更多的UBM48和金属柱50。
根据一些实施例,一种器件包括衬底、位于衬底上方的金属焊盘、以及与金属焊盘电断开的金属迹线。金属焊盘和金属迹线相互齐平。钝化层包括与金属焊盘的边缘部分重叠的部分。金属柱覆盖在金属焊盘上方,并且电连接至金属焊盘。金属迹线具有与金属柱重叠的部分。
根据其他一些实施例,一种器件包括衬底、位于衬底上方的金属焊盘、以及与金属焊盘电断开的金属迹线,其中金属焊盘与金属迹线相互齐平。聚合物层包括与金属焊盘的边缘部分重叠的部分。金属迹线具有与UBM重叠的第一部分,和不与UBM重叠的第二部分。UBM包括覆盖在金属焊盘上方并且与金属焊盘接触的第一部分,其中第一部分穿透聚合物层;以及覆盖在聚合物层上方的第二部分。焊料区设置为覆盖在UBM上方并且与UBM电连接。将第二金属迹线连接至焊料区,其中焊料区与第二金属迹线的底面和侧壁接触。
根据又一些其他实施例,一种器件包括衬底、位于衬底上方的含铝焊盘、和与含铝焊盘断开的金属迹线。含铝焊盘与金属迹线相互齐平。钝化层覆盖含铝焊盘的边缘部分。聚合物层位于钝化层上方并且覆盖含铝焊盘的边缘部分。UBM包括延伸入钝化层和聚合物层内以接触含铝焊盘的第一部分,和与聚合物层重叠的第二部分。金属柱位于UBM上方,其中金属柱的边缘与UBM的相应边缘对准。金属迹线包括与UBM的一部分和金属柱的一部分垂直对准的部分。
尽管已经详细地描述了本发明的实施例及其优势,但应该理解,可以在不背离所附权利要求限定的本发明主旨和范围的情况下,做各种不同的改变、替换和更改。此外,本申请的范围并不仅限于说明书中描述的工艺、机器、制造、材料组分、装置、方法和步骤的特定实施例。作为本领域普通技术人员根据本发明的发明内容将很容易理解,根据本发明可以利用现有的或今后开发的用于执行与根据本文所述相应实施例基本上相同的功能或获得基本上相同结果的工艺、机器、制造、材料组分、装置、方法或步骤。因此,所附权利要求应该在其范围内包括这样的工艺、机器、制造、材料组分、装置、方法或步骤。此外,每条权利要求构成单独的实施例,并且多条权利要求和实施例的组合在本发明的范围内。

Claims (19)

1.一种半导体器件,包括:
衬底;
金属焊盘,位于所述衬底上方;
第一金属迹线,与所述金属焊盘电断开,其中,所述金属焊盘和所述第一金属迹线相互齐平;
钝化层,包括与所述金属焊盘的边缘部分重叠的部分;
凸块下金属化层(UBM),包括延伸入所述钝化层内以接触所述金属焊盘的第一部分以及与所述钝化层重叠的第二部分;以及
金属柱,位于所述凸块下金属化层上方,所述金属柱的边缘与所述凸块下金属化层的相应边缘对准,并且所述第一金属迹线包括与所述凸块下金属化层的一部分和所述金属柱的一部分垂直对准的部分。
2.根据权利要求1所述的半导体器件,还包括覆盖在所述金属柱上方并且与所述金属柱接触的焊帽。
3.根据权利要求1所述的半导体器件,其中,所述金属焊盘包含铝和铜。
4.根据权利要求1所述的半导体器件,还包括与所述金属焊盘电断开的第二金属迹线,其中,所述第一金属迹线和所述第二金属迹线位于所述金属焊盘的相对侧,并且所述第二金属迹线包括与所述金属柱重叠的第一部分和不与所述金属柱重叠的第二部分。
5.根据权利要求1所述的半导体器件,还包括位于所述钝化层上方和位于所述金属柱的一部分下方的聚合物层,其中,所述金属柱通过所述聚合物层中的开口电连接至所述金属焊盘。
6.根据权利要求1所述的半导体器件,其中,所述第一金属迹线具有彼此相对的第一边缘和第二边缘,并且所述第一边缘和所述第二边缘均包括与所述金属柱重叠的部分。
7.一种半导体器件,包括:
衬底;
金属焊盘,位于所述衬底上方;
第一金属迹线,与所述金属焊盘断开,其中,所述金属焊盘和所述第一金属迹线相互齐平;
聚合物层,包括与所述金属焊盘的边缘部分重叠的部分;
凸块下金属化层(UBM),所述第一金属迹线包括与所述凸块下金属化层重叠的第一部分以及不与所述凸块下金属化层重叠的第二部分,并且所述凸块下金属化层包括:
第一部分,覆盖在所述金属焊盘上方并且与所述金属焊盘接触,其中,所述凸块下金属化层的第一部分穿透所述聚合物层;和
第二部分,覆盖在所述聚合物层上方;
焊料区,覆盖在所述凸块下金属化层上方并且电连接至所述凸块下金属化层;以及
第二金属迹线,连接至所述焊料区,其中,所述焊料区与所述第二金属迹线的底面和侧壁接触。
8.根据权利要求7所述的半导体器件,还包括覆盖在所述凸块下金属化层上方并且与所述凸块下金属化层接触的非回流焊的金属柱,其中,所述非回流焊的金属柱位于所述凸块下金属化层和所述焊料区之间,并且与所述凸块下金属化层和所述焊料区接触。
9.根据权利要求7所述的半导体器件,其中,所述凸块下金属化层包括在器件管芯中,并且所述第二金属迹线包括在封装衬底中。
10.根据权利要求7所述的半导体器件,还包括与所述焊料区重叠的所述第一金属迹线的第一部分。
11.根据权利要求7所述的半导体器件,其中,所述金属焊盘包括铝和铜。
12.根据权利要求7所述的半导体器件,还包括与所述金属焊盘电断开的第三金属迹线,其中,所述第一金属迹线和所述第三金属迹线位于所述金属焊盘的相对侧,并且所述第三金属迹线包括与所述凸块下金属化层重叠的第一部分以及不与所述凸块下金属化层重叠的第二部分。
13.根据权利要求7所述的半导体器件,还包括位于所述聚合物层下方并且与所述金属焊盘的边缘部分重叠的钝化层。
14.一种半导体器件,包括:
衬底;
含铝焊盘,位于所述衬底上方;
第一金属迹线,与所述含铝焊盘断开,其中,所述含铝焊盘和所述第一金属迹线相互齐平;
钝化层,覆盖所述含铝焊盘的边缘部分;
聚合物层,位于所述钝化层上方并且覆盖所述含铝焊盘的边缘部分;
凸块下金属化层(UBM),包括延伸入所述钝化层和所述聚合物层内以接触所述含铝焊盘的第一部分以及与所述聚合物层重叠的第二部分;以及
金属柱,位于所述凸块下金属化层上方,所述金属柱的边缘与所述凸块下金属化层的相应边缘对准,并且所述第一金属迹线包括与所述凸块下金属化层的一部分和所述金属柱的一部分垂直对准的部分。
15.根据权利要求14所述的半导体器件,其中,所述第一金属迹线具有彼此相对的第一边缘和第二边缘,并且所述第一边缘和所述第二边缘均包括与所述金属柱重叠的部分。
16.根据权利要求14所述的半导体器件,其中,所述第一金属迹线具有彼此相对的第一边缘和第二边缘,并且所述第一边缘包括与所述金属柱重叠的部分,而所述第二边缘不与所述金属柱重叠。
17.根据权利要求14所述的半导体器件,其中,所述钝化层和所述聚合物层还与所述第一金属迹线重叠。
18.根据权利要求14所述的半导体器件,还包括与所述含铝焊盘断开的第二金属迹线,其中,所述第一金属迹线和所述第二金属迹线位于所述含铝焊盘的相对侧,并且所述第二金属迹线包括与所述凸块下金属化层重叠的第一部分和不与所述凸块下金属化层重叠的第二部分。
19.根据权利要求14所述的半导体器件,还包括位于所述金属柱上方的焊帽。
CN201310131778.1A 2013-01-04 2013-04-16 用于集成电路的金属布线结构 Active CN103915412B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/734,573 2013-01-04
US13/734,573 US9224688B2 (en) 2013-01-04 2013-01-04 Metal routing architecture for integrated circuits

Publications (2)

Publication Number Publication Date
CN103915412A CN103915412A (zh) 2014-07-09
CN103915412B true CN103915412B (zh) 2016-12-28

Family

ID=51040991

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201310131778.1A Active CN103915412B (zh) 2013-01-04 2013-04-16 用于集成电路的金属布线结构

Country Status (4)

Country Link
US (2) US9224688B2 (zh)
KR (1) KR101564138B1 (zh)
CN (1) CN103915412B (zh)
TW (1) TWI540695B (zh)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9053989B2 (en) * 2011-09-08 2015-06-09 Taiwan Semiconductor Manufacturing Company, Ltd. Elongated bump structure in semiconductor device
US9224688B2 (en) * 2013-01-04 2015-12-29 Taiwan Semiconductor Manufacturing Company, Ltd. Metal routing architecture for integrated circuits
KR101683975B1 (ko) * 2014-08-05 2016-12-07 앰코 테크놀로지 코리아 주식회사 반도체 디바이스, 반도체 패키지, 반도체 디바이스 및 반도체 패키지의 제조 방법
US10043774B2 (en) * 2015-02-13 2018-08-07 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit packaging substrate, semiconductor package, and manufacturing method
US9704808B2 (en) * 2015-03-20 2017-07-11 Mediatek Inc. Semiconductor device and wafer level package including such semiconductor device
KR102410018B1 (ko) * 2015-09-18 2022-06-16 삼성전자주식회사 반도체 패키지
US9711458B2 (en) 2015-11-13 2017-07-18 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and formation method for chip package
US10276382B2 (en) 2016-08-11 2019-04-30 Advanced Semiconductor Engineering, Inc. Semiconductor device packages and stacked package assemblies including high density interconnections
US9922845B1 (en) * 2016-11-03 2018-03-20 Micron Technology, Inc. Semiconductor package and fabrication method thereof
DE102017210654B4 (de) * 2017-06-23 2022-06-09 Infineon Technologies Ag Elektronische Vorrichtung, die ein einen Hohlraum umfassendes Umverdrahtungsschicht-Pad umfasst
US10090271B1 (en) * 2017-06-28 2018-10-02 International Business Machines Corporation Metal pad modification
US10741466B2 (en) 2017-11-17 2020-08-11 Infineon Technologies Ag Formation of conductive connection tracks in package mold body using electroless plating
EP3495318A3 (en) 2017-12-08 2019-08-21 Infineon Technologies AG Semiconductor package with air cavity
US10566300B2 (en) * 2018-01-22 2020-02-18 Globalfoundries Inc. Bond pads with surrounding fill lines
JP7001530B2 (ja) * 2018-04-16 2022-01-19 ルネサスエレクトロニクス株式会社 半導体装置
US11848270B2 (en) * 2018-08-14 2023-12-19 Taiwan Semiconductor Manufacturing Co., Ltd. Chip structure and method for forming the same
US10796981B1 (en) 2019-04-04 2020-10-06 Infineon Technologies Ag Chip to lead interconnect in encapsulant of molded semiconductor package
US11133281B2 (en) 2019-04-04 2021-09-28 Infineon Technologies Ag Chip to chip interconnect in encapsulant of molded semiconductor package
CN112018052A (zh) 2019-05-31 2020-12-01 英飞凌科技奥地利有限公司 具有可激光活化模制化合物的半导体封装
CN116387270A (zh) 2019-06-11 2023-07-04 群创光电股份有限公司 电子装置
KR20210017663A (ko) * 2019-08-09 2021-02-17 삼성전자주식회사 두꺼운 금속층 및 범프를 갖는 반도체 소자들
CN111081553A (zh) * 2019-12-06 2020-04-28 联合微电子中心有限责任公司 一种半隐埋微凸点结构及其制备方法
US11587800B2 (en) 2020-05-22 2023-02-21 Infineon Technologies Ag Semiconductor package with lead tip inspection feature

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100555616C (zh) * 2006-06-15 2009-10-28 索尼株式会社 电子元件、使用其的半导体器件以及制造电子元件的方法
CN101765913A (zh) * 2007-07-30 2010-06-30 Nxp股份有限公司 底部粗糙度减小的半导体部件的应力缓冲元件
CN101882608A (zh) * 2009-05-08 2010-11-10 台湾积体电路制造股份有限公司 凸块垫结构及其制造方法
CN102668069A (zh) * 2009-10-23 2012-09-12 Ati科技无限责任公司 用于在半导体裸片中缓解应力的布线层

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3354424B2 (ja) * 1997-02-27 2002-12-09 三洋電機株式会社 半導体装置および半導体装置の製造方法
US5900643A (en) * 1997-05-19 1999-05-04 Harris Corporation Integrated circuit chip structure for improved packaging
US6118180A (en) * 1997-11-03 2000-09-12 Lsi Logic Corporation Semiconductor die metal layout for flip chip packaging
US6181569B1 (en) * 1999-06-07 2001-01-30 Kishore K. Chakravorty Low cost chip size package and method of fabricating the same
JP3606769B2 (ja) * 1999-07-13 2005-01-05 新光電気工業株式会社 半導体装置
US6586323B1 (en) * 2000-09-18 2003-07-01 Taiwan Semiconductor Manufacturing Company Method for dual-layer polyimide processing on bumping technology
JP2002198374A (ja) * 2000-10-16 2002-07-12 Sharp Corp 半導体装置およびその製造方法
US6636313B2 (en) * 2002-01-12 2003-10-21 Taiwan Semiconductor Manufacturing Co. Ltd Method of measuring photoresist and bump misalignment
US6762503B2 (en) * 2002-08-29 2004-07-13 Micron Technology, Inc. Innovative solder ball pad structure to ease design rule, methods of fabricating same and substrates, electronic device assemblies and systems employing same
JP2004214594A (ja) * 2002-11-15 2004-07-29 Sharp Corp 半導体装置およびその製造方法
JP4357862B2 (ja) * 2003-04-09 2009-11-04 シャープ株式会社 半導体装置
US6927156B2 (en) * 2003-06-18 2005-08-09 Intel Corporation Apparatus and method extending flip-chip pad structures for wirebonding on low-k dielectric silicon
TWI221335B (en) * 2003-07-23 2004-09-21 Advanced Semiconductor Eng IC chip with improved pillar bumps
US7098540B1 (en) * 2003-12-04 2006-08-29 National Semiconductor Corporation Electrical interconnect with minimal parasitic capacitance
JP3880600B2 (ja) * 2004-02-10 2007-02-14 松下電器産業株式会社 半導体装置およびその製造方法
US20060087039A1 (en) * 2004-10-22 2006-04-27 Taiwan Semiconductor Manufacturing Company, Ltd. Ubm structure for improving reliability and performance
TWI371809B (en) * 2007-06-04 2012-09-01 Advanced Semiconductor Eng Wafer structure and method for fabricating the same
US8115320B2 (en) * 2008-05-29 2012-02-14 United Microelectronics Corp. Bond pad structure located over active circuit structure
US8759949B2 (en) * 2009-04-30 2014-06-24 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer backside structures having copper pillars
US8058108B2 (en) * 2010-03-10 2011-11-15 Ati Technologies Ulc Methods of forming semiconductor chip underfill anchors
US9048135B2 (en) * 2010-07-26 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Copper pillar bump with cobalt-containing sidewall protection
US8642446B2 (en) * 2010-09-27 2014-02-04 Stats Chippac, Ltd. Semiconductor device and method of forming protective structure around semiconductor die for localized planarization of insulating layer
US8647974B2 (en) * 2011-03-25 2014-02-11 Ati Technologies Ulc Method of fabricating a semiconductor chip with supportive terminal pad
TWI493668B (zh) * 2011-05-23 2015-07-21 Via Tech Inc 接墊結構、線路載板及積體電路晶片
US8508043B2 (en) * 2011-11-16 2013-08-13 International Business Machines Corporation Metal pad structure for thickness enhancement of polymer used in electrical interconnection of semiconductor die to semiconductor chip package substrate with solder bump
US8922006B2 (en) * 2012-03-29 2014-12-30 Taiwan Semiconductor Manufacturing Company, Ltd. Elongated bumps in integrated circuit devices
US9224688B2 (en) * 2013-01-04 2015-12-29 Taiwan Semiconductor Manufacturing Company, Ltd. Metal routing architecture for integrated circuits

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100555616C (zh) * 2006-06-15 2009-10-28 索尼株式会社 电子元件、使用其的半导体器件以及制造电子元件的方法
CN101765913A (zh) * 2007-07-30 2010-06-30 Nxp股份有限公司 底部粗糙度减小的半导体部件的应力缓冲元件
CN101882608A (zh) * 2009-05-08 2010-11-10 台湾积体电路制造股份有限公司 凸块垫结构及其制造方法
CN102668069A (zh) * 2009-10-23 2012-09-12 Ati科技无限责任公司 用于在半导体裸片中缓解应力的布线层

Also Published As

Publication number Publication date
KR101564138B1 (ko) 2015-10-28
KR20140089283A (ko) 2014-07-14
US20140191390A1 (en) 2014-07-10
TWI540695B (zh) 2016-07-01
CN103915412A (zh) 2014-07-09
US9881885B2 (en) 2018-01-30
TW201428919A (zh) 2014-07-16
US20160079192A1 (en) 2016-03-17
US9224688B2 (en) 2015-12-29

Similar Documents

Publication Publication Date Title
CN103915412B (zh) 用于集成电路的金属布线结构
US10734347B2 (en) Dummy flip chip bumps for reducing stress
CN103066053B (zh) 集成电路的连接件结构
US10867810B2 (en) Substrate pad structure
CN103515314B (zh) 集成电路封装及其形成方法
US8299616B2 (en) T-shaped post for semiconductor devices
KR20190057043A (ko) 반도체 패키지 및 그 제조 방법
CN103000598B (zh) 半导体器件中的伸长凸块结构
US9324687B1 (en) Wafer-level passive device integration
US20130270699A1 (en) Conical-Shaped or Tier-Shaped Pillar Connections
CN103594441A (zh) 半导体封装件及其制造方法
CN103035598B (zh) 无ubm的连接件的形成
CN106898596A (zh) 半导体结构及其制造方法
EP3361502B1 (en) Semiconductor package with rigid under bump metallurgy (ubm) stack
CN103247593B (zh) 钝化后互连结构及其形成方法
US9548283B2 (en) Package redistribution layer structure and method of forming same
US9269688B2 (en) Bump-on-trace design for enlarge bump-to-trace distance
KR101982905B1 (ko) 반도체 패키지 및 그 제조 방법
US9093332B2 (en) Elongated bump structure for semiconductor devices
TWI529888B (zh) 半導體裝置及其製造方法
TWI556394B (zh) 半導體結構及其形成方法及半導體裝置

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant