JP2004172590A - シリコンオキシカーバイド、シリコンオキシカーバイド層の成長方法、半導体装置、および半導体装置の製造方法 - Google Patents
シリコンオキシカーバイド、シリコンオキシカーバイド層の成長方法、半導体装置、および半導体装置の製造方法 Download PDFInfo
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Abstract
【解決手段】 半導体装置の製造方法は、銅配線を覆うシリコンカーバイド層を有する下地構造を準備する工程と、前記下地構造上に、ソースガスとして、テトラメチルシクロテトラシロキサン、炭酸ガス、炭酸ガスの流量に対して3%以下の流量の酸素を用い、気相成長でシリコンオキシカーバイドを成長する工程と、を含む。他の半導体装置の製造方法は、銅配線を覆うシリコンカーバイド層を有する下地構造を準備する工程と、前記下地構造のシリコンカーバイド層表面を、O2より分子量が大きく、酸素を含む弱酸化性ガスのプラズマで親水化処理する工程と、親水化処理したシリコンカーバイド層表面上に、酸化シリコンより比誘電率の小さい低誘電率絶縁層を形成する工程と、を含む。
【選択図】 図1
Description
配線の低抵抗化のため、Al配線に代え、Cu配線が用いられるようになった。しかし、Cuより低い抵抗率を持つ配線材料を用いることは困難である。配線の低抵抗化が限界に近づくと、高速動作化のためには配線の寄生容量を減少させることが必要となる。なお、Cu配線を用いた場合、Cuの酸化防止、拡散防止等のため、Cu配線を覆って、SiNや、SiC等の拡散防止膜が用いられる。
低比誘電率材料は、一般的に、たとえばCuの拡散防止膜として形成された下地との密着性が低い。密着性が低い層間絶縁膜を用い、配線層数を増加すると、下地層との界面で膜剥がれが生じる。
本発明の他の目的は、半導体装置の多層配線に用いるのに適した誘電率の低い絶縁材料を提供することである。
本発明のさらに他の目的は、低誘電率の絶縁材料を用いた多層配線を有し、信頼性の高い半導体装置およびその製造方法を提供することである。
本発明の他の観点によれば、水素含有量が30at%以下であり、比誘電率が約3.1以下であるシリコンオキシカーバイドが提供される。
ノベラス(Novellus)社より入手可能である気相成長のシリコンオキシカーバイド(登録商標CORAL)膜は、比誘電率が約2.9と低いが、SiC層等との密着性が弱く、硬度、弾性定数等の物理的強度が不足する傾向がある。
図1(B)は、酸素流量に対する硬度(hardness)及び弾性定数(modulus)の変化を示すグラフである。図中横軸が酸素流量を単位sccmで示し、縦軸が硬度を単位GPaで、弾性定数を単位GPaで示す。実線で結んだ測定点が硬度のデータであり、破線で結んだ測定点が弾性定数のデータである。なお、白丸は比較のためのCORALの硬度及び弾性定数を示す。CORALに対しては、横軸は意味を有さない(酸素流量は250sccmで固定)。
図1(C)は、酸素流量の変化に対する比誘電率の変化を示すグラフである。横軸が酸素流量をsccmで示し、縦軸が比誘電率を示す。図から明らかなように、酸素流量を減少させるに従って、比誘電率は減少している。酸素流量100sccmより上で、特に150sccmより上で、比誘電率の増加が著しい。比誘電率を低く抑えるためには酸素流量は150sccm(CO2ガスの流量の3%)以下、特に100sccm(CO2ガスの流量の2%)以下とするのが好ましい。
TORAL成膜時の酸素流量を、0〜50sccmと少量にした時、チャンバ内ソースガスは、O2組成が減少して、相対的にCO2組成が増大している。ソースガスのプラズマがCO2プラズマに近づくとも考えられる。TORAL膜がSiC膜と高い密着性を示すことは、CO2プラズマ処理したSiC層とその上に成膜したCORAL膜とが高い密着性を示すことと、符合するとも考えられる。酸素を含まず、CO2を含むガスのプラズマ、またはCO2流量に対し、酸素流量を低く制限したガスのプラズマが良好な結果を生じている。
図10は、使用したプラズマCVD装置の構成を概略的に示す。下電極50は、8インチウエハを6枚載置するサセプタを兼ねる。サセプタは、各ウエハを搬送する搬送機構を備えている。下電極50に対向するように、6つの上電極51a、51b、51c、51d、51e、51fが配置され、6組の平行平板電極を構成している。これらがステージS0−S5を構成する。
サンプル23、24は、チャンバ内圧力をさらに5.0torrと増加させ、下電極に与えるLF電力を200Wとした場合を示す。上電極に与えるHF電力は、1100W、1200Wとした。HF電力の増加と共に堆積速度は増加し、膜厚の不均一も増加するが、屈折率は徐々に低下している。
変形例として、シリコンオキシカーバイド層15、25として、厚さ350nmのSiOC−A層を用い、シリコンオキシカーバード層18、28として、厚さ550nmのSiOC−A層を用いた。SiOC−Aの成膜条件は、TMCTS流量1ml/min、CO2流量5000sccm、圧力3.5toor、HF電力300W,LF電力200Wである。この構成においても、400℃、30分間の熱処理を5回繰り返した結果、膜剥れは全くみられなかった。2層目配線層の容量は約180fF/mmであった。シリコンオキシカーバイド層をノベラス社のCORALで作成した場合、熱サイクル試験において下地SiC層との界面で剥れが生じた。
図6(A)に示すように、シリコン基板10の上に、上述の実施例同様PSGによる層間絶縁膜11、下層配線12を形成する。下層配線12表面を覆うように、エッチストッパ用のSiC層14を厚さ約50nm、ノベラス社の登録商標ESL3を用いて成膜する。
図6(B)に示すように、デュアルダマシン用凹部にTaN層、Cu層をスパッタリングし、その上にメッキCu層を形成し、CMPにより平坦化することにより、デュアルダマシン銅配線19を形成する。銅配線19を覆って、銅拡散防止層として、厚さ70nmのSiC層24をノベラス社のESL3を用いて成膜する。
400℃、30分間の熱処理を5回繰り返し、膜剥がれが生じるか否かを観察した。膜剥がれは全く見られなかった。
図7(A)、(B)は、本発明のさらに他の実施例による半導体集積回路装置の多層配線形成工程を示すシリコン基板の断面図である。前述の実施例同様、半導体基板10の表面上に、層間絶縁膜11、下層配線12を形成し、その表面をノベラス社の登録商標ESL3を用いた厚さ約70nmのSiC層14で覆う。このSiC層14表面をCO2プラズマで処理した。図10のCVD装置において、第1ステージS0でCO2プラズマ処理を行なった。処理条件は、CO2流量5000sccm、圧力4torr、RF電力200W、処理時間5秒であった。このCO2プラズマ処理は、SiC層14表面に親水化表面14xを形成すると考えられる。
図7(B)に示すように、デュアルダマシン用凹部表面上にTaN層、Cu層をそれぞれ約30nmスパッタリングで形成し、その表面上にCu層をメッキで成膜する。SiOC層18y表面上の不要の配線層をCMP等により除去することにより、デュアルダマシン銅配線19を完成する。銅配線19を覆って、銅拡散防止層として、厚さ70nmのSiC層24をノベラス社のESL3を用いて成膜する。
TORALに代え、他の新規SiOCを用いることもできる。1例として、上記構造においてSiOC層15,18をSiOC−Bで形成した。成膜条件は上述のものである。400℃、30分間の熱処理を5回繰り返した。膜剥がれは全く見られなかった。
図9は、多層配線構造を有する半導体集積回路装置の構成を概略的に示す。シリコン基板1の表面上には、シャロートレンチアイソレーションによる素子分離領域2が形成され、活性領域表面上にゲート電極3が形成され、MOSトランジスタ構造が作成される。ゲート電極3を埋め込むように、PSG層4が成膜され、Wプラグ5が埋め込まれる。さらにその表面に酸化シリコン層6が成膜され、ビア導電体7が埋め込まれる。
(付記2)(2) 前記炭素含有量が約25at%以下である付記1記載のシリコンオキシカーバイド。
(付記4)(3) 水素含有量が30at%以下であり、比誘電率が約3.1以下であるシリコンオキシカーバイド。
(付記6)(4) 下地を準備する工程と、
ソースガスとして、テトラメチルシクロテトラシロキサン、炭酸ガス、炭酸ガスの流量に対して3%以下の流量の酸素を用い、気相成長により、前記下地上にシリコンオキシカーバイド層を成長する工程と、
を含むシリコンオキシカーバイド層を成長する方法。
(付記8) 前記気相成長が、4toorより低い圧力で行われる付記6記載のシリコンオキシカーバイド層を成長する方法。
(付記10) 前記気相成長が、4toorより高い圧力で行われる付記6記載のシリコンオキシカーバイド層を成長する方法。
(付記12) 半導体基板と、半導体基板上方に形成された銅配線と、銅配線を覆うシリコンカーバイド層と、シリコンカーバイド層を覆い、水素を含み、炭素含有量が約18at%以上であり、比誘電率が約3.1以下である第1のシリコンオキシカーバイド層とを有する半導体装置。
(付記14) さらに、前記第1のシリコンオキシカーバイド層上に接して形成され、炭素含有量が第1のシリコンオキシカーバイド層より1at%以上低い第2のシリコンオキシカーバイド層を有する付記12記載の半導体装置。
半導体基板上方に形成された銅配線と、
銅配線を覆うシリコンカーバイド層と、シリコンカーバイド層を覆い、水素を含み、水素含有量が30at%以下であり、比誘電率が約3.1以下である第1のシリコンオキシカーバイド層と、
を有する半導体装置。
(付記18) さらに、前記第1のシリコンオキシカーバイド層上に接して形成され、水素含有量が第1のシリコンオキシカーバイド層より2at%以上高い第2のシリコンオキシカーバイド層を有する付記16記載の半導体装置。
半導体基板上方に形成された銅配線と、
銅配線を覆うシリコンカーバイド層と、シリコンカーバイド層を覆い、水素を含み、炭素含有量が17at%以上、または水素含有量が30at%以下であり、比誘電率が約3.1以下である第1のシリコンオキシカーバイド層と、
を有する半導体装置。
前記下地構造上に、ソースガスとして、テトラメチルシクロテトラシロキサン、炭酸ガス、炭酸ガスの流量に対して3%以下の流量の酸素を用い、気相成長でシリコンオキシカーバイド層を成長する工程と、
を含む半導体装置の製造方法。
N (付記24)(8) 前記酸素の流量が0%である付記23記載の半導体装置の製造方法。
N (付記25)(9) 前記シリコンオキシカーバイド層を成長する工程の後、続いてCO2プラズマで表面を軽く酸化する工程を含む付記23記載の半導体装置の製造方法。
(付記27) 半導体基板と、半導体基板上方に形成された銅配線と、銅配線を覆うシリコンカーバイド層とを有する下地構造を準備する工程と、
前記下地構造のシリコンカーバイド層表面を、O2より分子量が大きく、酸素を含む弱酸化性ガスのプラズマで親水化処理する工程と、
親水化処理したシリコンカーバイド層表面上に、酸化シリコンより比誘電率の小さい低誘電率絶縁層を形成する工程と、
を含む半導体装置の製造方法。
(付記29) 前記プラズマで処理する工程が、前記低誘電率絶縁層を形成する工程と同一チャンバ内で行われる付記27記載の半導体装置の製造方法。
12 下層配線
14、17 SiC層
15、18 SiOC(TORAL)層
ARC 反射防止膜
PR ホトレジスト
19 デュアルダマシン配線
21 SiC層
22 有機絶縁層
23 酸化シリコン層
24 SiC層
25 SiOC層
27 SiC層
28 SiOC層
29 デュアルダマシン配線
34 有機絶縁層
36 SiC層
37 有機絶縁層
38 酸化シリコン層
100 半導体基板
IL 層間絶縁膜
W 配線
HM ハードマスク(SiN層)
PD パッド
Claims (10)
- 水素を含み、炭素含有量が約18at%以上であり、比誘電率が約3.1以下であるシリコンオキシカーバイド。
- 前記炭素含有量が約25at%以下である請求項1記載のシリコンオキシカーバイド。
- 水素含有量が30at%以下であり、比誘電率が約3.1以下であるシリコンオキシカーバイド。
- 下地を準備する工程と、
ソースガスとして、テトラメチルシクロテトラシロキサン、炭酸ガス、炭酸ガスの流量に対して3%以下の流量の酸素を用い、前記下地上に気相成長でシリコンオキシカーバイド層を成長する工程と、
を含むシリコンオキシカーバイド層を成長する方法。 - 前記酸素の流量が0%である請求項4記載のシリコンオキシカーバイド層を成長する方法。
- 半導体基板と、
半導体基板上方に形成された銅配線と、
銅配線を覆うシリコンカーバイド層と、
シリコンカーバイド層を覆い、水素を含み、炭素含有量が17at%以上、または水素含有量が30at%以下であり、比誘電率が約3.1以下である第1のシリコンオキシカーバイド層と、
を有する半導体装置。 - 半導体基板と、半導体基板上方に形成された銅配線と、銅配線を覆うシリコンカーバイド層とを有する下地構造を準備する工程と、
前記下地構造上に、ソースガスとして、テトラメチルシクロテトラシロキサン、炭酸ガス、炭酸ガスの流量に対して3%以下の流量の酸素を用い、気相成長でシリコンオキシカーバイド層を成長する工程と、
を含む半導体装置の製造方法。 - 前記酸素の流量が0%である請求項7又は8記載の半導体装置の製造方法。
- 前記シリコンオキシカーバイド層を成長する工程に続いて、CO2プラズマで表面を軽く酸化する工程を含む請求項7記載の半導体装置の製造方法。
- 半導体基板と、半導体基板上方に形成された銅配線と、銅配線を覆うシリコンカーバイド層とを有する下地構造を準備する工程と、
前記下地構造のシリコンカーバイド層表面を、O2より分子量が大きく、酸素を含む酸化性ガスのプラズマで親水化処理する工程と、
親水化処理したシリコンカーバイド層表面上に、酸化シリコンより比誘電率の小さい低誘電率絶縁層を形成する工程と、
を含む半導体装置の製造方法。
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Also Published As
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US20040155340A1 (en) | 2004-08-12 |
US8349722B2 (en) | 2013-01-08 |
JP4338495B2 (ja) | 2009-10-07 |
US20090093130A1 (en) | 2009-04-09 |
US6949830B2 (en) | 2005-09-27 |
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