JP2004021916A5 - - Google Patents

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Publication number
JP2004021916A5
JP2004021916A5 JP2002179969A JP2002179969A JP2004021916A5 JP 2004021916 A5 JP2004021916 A5 JP 2004021916A5 JP 2002179969 A JP2002179969 A JP 2002179969A JP 2002179969 A JP2002179969 A JP 2002179969A JP 2004021916 A5 JP2004021916 A5 JP 2004021916A5
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JP
Japan
Prior art keywords
memory
data
variable
signal line
termination
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2002179969A
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English (en)
Japanese (ja)
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JP2004021916A (ja
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Publication date
Application filed filed Critical
Priority to JP2002179969A priority Critical patent/JP2004021916A/ja
Priority claimed from JP2002179969A external-priority patent/JP2004021916A/ja
Priority to US10/299,712 priority patent/US6844754B2/en
Publication of JP2004021916A publication Critical patent/JP2004021916A/ja
Publication of JP2004021916A5 publication Critical patent/JP2004021916A5/ja
Pending legal-status Critical Current

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JP2002179969A 2002-06-20 2002-06-20 データバス Pending JP2004021916A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2002179969A JP2004021916A (ja) 2002-06-20 2002-06-20 データバス
US10/299,712 US6844754B2 (en) 2002-06-20 2002-11-20 Data bus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002179969A JP2004021916A (ja) 2002-06-20 2002-06-20 データバス

Publications (2)

Publication Number Publication Date
JP2004021916A JP2004021916A (ja) 2004-01-22
JP2004021916A5 true JP2004021916A5 (enExample) 2005-10-20

Family

ID=29728235

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002179969A Pending JP2004021916A (ja) 2002-06-20 2002-06-20 データバス

Country Status (2)

Country Link
US (1) US6844754B2 (enExample)
JP (1) JP2004021916A (enExample)

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US8327104B2 (en) 2006-07-31 2012-12-04 Google Inc. Adjusting the timing of signals associated with a memory system
US9171585B2 (en) 2005-06-24 2015-10-27 Google Inc. Configurable memory circuit system and method
US8359187B2 (en) 2005-06-24 2013-01-22 Google Inc. Simulating a different number of memory circuit devices
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US20080082763A1 (en) 2006-10-02 2008-04-03 Metaram, Inc. Apparatus and method for power management of memory circuits by a system or component thereof
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US8130560B1 (en) 2006-11-13 2012-03-06 Google Inc. Multi-rank partial width memory modules
US8438328B2 (en) 2008-02-21 2013-05-07 Google Inc. Emulation of abstracted DIMMs using abstracted DRAMs
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KR100780949B1 (ko) * 2006-03-21 2007-12-03 삼성전자주식회사 데이터 독출 모드에서 ｏｄｔ 회로의 온/오프 상태를테스트할 수 있는 반도체 메모리 장치 및 ｏｄｔ 회로의상태 테스트 방법
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