JP2004021916A - データバス - Google Patents

データバス Download PDF

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Publication number
JP2004021916A
JP2004021916A JP2002179969A JP2002179969A JP2004021916A JP 2004021916 A JP2004021916 A JP 2004021916A JP 2002179969 A JP2002179969 A JP 2002179969A JP 2002179969 A JP2002179969 A JP 2002179969A JP 2004021916 A JP2004021916 A JP 2004021916A
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JP
Japan
Prior art keywords
data
impedance
terminating
signal
variable resistor
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JP2002179969A
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English (en)
Japanese (ja)
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JP2004021916A5 (enExample
Inventor
Narihito Yamagata
山形　整人
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Technology Corp
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Renesas Technology Corp
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Publication date
Application filed by Renesas Technology Corp filed Critical Renesas Technology Corp
Priority to JP2002179969A priority Critical patent/JP2004021916A/ja
Priority to US10/299,712 priority patent/US6844754B2/en
Publication of JP2004021916A publication Critical patent/JP2004021916A/ja
Publication of JP2004021916A5 publication Critical patent/JP2004021916A5/ja
Pending legal-status Critical Current

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers

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  • Dram (AREA)
  • Logic Circuits (AREA)
  • Memory System (AREA)
JP2002179969A 2002-06-20 2002-06-20 データバス Pending JP2004021916A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2002179969A JP2004021916A (ja) 2002-06-20 2002-06-20 データバス
US10/299,712 US6844754B2 (en) 2002-06-20 2002-11-20 Data bus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002179969A JP2004021916A (ja) 2002-06-20 2002-06-20 データバス

Publications (2)

Publication Number Publication Date
JP2004021916A true JP2004021916A (ja) 2004-01-22
JP2004021916A5 JP2004021916A5 (enExample) 2005-10-20

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ID=29728235

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002179969A Pending JP2004021916A (ja) 2002-06-20 2002-06-20 データバス

Country Status (2)

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US (1) US6844754B2 (enExample)
JP (1) JP2004021916A (enExample)

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KR100798739B1 (ko) 2006-09-27 2008-01-29 주식회사 하이닉스반도체 반도체메모리소자 및 그의 구동 방법
JP2009540633A (ja) * 2006-06-02 2009-11-19 ラムバス・インコーポレーテッド 段階的オンダイターミネーションを備えた集積回路
JP5752862B1 (ja) * 2014-06-18 2015-07-22 ゼンテルジャパン株式会社 半導体回路装置及び半導体メモリシステム
US9536604B1 (en) 2016-01-06 2017-01-03 International Business Machines Corporation Impedance matching system for DDR memory

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US7088170B2 (en) * 2003-06-30 2006-08-08 International Business Machines Corporation Multiplexer and demultiplexer
US20060132577A1 (en) * 2004-12-04 2006-06-22 Hon Hai Precision Industry Co., Ltd. Circuit topology for high-speed printed circuit board
CN1828478A (zh) * 2005-03-05 2006-09-06 鸿富锦精密工业（深圳）有限公司 主板双倍资料速率内存的电源电路
US8060774B2 (en) 2005-06-24 2011-11-15 Google Inc. Memory systems and memory modules
US8111566B1 (en) 2007-11-16 2012-02-07 Google, Inc. Optimal channel design for memory devices for providing a high-speed memory interface
US20080028136A1 (en) 2006-07-31 2008-01-31 Schakel Keith R Method and apparatus for refresh management of memory modules
US9542352B2 (en) * 2006-02-09 2017-01-10 Google Inc. System and method for reducing command scheduling constraints of memory circuits
US8081474B1 (en) 2007-12-18 2011-12-20 Google Inc. Embossed heat spreader
US8335894B1 (en) * 2008-07-25 2012-12-18 Google Inc. Configurable memory system with interface circuit
US8397013B1 (en) 2006-10-05 2013-03-12 Google Inc. Hybrid memory module
US20080126690A1 (en) * 2006-02-09 2008-05-29 Rajan Suresh N Memory module with memory stack
US8244971B2 (en) 2006-07-31 2012-08-14 Google Inc. Memory circuit system and method
US8077535B2 (en) 2006-07-31 2011-12-13 Google Inc. Memory refresh apparatus and method
US8041881B2 (en) 2006-07-31 2011-10-18 Google Inc. Memory device with emulated characteristics
US9507739B2 (en) 2005-06-24 2016-11-29 Google Inc. Configurable memory circuit system and method
US8055833B2 (en) 2006-10-05 2011-11-08 Google Inc. System and method for increasing capacity, performance, and flexibility of flash storage
US8327104B2 (en) 2006-07-31 2012-12-04 Google Inc. Adjusting the timing of signals associated with a memory system
US9171585B2 (en) 2005-06-24 2015-10-27 Google Inc. Configurable memory circuit system and method
US8359187B2 (en) 2005-06-24 2013-01-22 Google Inc. Simulating a different number of memory circuit devices
US8089795B2 (en) 2006-02-09 2012-01-03 Google Inc. Memory module with memory stack and interface with enhanced capabilities
US8386722B1 (en) 2008-06-23 2013-02-26 Google Inc. Stacked DIMM memory interface
US20080082763A1 (en) 2006-10-02 2008-04-03 Metaram, Inc. Apparatus and method for power management of memory circuits by a system or component thereof
US7386656B2 (en) 2006-07-31 2008-06-10 Metaram, Inc. Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit
US10013371B2 (en) 2005-06-24 2018-07-03 Google Llc Configurable memory circuit system and method
US8796830B1 (en) 2006-09-01 2014-08-05 Google Inc. Stackable low-profile lead frame package
US8090897B2 (en) 2006-07-31 2012-01-03 Google Inc. System and method for simulating an aspect of a memory circuit
US8130560B1 (en) 2006-11-13 2012-03-06 Google Inc. Multi-rank partial width memory modules
US8438328B2 (en) 2008-02-21 2013-05-07 Google Inc. Emulation of abstracted DIMMs using abstracted DRAMs
CN100518436C (zh) * 2005-08-05 2009-07-22 鸿富锦精密工业（深圳）有限公司 高速印刷电路板中传输线的布线架构
DE112006002300B4 (de) 2005-09-02 2013-12-19 Google, Inc. Vorrichtung zum Stapeln von DRAMs
US7372293B2 (en) * 2005-12-07 2008-05-13 Intel Corporation Polarity driven dynamic on-die termination
US9632929B2 (en) 2006-02-09 2017-04-25 Google Inc. Translating an address associated with a command communicated between a system and memory circuits
US20070205805A1 (en) * 2006-03-03 2007-09-06 Oliver Kiehl Electrical system including driver that provides a first drive strength and a second drive strength
US7479799B2 (en) * 2006-03-14 2009-01-20 Inphi Corporation Output buffer with switchable output impedance
KR100780949B1 (ko) * 2006-03-21 2007-12-03 삼성전자주식회사 데이터 독출 모드에서 ｏｄｔ 회로의 온/오프 상태를테스트할 수 있는 반도체 메모리 장치 및 ｏｄｔ 회로의상태 테스트 방법
US20070247185A1 (en) * 2006-03-30 2007-10-25 Hideo Oie Memory system with dynamic termination
US20080025136A1 (en) * 2006-07-31 2008-01-31 Metaram, Inc. System and method for storing at least a portion of information received in association with a first operation for use in performing a second operation
US7724589B2 (en) 2006-07-31 2010-05-25 Google Inc. System and method for delaying a signal communicated from a system to at least one of a plurality of memory circuits
US20080162801A1 (en) * 2006-12-29 2008-07-03 Ripan Das Series termination for a low power memory interface
US20080197877A1 (en) * 2007-02-16 2008-08-21 Intel Corporation Per byte lane dynamic on-die termination
US20090091963A1 (en) * 2007-10-04 2009-04-09 Advanced Micro Devices, Inc. Memory device
TW200921595A (en) * 2007-11-14 2009-05-16 Darfon Electronics Corp Multi-lamp backlight apparatus
JP5217520B2 (ja) * 2008-03-06 2013-06-19 株式会社リコー 電子機器
US8041865B2 (en) * 2008-08-04 2011-10-18 Qimonda Ag Bus termination system and method
US7915912B2 (en) * 2008-09-24 2011-03-29 Rambus Inc. Signal lines with internal and external termination
DE202010017690U1 (de) * 2009-06-09 2012-05-29 Google, Inc. Programmierung von Dimm-Abschlusswiderstandswerten
KR20110076481A (ko) * 2009-12-29 2011-07-06 삼성전자주식회사 메모리 모듈 및 이를 포함하는 메모리 시스템
US10380060B2 (en) * 2016-06-17 2019-08-13 Etron Technology, Inc. Low-pincount high-bandwidth memory and memory bus
US10340022B2 (en) * 2017-05-16 2019-07-02 Samsung Electronics Co., Ltd. Nonvolatile memory including on-die-termination circuit and storage device including the nonvolatile memory
KR102471160B1 (ko) * 2017-05-16 2022-11-25 삼성전자주식회사 온-다이-터미네이션 회로를 포함하는 비휘발성 메모리 및 상기 비휘발성 메모리를 포함하는 스토리지 장치
US10528515B2 (en) * 2017-06-27 2020-01-07 Intel Corporation Memory channel driver with echo cancellation

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US5467455A (en) * 1993-11-03 1995-11-14 Motorola, Inc. Data processing system and method for performing dynamic bus termination
JPH08194034A (ja) 1995-01-19 1996-07-30 Hitachi Ltd 半導体試験装置
EP1050824A3 (en) * 1999-04-22 2004-01-28 Matsushita Electric Industrial Co., Ltd. Bidirectional signal transmission circuit and bus system
JP2001177580A (ja) 1999-12-20 2001-06-29 Sony Corp インピーダンス適合システム
US6356106B1 (en) * 2000-09-12 2002-03-12 Micron Technology, Inc. Active termination in a multidrop memory system
US6690191B2 (en) * 2001-12-21 2004-02-10 Sun Microsystems, Inc. Bi-directional output buffer

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009540633A (ja) * 2006-06-02 2009-11-19 ラムバス・インコーポレーテッド 段階的オンダイターミネーションを備えた集積回路
KR100798739B1 (ko) 2006-09-27 2008-01-29 주식회사 하이닉스반도체 반도체메모리소자 및 그의 구동 방법
US7710797B2 (en) 2006-09-27 2010-05-04 Hynix Semiconductors, Inc. Semiconductor memory device and method for driving the same
JP5752862B1 (ja) * 2014-06-18 2015-07-22 ゼンテルジャパン株式会社 半導体回路装置及び半導体メモリシステム
WO2015193992A1 (ja) * 2014-06-18 2015-12-23 ゼンテルジャパン株式会社 半導体回路装置及び半導体メモリシステム
US9536604B1 (en) 2016-01-06 2017-01-03 International Business Machines Corporation Impedance matching system for DDR memory

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Publication number Publication date
US20030234664A1 (en) 2003-12-25
US6844754B2 (en) 2005-01-18

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