JP2003296096A5 - - Google Patents

Download PDF

Info

Publication number
JP2003296096A5
JP2003296096A5 JP2002099202A JP2002099202A JP2003296096A5 JP 2003296096 A5 JP2003296096 A5 JP 2003296096A5 JP 2002099202 A JP2002099202 A JP 2002099202A JP 2002099202 A JP2002099202 A JP 2002099202A JP 2003296096 A5 JP2003296096 A5 JP 2003296096A5
Authority
JP
Japan
Prior art keywords
data
latch circuit
instructions
input
salc
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2002099202A
Other languages
English (en)
Japanese (ja)
Other versions
JP2003296096A (ja
JP3719509B2 (ja
Filing date
Publication date
Application filed filed Critical
Priority to JP2002099202A priority Critical patent/JP3719509B2/ja
Priority claimed from JP2002099202A external-priority patent/JP3719509B2/ja
Priority to EP03006757A priority patent/EP1351134A3/en
Priority to US10/404,182 priority patent/US7171535B2/en
Publication of JP2003296096A publication Critical patent/JP2003296096A/ja
Publication of JP2003296096A5 publication Critical patent/JP2003296096A5/ja
Application granted granted Critical
Publication of JP3719509B2 publication Critical patent/JP3719509B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

JP2002099202A 2002-04-01 2002-04-01 シリアル演算パイプライン、演算装置、算術論理演算回路およびシリアル演算パイプラインによる演算方法 Expired - Fee Related JP3719509B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2002099202A JP3719509B2 (ja) 2002-04-01 2002-04-01 シリアル演算パイプライン、演算装置、算術論理演算回路およびシリアル演算パイプラインによる演算方法
EP03006757A EP1351134A3 (en) 2002-04-01 2003-03-25 Superpipelined arithmetic-logic unit with feedback
US10/404,182 US7171535B2 (en) 2002-04-01 2003-04-01 Serial operation pipeline, arithmetic device, arithmetic-logic circuit and operation method using the serial operation pipeline

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002099202A JP3719509B2 (ja) 2002-04-01 2002-04-01 シリアル演算パイプライン、演算装置、算術論理演算回路およびシリアル演算パイプラインによる演算方法

Publications (3)

Publication Number Publication Date
JP2003296096A JP2003296096A (ja) 2003-10-17
JP2003296096A5 true JP2003296096A5 (cg-RX-API-DMAC7.html) 2005-04-07
JP3719509B2 JP3719509B2 (ja) 2005-11-24

Family

ID=28035903

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002099202A Expired - Fee Related JP3719509B2 (ja) 2002-04-01 2002-04-01 シリアル演算パイプライン、演算装置、算術論理演算回路およびシリアル演算パイプラインによる演算方法

Country Status (3)

Country Link
US (1) US7171535B2 (cg-RX-API-DMAC7.html)
EP (1) EP1351134A3 (cg-RX-API-DMAC7.html)
JP (1) JP3719509B2 (cg-RX-API-DMAC7.html)

Families Citing this family (42)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1669868A4 (en) * 2003-09-30 2009-03-25 Sanyo Electric Co PROCESSOR AND INTEGRATED CIRCUIT WITH CONVERTIBLE CIRCUIT AND PROCESSING PROCESS THEREFORE
JP4478050B2 (ja) * 2005-03-18 2010-06-09 株式会社リコー Simd型マイクロプロセッサ及びデータ処理方法
JP2006287675A (ja) * 2005-04-01 2006-10-19 Renesas Technology Corp 半導体集積回路
US7681017B2 (en) * 2005-11-01 2010-03-16 Lsi Corporation Pseudo pipeline and pseudo pipelined SDRAM controller
CN101615173B (zh) * 2006-02-06 2011-11-30 威盛电子股份有限公司 处理任何数个不同格式数据的串流处理器及其方法及模块
US8656143B2 (en) 2006-03-13 2014-02-18 Laurence H. Cooke Variable clocked heterogeneous serial array processor
US20070226455A1 (en) * 2006-03-13 2007-09-27 Cooke Laurence H Variable clocked heterogeneous serial array processor
JP2007249843A (ja) * 2006-03-17 2007-09-27 Fujitsu Ltd 再構成可能な演算装置
EP2011018B1 (en) 2006-04-12 2016-07-13 Soft Machines, Inc. Apparatus and method for processing an instruction matrix specifying parallel and dependent operations
US7870556B2 (en) * 2006-05-16 2011-01-11 Ab Initio Technology Llc Managing computing resources in graph-based computations
US8346831B1 (en) * 2006-07-25 2013-01-01 Vivante Corporation Systems and methods for computing mathematical functions
US20080052490A1 (en) * 2006-08-28 2008-02-28 Tableau, Llc Computational resource array
US20080052429A1 (en) * 2006-08-28 2008-02-28 Tableau, Llc Off-board computational resources
US20080126472A1 (en) * 2006-08-28 2008-05-29 Tableau, Llc Computer communication
US20080052525A1 (en) * 2006-08-28 2008-02-28 Tableau, Llc Password recovery
WO2008061154A2 (en) 2006-11-14 2008-05-22 Soft Machines, Inc. Apparatus and method for processing instructions in a multi-threaded architecture using context switching
DE212007000102U1 (de) * 2007-09-11 2010-03-18 Core Logic, Inc. Rekonfigurierbarer Array-Prozessor für Gleitkomma-Operationen
US9152427B2 (en) 2008-10-15 2015-10-06 Hyperion Core, Inc. Instruction issue to array of arithmetic cells coupled to load/store cells with associated registers as extended register file
JP5590849B2 (ja) * 2009-10-08 2014-09-17 キヤノン株式会社 複数の処理モジュールを有する並列処理回路を備えるデータ処理装置、その制御装置、およびその制御方法、プログラム
EP3156896B1 (en) 2010-09-17 2020-04-08 Soft Machines, Inc. Single cycle multi-branch prediction including shadow cache for early far branch prediction
US9842005B2 (en) 2011-03-25 2017-12-12 Intel Corporation Register file segments for supporting code block execution by using virtual cores instantiated by partitionable engines
KR101966712B1 (ko) 2011-03-25 2019-04-09 인텔 코포레이션 분할가능한 엔진에 의해 인스턴스화된 가상 코어를 이용한 코드 블록의 실행을 지원하는 메모리 프래그먼트
TWI533129B (zh) 2011-03-25 2016-05-11 軟體機器公司 使用可分割引擎實體化的虛擬核心執行指令序列程式碼區塊
CN107729267B (zh) 2011-05-20 2022-01-25 英特尔公司 资源的分散分配以及用于支持由多个引擎执行指令序列的互连结构
CN103649931B (zh) 2011-05-20 2016-10-12 索夫特机械公司 用于支持由多个引擎执行指令序列的互连结构
CN104040490B (zh) 2011-11-22 2017-12-15 英特尔公司 用于多引擎微处理器的加速的代码优化器
US20150039859A1 (en) 2011-11-22 2015-02-05 Soft Machines, Inc. Microprocessor accelerated code optimizer
WO2014150991A1 (en) 2013-03-15 2014-09-25 Soft Machines, Inc. A method for implementing a reduced size register view data structure in a microprocessor
WO2014151043A1 (en) 2013-03-15 2014-09-25 Soft Machines, Inc. A method for emulating a guest centralized flag architecture by using a native distributed flag architecture
US10275255B2 (en) 2013-03-15 2019-04-30 Intel Corporation Method for dependency broadcasting through a source organized source view data structure
US9886279B2 (en) 2013-03-15 2018-02-06 Intel Corporation Method for populating and instruction view data structure by using register template snapshots
WO2014150806A1 (en) 2013-03-15 2014-09-25 Soft Machines, Inc. A method for populating register view data structure by using register template snapshots
US10140138B2 (en) 2013-03-15 2018-11-27 Intel Corporation Methods, systems and apparatus for supporting wide and efficient front-end operation with guest-architecture emulation
KR101708591B1 (ko) 2013-03-15 2017-02-20 소프트 머신즈, 인크. 블록들로 그룹화된 멀티스레드 명령어들을 실행하기 위한 방법
WO2014150971A1 (en) 2013-03-15 2014-09-25 Soft Machines, Inc. A method for dependency broadcasting through a block organized source view data structure
US9891924B2 (en) 2013-03-15 2018-02-13 Intel Corporation Method for implementing a reduced size register view data structure in a microprocessor
US9569216B2 (en) 2013-03-15 2017-02-14 Soft Machines, Inc. Method for populating a source view data structure by using register template snapshots
US9811342B2 (en) 2013-03-15 2017-11-07 Intel Corporation Method for performing dual dispatch of blocks and half blocks
US9904625B2 (en) 2013-03-15 2018-02-27 Intel Corporation Methods, systems and apparatus for predicting the way of a set associative cache
US9747104B2 (en) * 2014-05-12 2017-08-29 Qualcomm Incorporated Utilizing pipeline registers as intermediate storage
JP2017174291A (ja) 2016-03-25 2017-09-28 ルネサスエレクトロニクス株式会社 画像処理装置、画像処理方法、及び自動車制御装置
US11340875B2 (en) * 2020-06-02 2022-05-24 Sri International Searchable storage of sequential application programs

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5179734A (en) * 1984-03-02 1993-01-12 Texas Instruments Incorporated Threaded interpretive data processor
JPH0767063B2 (ja) * 1990-01-23 1995-07-19 ヤマハ株式会社 デジタル信号処理回路
US5038311A (en) * 1990-08-10 1991-08-06 General Electric Company Pipelined fast fourier transform processor
JP3096387B2 (ja) * 1994-01-28 2000-10-10 三菱電機株式会社 数値演算処理装置
JPH08137819A (ja) * 1994-11-04 1996-05-31 Hitachi Ltd 接続制御装置
US6044166A (en) * 1995-01-17 2000-03-28 Sarnoff Corporation Parallel-pipelined image processing system
JPH10240558A (ja) * 1997-02-24 1998-09-11 Hitachi Ltd データ処理装置の制御方法、データ処理装置、電子線描画装置

Similar Documents

Publication Publication Date Title
TWI515669B (zh) 用於狀態機中資料分析之系統與方法
TW200839571A (en) Device and method for access time reduction by speculatively decoding non-memory read commands on a serial interface
KR20010078508A (ko) 매트릭스 연산 장치 및 매트릭스 연산기능을 갖는 디지털신호처리 장치
CN107315575A (zh) 一种用于执行向量合并运算的装置和方法
JP2002163127A (ja) トレース制御回路
JP3068138B2 (ja) ベクトル演算処理装置
JP2000322235A (ja) 情報処理装置
KR900010587A (ko) 생산라인의 고성능 명령어 실행방법 및 장치
JPS58500778A (ja) 3つの時間多重部分における命令を実行するためのデイジタルコンピユ−タ
JP2003216411A5 (cg-RX-API-DMAC7.html)
WO2017024798A1 (zh) 超长指令字指令集的指令处理方法及装置
JPS60237503A (ja) シ−ケンスコントロ−ラの高速処理方式
JP7157457B2 (ja) データ処理装置
JP2667810B2 (ja) ベクトル処理装置
US20060101235A1 (en) Microprocessor
JPH1153344A (ja) 行列演算装置及びそれを有する数値演算プロセッサ
JPS59206968A (ja) Eprom搭載型マイクロコンピユ−タ
JPS61249140A (ja) マイクロプログラム制御装置
JP2542120B2 (ja) 情報処理装置
JPS6047615B2 (ja) 逐次化命令実行制御方式
JPH0660669A (ja) 半導体記憶装置
CN102768623A (zh) 一种vliw流水线的发射方法和装置
JPH1063503A (ja) 演算処理装置及び演算処理方法
JPS60175146A (ja) プログラマブル・コントロ−ラ
JPS62145430A (ja) デ−タ処理装置