CN107729267B - 资源的分散分配以及用于支持由多个引擎执行指令序列的互连结构 - Google Patents

资源的分散分配以及用于支持由多个引擎执行指令序列的互连结构 Download PDF

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CN107729267B
CN107729267B CN201710764883.7A CN201710764883A CN107729267B CN 107729267 B CN107729267 B CN 107729267B CN 201710764883 A CN201710764883 A CN 201710764883A CN 107729267 B CN107729267 B CN 107729267B
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M·阿布达拉
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Intel Corp
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Abstract

本申请涉及微处理器和用于在集成电路中分散资源分配的方法。该方法包括从多个可划分引擎的多个资源消费方接收访问多个资源的多个请求，其中资源跨多个引擎分布并且经由全局互连结构进行访问。在每个资源处，增加用于访问所述每个资源的请求的数量。在所述每个资源处，将请求的数量与阈值限制器比较。在所述每个资源处，取消所接收的超过阈值限制器的后续请求。随后，实施当前时钟周期内未被取消的请求。

Description

资源的分散分配以及用于支持由多个引擎执行指令序列的互 连结构
本申请是国际申请号为PCT/US2012/038711，国际申请日为2012/05/18，进入国家阶段的申请号为201280034739.3，题为“资源的分散分配以及用于支持由多个引擎执行指令序列的互连结构”的发明专利申请的分案申请。
本申请要求由Mohammad A.Abdallah于2011年5月20日提交的题为“DECENTRALIZED ALLOCATION OF RESOUIRCES AND INTERCONNECT STRUCTURES TOSUPPORT THE EXECUTION OF INSTRUCTION SEQUENCES BY A PLURALITY OF ENGINES”的共同未决的被共同转让的第61/488662号美国临时专利申请的权益，并且其全文结合于此。
相关申请的交叉引用
本申请涉及由Mohammad A.Abdallah于2007年11月14日提交的题为“APPARATUSAND METHOD FOR PROCESSING COMPLEX INSTRUCTION FORMATS IN A MULTITHREADEDARCHITECTURE SUPPORTING VARIOUS CONTEXT SWITCH MODES AND VIRTUALIZATIONSCHEMES”的共同未决的被共同转让的第2010/0161948号美国公开，并且其全文结合于此。
本申请涉及由Mohammad A.Abdallah于2007年4月12日提交的题为“APPARATUSAND METHOD FOR PROCESSING AN INSTRUCTION MATRIX SPECIFYING PARALLEL INDEPENDENT OPERATIONS”的共同未决的被共同转让的第2009/0113170号美国公开，并且其全文结合于此。
技术领域
本发明总体上涉及数字计算机系统，更特别地涉及一种用于选择包括指令序列的指令的系统和方法。
背景技术
需要处理器来处理相依赖的或者完全独立的多个任务。这样的处理器的内部状态通常由寄存器构成，该寄存器在程序执行的每个特定瞬间可能保存有不同的数值。在程序执行的每个瞬间，内部状态图像被称作处理器的架构状态。
当代码执行被切换而运行另一功能(例如，另一线程、处理或程序)时，则机器/处理器的状态必须被保存，以使得新的功能能够利用内部寄存器来构建其新的状态。一旦新的功能终止，则其状态能够被丢弃并且之前环境的状态将被恢复并继续执行。这样的切换处理被称作环境切换(context switch)并且通常包括数十个或数百个周期，尤其是利用采用大量寄存器(例如，64个、128个、256个)和/或乱序执行的现代架构的情况下。
在线程感知(thread-aware)的硬件架构中，对于硬件而言，针对有限数量的硬件支持的线程而支持多种环境状态是正常的。在这种情况下，硬件针对每个所支持的线程复制所有架构状态单元。这使得在执行新线程时无需进行环境切换。然而，这仍然具有多种缺陷，即针对以硬件形式所支持的每个附加线程复制所有架构状态单元(即，寄存器)的面积、功率和复杂度。此外，如果软件线程的数量超过了被明确支持的硬件线程的数量，则仍然必须执行环境切换。
由于在需要大量线程的精细粒度的基础上需要并行性，所以这变得很常见。具有重复的环境状态硬件存储器的硬件线程感知架构对非线程化的软件代码并没有帮助，而仅仅是减少了被线程化的软件的环境切换的数量。然而，那些线程通常针对粗粒度并行化进行构建，并且导致针对发起和同步的繁重软件开销，让诸如函数调用和循环并行执行之类的细粒度并行性没有有效的线程化发起/自动生成。这样描述的开销伴随着难以使用用于非明确/易于并行化/线程化的软件代码的现有技术编译器或用户并行化技术对这样的代码进行自动并行化。
发明内容
在一个实施例中，本发明被实施为一种用于在集成电路(例如，微处理器等)中分散资源分配的方法。该方法包括从多个可划分引擎的多个资源消费方接收访问多个资源的多个请求，其中该资源跨多个引擎分布并且经由全局互连结构进行访问。在每个资源处，增加用于访问所述每个资源的请求的数量。在所述每个资源处，将请求的数量与阈值限制器比较。在所述每个资源处，取消所接收的超过该阈值限制器的后续请求。随后，实施当前时钟周期内未被取消的请求。
以上是概述并且因此必然包含了细节的简化、概括以及省略；因此，本领域技术人员将会意识到，该概述仅是说明性的而并非意在以任何方式进行限制。仅由权利要求所限定的本发明的其它方面、发明特征以及优势，将在以下所给出的非限制性的详细描述中变得显而易见。
附图说明
在附图的图示中通过示例而非限制对本发明进行图示，并且其中同样的附图标记指代相似的单元。
图1A示出了全局前端生成代码块和继承向量以支持代码序列在其相应引擎上执行的方式的概览。
图1B示出了依据本发明的一个实施例的引擎及其组件的概览示图，包括用于多核处理器的分段调度器和寄存器文件、互连和分片存储器子系统。
图2示出了依据本发明的一个实施例的描绘图1A和图1B的讨论中所描述的互连以及多个局部互连的附加特征的概览示图。
图3示出了依据本发明的一个实施例的包括对争议资源实施有效访问的资源预约机制的组件。
图4示出了依据本发明的一个实施例的互连以及到存储器片段之中的端口。
图5示出了依据本发明的一个实施例的互连以及到分段之中的端口。
图6示出了依据本发明的一个实施例的描绘分段互连的示图。
图7示出了依据本发明的一个实施例的图示对针对互连分段的请求进行竞争和分配的方式的表格。
图8示出了依据本发明的一个实施例的图示对针对点对点总线的请求进行处置的方式的表格。
图9示出了依据本发明的一个实施例的实施图7的表格的功能的示例性逻辑实施方式的示图。
图10示出了依据本发明的一个实施例的实施对针对点对点总线的请求进行处置的方式的功能的示例性逻辑实施方式的示图。
图11示出了依据本发明的一个实施例的互连的示图。
图12示出了依据本发明的一个实施例的图示图11的发送器模型互连结构运行的方式的表格。
图13示出了依据本发明的一个实施例的实施对针对共享总线互连结构的请求进行处置的方式的功能的示例性逻辑实施方式的示图。
图14示出了依据本发明的一个实施例的示例性微处理器流水线的示图。
具体实施方式
虽然已经结合一个实施例对本发明进行了描述，但是本发明并非意在被局限于这里所给出的具体形式。与之相反，由于能够被合理包括在如所附权利要求所限定的本发明的范围之内，所以其意在覆盖这样的替换、修改和等同形式。
在以下详细描述中，已经给出了诸如具体方法顺序、结构、单元和连接之类的众多具体细节。然而，所要理解的是，这些和其它具体细节无需被用来实践本发明的实施例。在其它情况下，已经省略了公知的结构、单元或连接，或者没有对其进行特别详细的描述，以避免不必要地对该描述造成混淆。
说明书中对“一个实施例”或“实施例”的引用意在表明结合该实施例所描述的特定特征、结构或特性包括在本发明的至少一个实施例中。在说明书中各处出现的短语“在一个实施例中”并非必然全部都指代相同的实施例，也并非是与其它实施例互相排斥的单独或可替换的实施例。此外，描述了可以由一些实施例而并非由其它实施例所表现的各种特征。类似地，描述了可能是针对一些实施例而非其它实施例的要求的各种要求。
随后的详细描述的一些部分以过程、步骤、逻辑框、处理以及对计算机存储器内的数据比特的运算的其它符号表示的形式进行呈现。这些描述和表示是数据处理领域的技术人员用来最为有效地向本领域的其它技术人员传递其工作实质的手段。过程、计算机执行的步骤、逻辑框、处理等在这里且一般地被理解为是导致所期望结果的步骤或指令的自相一致的序列。步骤是需要对物理量进行物理操控的那些步骤。通常，虽然并非必然如此，这些量采用计算机可读存储介质的电或磁信号的形式并且能够在计算机系统中存储、传输、组合、比较以及以其它方式操控。已经证明，主要出于一般使用的原因，将这些信号称为比特、数值、单元、符号、字符、项、数字等有时是方便的。
然而，应当记住的是，所有这些和类似术语是与适当的物理量相关联并且仅是应用于这些量的便利标记。除非从以下讨论中明显地另外特别指出，否则要意识到的是，贯穿本发明，利用诸如“处理”或“访问”或“写入”或“存储”或“复制”等术语进行的讨论指代计算机系统或类似电子计算设备的动作和处理，其对计算机系统的寄存器和存储器以及其它计算机可读介质内被表示为物理(电子)量的数据进行操控并将其变换为被类似表示为计算机系统的存储器或寄存器或者其它这样的信息存储、传输或显示设备内的物理量的其它数据。
本发明的实施例利用前端调度器、多个分段寄存器文件或者单个寄存器文件以及存储器子系统来实现用于多核处理器的多个核心的分片地址空间。在一个实施例中，分片(fragmentation)通过允许另外的虚拟核心(例如，软核心)协同执行包括一个或多个线程的指令序列而使得能够对多处理器的性能进行缩放。分片层级同样跨每个高速缓存层级(例如，L1高速缓存、L2高速缓存)。分片层级使用地址比特将地址空间划分为片段，其中地址比特被使用以使得片段通过处于高速缓存行界限以上和页面界限以下的比特来识别。每个片段被配置为利用多端口组结构进行存储。以下在图1A和图1B中对本发明的实施例进一步进行描述。
图1A示出了依据本发明的一个实施例的处理器的概览示图。如图1A中所描述的，处理器包括全局前端取回和调度器10以及多个可划分引擎11-14。
图1A示出了全局前端生成代码块和继承向量以支持代码序列在其相应引擎上执行的方式的概览。根据特定的虚拟核心执行模式，代码序列20-23中的每个代码序列可以属于相同的逻辑核心/线程或者不同的逻辑核心/线程。全局前端取回和调度器将对代码序列20-23进行处理以生成代码块和继承向量。如所示出的，这些代码块和继承向量被分配给特定的可划分引擎。
引擎依据所选择的模式实施虚拟核心。引擎包括分段、片段以及多个执行单元。引擎内的资源可以被用来实施具有多种模式的虚拟核心。如由虚拟核心模式所提供的，能够实施一个软核心或许多软核心以支持一个逻辑核心/线程。在图1A的实施例中，根据所选择的模式，虚拟核心可以支持一个逻辑核心/线程或者四个逻辑核心/线程。在虚拟核心支持四个逻辑核心/线程的实施例中，每个虚拟核心的资源跨每个可划分引擎分布。在虚拟核心支持一个逻辑核心/线程的实施例中，所有引擎的资源专用于该核心/线程。对引擎进行划分，以使得每个引擎提供包括每个虚拟核心的资源的子集。换句话说，虚拟核心将包括引擎11-14中每个引擎的资源的子集。引擎11-14中每个引擎的资源之间的通信由全局互连结构30提供，以便促成该处理。可替换地，引擎11-14能够被用来实施物理模式，其中引擎11-14的资源专用于支持专用核心/线程的执行。以这种方式，由引擎实施的软核心包括具有跨每个引擎分布的资源的虚拟核心。在以下附图中进一步对虚拟核心的执行模式进行描述。
应当注意的是，在常规核心实施方式中，一个核心/引擎内的资源仅被分配给一个逻辑线程/核心。与之相比，在本发明的实施例中，任意引擎/核心的资源能够连同其它引擎/核心划分一起被划分，以例示出被分配给一个逻辑线程/核心的虚拟核心。本发明的实施例还能够实施其中那些相同的引擎能够被划分以支持许多专用核心/线程或者许多动态分配的核心/线程的多种虚拟执行模式，以及其中所有引擎的所有资源都支持单个核心/线程的执行的配置。以下进一步对一些代表性实施例进行描述。在当前发明的其它实施例中，当前发明的技术能够直接被应用于常规的多核实施方式，以使得能够对多核共享的资源和互连进行有效的竞争、预约和分配。类似地，当前发明能够在单核或计算引擎内被应用，以使得能够对该核心内任意的共享资源或互连(即，端口、总线、执行单元、高速缓存、结构)进行有效的竞争、预约和分配。
例如，图1A、图1B和图5中所示的实施例能够被典型的多核设计所替代，该设计没有全局前端或继承向量，但是具有例示对诸如高速缓存、共享互连(例如，网或网格)或共享多向总线之类的资源进行访问的多个核心或多个线程的引擎。在这样的实施例中，当前发明仍然能够被直接应用，以允许有效的资源和互连的竞争、预约和分配。类似地，当前发明的实施例能够被应用于每个核心或引擎，以便竞争、预约和分配资源或互连。
图1B示出了依据本发明的一个实施例的可划分引擎及其组件的概览视图，包括用于多核处理器的分段调度器和寄存器文件、全局互连以及分片存储器子系统。如图1中所描绘的，示出了四个片段101-104。分片层级同样跨每个高速缓存层级(例如，L1高速缓存、L2高速缓存和负载存储缓冲器)。数据能够通过存储器全局互连110a在每个L1高速缓存、每个L2高速缓存以及每个负载存储缓冲器之间进行交换。
存储器全局互连包括路由矩阵，其允许多个核心(例如，地址计算和执行单元121-124)访问可以被存储在分片高速缓存层级(例如，L1高速缓存、负载存储缓冲器和L2高速缓存)中的任意点的数据。图1还描绘了每个片段101-104由此能够通过存储器全局互连110a被地址计算和执行单元121-124访问的方式。
执行全局互连110b类似地包括路由矩阵，其允许多个核心(例如，地址计算和执行单元121-124)访问可以被存储在任意分段寄存器文件的数据。因此，核心通过存储器全局互连110a或执行全局互连110b对存储在任意片段中的数据以及存储在任意分段中的数据进行访问。
图1B进一步示出了全局前端取回和调度器150，其具有整个机器的视野并且对寄存器文件分段和分片存储器子系统的利用进行管理。地址生成包括片段定义的基础。全局前端取回和调度器通过向每个分段的划分调度器分配指令序列而运行。公共划分调度器随后分派那些指令序列以用于在地址计算和执行单元121-124上执行。
此外，应当注意的是，图1A中所示的可划分引擎能够以层级方式进行嵌套。在这样的实施例中，第一级可划分引擎将包括局部前端取回和调度器以及与之连接的多个二级可划分引擎。
图2示出了描绘依据本发明的一个实施例的以上在图1A和图1B的讨论中所描述的互连30以及多个局部互连40-42的附加特征的概览视图。图2的结构图示了互连结构的协调(orchestrating)模型。图2示出了被连接至相对应的多个消费方的多个资源。该资源是每个可划分引擎的数据存储资源(例如，寄存器文件、负载存储缓冲器、L1高速缓存和L2高速缓存)。消费方是每个可划分引擎的执行单元和地址计算单元。图2进一步示出了多个协调器(orchestrator)21-23。
如上所述，每个引擎11-14的资源之间的通信由互连结构来提供。通过示例，在图2的实施例中，互连结构30是专用的点对点总线。在图2的实施例中，存在范围跨每个引擎的资源的六条总线。每个周期仅一个消费方/资源对能够利用六条总线之一。消费方/资源对通过图10的或-与(OR-AND)和阈值检测逻辑针对六条总线的使用互相竞争。然而，如在图9的讨论中进一步描述的，能够使用预约加法器和阈值限制或处理来实现针对共享多点总线配置的相同协调。
协调器21-23包括将资源的路由指向消费方的受控实体。例如，在一个实施例中，协调器可以是线程调度器，其对资源进行调度以便通过互连传输至准备执行的消费方。协调器(例如线程调度器)识别正确的资源，预约必要的总线，并且使得该资源传输至所选择的消费方。以这种方式，协调器监视指令的准备状态并且选择将被用来执行该指令的执行单元。该信息被用来通过使用如图9或图10所示的预约和分配逻辑竞争互连处的请求来对资源跨互连向所选择的执行单元(例如，所选择的消费方)的传输进行协调。以这种方式，消费方自身的执行单元被视为需要由协调器使用与针对互连所图示的类似的资源预约和分配方法进行竞争的资源。其中通过使用图9或图10之一的预约和分配逻辑来竞争来自所有协调器的请求而预约和分配执行单元。
互连包括路由矩阵，其允许多个资源消费方(在这种情况下为多个核心(例如，地址计算和执行单元121-124))访问可以被存储在分片高速缓存层级(例如，L1高速缓存、负载存储缓冲器和L2高速缓存)中的任意点处的资源(在这种情况下为数据)。核心能够类似地访问可以存储在任意分段寄存器文件处的数据。因此，核心通过互连结构30对存储在任意片段中的数据以及存储在任意分段中的数据进行访问。在一个实施例中，如以上在图1B的讨论中所示出并描述的，该互连结构包括两个结构，存储器互连110a和执行互连110b。
图2还示出了多个局部互连40-42。局部互连40-42包括路由矩阵，其允许来自相邻的可划分引擎的资源消费方快速访问紧邻的可划分引擎的资源。例如，一个核心能够使用局部互连40快速访问相邻的可划分引擎的资源(例如，寄存器文件、负载存储缓冲器等)。
因此，互连结构自身包括必须由每个可划分引擎的每个核心所共享的资源。互连结构30和局部互连结构40-42实施了允许来自任意可划分引擎的核心访问任意其它可划分引擎的资源的互连结构。该互连结构包括在互连结构的情况下范围跨集成电路设备的所有可划分引擎以及在局部互连结构的情况下范围介于集成电路设备的引擎之间的传输线路。
本发明的实施例实施了用于使用互连和局部互连的非集中化的访问处理。有限数量的全局总线和局部总线包括必须由协调器有效共享的资源。此外，非集中化的访问处理被协调器用来有效地共享向每个可划分引擎的资源提供读/写访问的有限数量的端口。在一个实施例中，非集中化的访问处理由预约总线(例如，局部互连总线或互连总线)以及到所期望的资源中的端口的协调器来实施。例如，协调器21需要预约互连和端口以便消费方1访问资源3，而协调器22则需要预约互连和端口以便消费方访问资源2。
图3示出了依据本发明的一个实施例的包括对竞争资源实施有效访问的资源预约机制的组件。如图3所示，示出了耦合至控制对三个资源中的每个资源的四个端口中的每个端口的访问的阈值限制器311-313的三个预约加法器301-303。每个加法器输出和值(如果未被取消)还用作每个访问的端口选择器，以使得每个成功的请求能够使用由该请求加法器的输出处的和值指示的端口号。应当注意的是，如图3的示图中所指示的，每个所描绘的加法器的和值也是未被取消的相对应请求所分配的端口号。
应当注意的是，该端口分配和预约问题能够类似于图7的总线分段分配表格进行图示，并且因此其实施逻辑也能够与图9相类似，其中每个分段在这种情况下反映寄存器文件分段而不是总线分段。利用在这种情况下的相同类比，与图7中对总线分段的图示相类似地，试图访问多个寄存器文件分段的指令仅在其能够预约其所有寄存器分段请求的情况下能够成功，并且在针对该指令的任何寄存器分段访问被取消的情况下将失败。
本发明的实施例实施了用于使用互连和局部互连的非集中化的访问处理。能够由多个非集中化的取回器、发送器、协调器或代理器针对共享的互连、资源或消费方发起请求、访问和控制。那些非集中化的请求、访问和控制根据那些共享资源的拓扑和结构而使用如本发明中所描述的方法和逻辑实施方式的变化形式在共享资源处进行竞争。通过示例，引擎及其读/写端口的资源需要被核心有效共享。此外，有限数量的全局总线和局部总线包括需要被有效共享的资源。在图3的实施例中，非集中化的访问处理通过预约加法器和阈值限制器来实施。在一个实施例中，在每个竞争资源处，预约加法器树和阈值限制器控制对该竞争资源的访问。如本文所使用的，术语竞争资源是指负载存储缓冲器、存储器/高速缓存片段、寄存器文件分段或L2高速缓存的读写端口、全局总线预约或局部总线预约。
预约加法器和阈值限制器控制对每个竞争资源的访问。如以上所描述的，为了访问资源，核心需要预约必要总线并预约必要端口。在每个周期期间，协调器试图预约执行其未决指令所必需的资源。例如，对于对图3中所示的指令I1进行调度的协调器而言，该协调器将在其所需要的资源的预约加法器中设置标志或比特。在这样的情况下，在寄存器文件1中和寄存器文件3中对比特进行设置。其它协调器将类似地在其所需要的资源的预约加法器中设置比特。例如，针对指令I2的不同协调器针对寄存器文件2设置两个比特。在协调器请求其所需要的资源时，预约加法器对请求求和直至它们达到阈值限制器。在图4的实施例中，针对每个资源存在四个端口。因此，预约加法器将接受来自预约请求的标志直至四个端口都被预约。将不接受其它标志。
协调器将不接受对执行其指令的确认，除非其执行指令所必需的所有标志都被设置。因此，协调器将在必需总线的标志被设置以及必需读写端口的标志被设置的情况下接受对执行指令的确认。如果针对任何标志接收到取消信号，则该协调器的请求的所有标志都被清除，并且对该请求进行排队直至下一个周期。
以这种方式，每个协调器以逐个周期为基础针对资源互相竞争。对被取消的请求进行排队并且在下一个周期中被给予优先级。这确保了一个特定核心不会在大量周期内被排除在资源访问之外。应当注意的是，所提出的实施方式中的资源自动分配到资源，例如，如果请求成功获得了资源(例如，其没有被加法器和阈值逻辑所取消)，则对应于该请求的加法器和值输出表示分配给该请求的资源编号，因此在不需要任何来自协调器的进一步参与的情况下完成了资源分配。该预约和分配加法器以及阈值限制器公平地以分散方式(例如，无需请求方/协调器主动参与任何集中化仲裁)平衡对竞争资源的访问。每个远程协调器向共享资源发送其请求，成功的那些请求将自动被给予资源/总线。
图4示出了依据本发明的一个实施例的互连和到存储器片段之中的端口。如图4中所描绘的，每个存储器片段被示为具有四个读写端口，其提供对负载存储缓冲器、L1高速缓存和L2高速缓存的读/写访问。负载存储缓冲器包括多个条目(entry)，并且L1高速缓存包括多条通路。
如以上所描述的，本发明的实施例实施了用于使用互连和局部互连的非集中化的访问处理。有限数量的全局总线和局部总线包括必须被核心有效共享的资源。因此，预约加法器和阈值限制器控制对每个竞争资源(在这种情况下为到每个片段之中的端口)的访问。如以上所描述的，为了访问资源，核心需要预约必需的总线并且预约必需的端口。
图5示出了依据本发明的一个实施例的互连和到分段之中的端口。如图5中所描绘的，每个分段被示为具有4个读写端口，其提供对操作数/结果缓冲器、线程化寄存器文件以及公共划分(common partition)或调度器的读/写访问。图5的实施例被示为在每个分段中包括公共划分或调度器。在该实施例中，共同划分调度器被配置为与图1B中所示的全局前端取回和调度器一起协同工作。
用于使用互连和局部互连的非集中化访问处理采用预约加法器和阈值限制器来控制对每个竞争资源(在这种情况下为到每个分段之中的端口)的访问。如以上所描述的，为了访问资源，核心需要预约必需的总线并且预约必需的端口。
图6示出了依据本发明的一个实施例的描绘分段互连601的示图。如图6所示，互连601被示为将资源1-4连接至消费方1-4。互连601还被示为包括分段1、分段2和分段3。
图6示出了取回模型互连结构的示例。在图6的实施例中，没有协调器。在该实施例中，资源由消费方在它们试图取回必需的资源以支持消费(例如，执行单元)时进行竞争。消费方向预约加法器和阈值限制器发送必要的取回请求。
该互连结构包括多个全局分段总线。局部互连结构包括多个局部连接的引擎至引擎总线。因此，为了平衡在性能和构造两方面的成本，存在有限数量的全局总线和有限数量的局部总线。在图6的实施例中，示出了四个全局分段的总线。
在一个实施例中，全局总线能够被分段成3个部分。分段允许全局总线的总长度依据全局访问的距离进行调节。例如，由消费方1对资源4的访问将跨越整个总线，并且因此不进行分段。然而，由消费方1对资源3的访问不会跨越整个总线，并且因此全局总线能够在资源3和资源4之间进行分段。
在图6的实施例中，互连601被示为具有4条总线。例如能够经由三态缓冲器来实施分段。分段导致了总线的更快且更功率有效的传输特性。在图6的实施例中，总线各自包括单向三态缓冲器(例如，缓冲器602)和双向三态缓冲器(例如，缓冲器603)。双向三态缓冲器在图6的示图中以阴影示出。该缓冲器使得互连能够被分段以改善其信号传输特性。这些分段还包括必须由资源消费方进行竞争并为其分配的资源。以下在图7的示图中图示了该处理。
图7示出了依据本发明的一个实施例的图示对针对互连601的分段的请求进行竞争和分配的方式的表格。图7的表格的左侧示出了当请求在周期内被接收时它们如何进行排序。在这种情况下，示出了八个请求。当来自资源消费方的请求想要预约分段时，该消费方在所请求分段的预约表格中置1。例如，针对请求1，消费方1想要预约分段1和分段2以便访问资源3。因此，消费方1在分段1和分段2的请求栏中设置标志或比特，而分段3的栏则保持为零。以这种方式，在栏内添加请求。对请求进行分配，直至它们超过了全局总线的数量(在该情况下为4)。当请求超过全局总线的数量时，它们被取消。这由因为超过了限制而被取消的请求编号6和请求编号7所示出。
图8示出了依据本发明的一个实施例的图示对针对点对点总线的请求进行处置的方式的表格。与图7的表格相反，图8的表格示出了仅一个消费方以及仅一个资源如何能够使用点对点总线(例如，图2中图示的互连)。请求来自想要通过点对点总线对资源进行路由的多个协调器。在这种情况下，点对点总线示出了可能的消费方资源对的数量(例如，从左至右的六个栏)以及从上到下的请求1-8的数量。由于在任何给定时间仅有一个资源消费方对能够使用总线，所以该栏在所有请求由于超过限制而被取消之前仅能够具有一个请求标志。因此，在每一栏中，第一请求被许可，而所有后续请求由于超过限制而被取消。由于存在六条全局点对点总线，所以存在能够在每个周期中容纳六个不同请求的六个栏。
图9示出了依据本发明的一个实施例的实施图7的表格的功能的示例性逻辑实施方式的示图。如以上所描述的，图7的表格图示了依据本发明的一个实施例的对针对互连601的分段的请求进行竞争和分配的方式。特别地，图9示出了用于分配与来自图7的表格的总线分段2相关联的栏的逻辑。
图9的实施例示出了多个并行加法器901-905。如果超出限制，则两个请求都被取消。如以上所描述的，存在能够被用来实施分段2的4条总线。前四个请求能够被处理并获得许可，因为即使它们全部通过使用逻辑1标记请求而被加以标志，它们也不会超出限制。其余请求则需要检查它们是否会超出限制。这是由并行加法器901-905来完成的。前三行之后的每个加法器将其自身与所有之前的行相加并且相对限制进行检查。如果加法器超出了限制，则如所示出的，请求被取消。加法器和值输出还确定向每个请求分配哪个特定总线分段。在图9的实施例中，这是通过如所示出的总线分段编号来完成的。
图10示出了依据本发明的一个实施例的实施对针对点对点总线的请求进行处置的方式的功能的示例性逻辑实施方式的示图。图8的表格示出了仅一个消费方以及仅一个资源如何能够使用点对点总线。具体地，图10示出了用于分配与来自图8的表格的总线栏2-4相关联的栏的逻辑。
如所示出的，图10的实施例示出了耦合至与(AND)门的多个多输入或(OR)门。如以上所描述的，一个消费方以及仅一个资源能够使用点对点总线。由于在任意给定时间仅有一个资源/消费方对能够使用总线，所以该栏在所有后续请求因为超过限制而被取消之前仅能够具有一个请求标志。因此，在每个栏中，第一请求获得许可，而所有后续请求由于超过限制而被取消。在图10的实施例中，该栏的每行通过或(OR)运算与该栏的所有之前的行进行逻辑组合并且随后通过与(AND)运算与其自身进行逻辑组合。因此，如所示出的，如果任何之前的行预约了该栏，则所有后续请求被取消。
图11示出了依据本发明的一个实施例的互连1101的示图。互连1101包括由每个发送器和每个接收器所共享的五个共享互连结构。
图11的实施例示出了发送模型互连结构的示例。例如，发送器包括引擎的执行单元。接收器包括引擎的存储器片段和寄存器分段。在该模型中，发送器向预约加法器和阈值限制器发出必要的请求以预约用于实施其传输的资源。这些资源包括到接收器中的端口以及互连1101的多个共享总线。
图12示出了依据本发明的一个实施例的图示图11的发送器模型互连结构运行的方式的表格。该表格示出了接收自所有发送器的请求。该表格的右侧示出了互连分配。由于互连1101包括五个共享总线，所以前五个请求获得了许可，而任何另外的请求由于超过限制而被取消。因此，请求1、请求3、请求4、请求5和请求6获得了许可。然而，请求7由于已经超过了限制而被取消。
图13示出了依据本发明的一个实施例的实施对针对共享总线互连结构的请求进行处置的方式的功能的示例性逻辑实施方式的示图。
图13示出了如何由加法器901-905处置互连总线的分配。该逻辑实施图12的表格。当请求被接收时，设置相对应的标志。加法器将其各自的标志与所有之前的标志相加。标志将连同其总线编号一起被加法器许可，只要它们并未超过限制(该限制在这种情况下为5)。如以上所描述的，超过限制的任何请求都被取消。
应当注意的是，互连的发送器模型和取回模型能够使用公共互连结构和公共竞争机制而同时得到支持。这由类似于图9的示图的图13的示图所示出。
应当注意的是，当前发明中不同通信模型(发送器、取回、协调器等)和不同互连拓扑(点对点总线、多总线和分段总线等)的当前表现形式不应当被解释为可应用于当前发明的仅有的通信模式或仅有的互连拓扑。与之相反，本领域技术人员能够轻易地将当前发明的不同竞争、预约和分配技术与任意通信模式或总线拓扑进行混合和匹配。
应当进一步注意的是，当前发明的所描述的实施例与资源一起呈现互连。这应当被理解为意在示出用于实施当前发明的较为宽泛的可能性集合的一般化说明，但是应当注意的是，如当前发明中所使用的互连的含义并不局限于不同核心或计算引擎之间或者寄存器文件或存储器片段之间的数据互连，而是还指代承载针对资源的请求的控制互连以及承载来自结构(即，寄存器文件端口、存储器端口、阵列解码器总线等)的数据的物理互连。该较为宽泛的含义例如在图3中进行了图示，其将互连仅示为来自每个寄存器文件的端口。
图14示出了依据本发明的一个实施例的示例性微处理器流水线1400的示图。微处理器流水线1400包括实施用于识别和取回包括如以上所描述的执行的指令的处理的功能的取回模块1401。在图14的实施例中，该取回模块后跟有解码模块1402、分配模块1403、分派模块1404、执行模块1405和引退模块1406。应当注意的是，微处理器流水线1400仅是实施以上所描述的本发明实施例的功能的流水线的一个示例。本领域技术人员将会认识到，能够实施包括以上所描述的解码模块的功能的其它微处理器流水线。
出于解释的目的，以上描述参考了并非意在作为穷举或者对当前发明进行限制的具体实施例。可能有许多与以上教导相符的修改和变化。选择和描述实施例，以便对本发明的原理及其实际应用进行最佳解释，从而使得本领域其他技术人员能够利用可以适用于其特定用途的各种修改形式对本发明及其各个实施例最佳地加以利用。

Claims (17)

1.一种用于在处理器中分配资源给消费方的方法，该方法包括：
由处理器的调度器接收对于一个或多个资源的多个请求，其中所述多个请求中的每一个是从一组一个或多个消费方中的一个消费方处接收的，并且所述一个或多个资源中的每个资源存储用于一个或多个代码序列的数据；
使用一组逻辑结构确定所述多个请求中的针对所述一个或多个资源中的一个资源的请求的数量；
当所确定的针对所述资源的请求的数量低于预定限值时，通过互连结构，基于来自于所述一组一个或多个消费方中的所述消费方的所述多个请求中的针对所述资源的请求来分配所述资源给所述消费方，其中所述互连结构具有在每个时钟周期内能访问的有限数量的总线，并且其中所述互连结构包括多个全局分段总线，其中所述互连结构包括用于连接所述一组一个或多个消费方至所述一个或多个资源的路由矩阵，
其中分配所述资源包括响应于所述多个请求使用一个或多个并行加法器竞争所述多个全局分段总线中的总线来分配所述资源，其中所述一个或多个并行加法器基于由所述一个或多个并行加法器产生的和将全局分段总线分配给所述多个全局分段总线中的请求，
其中所述多个全局分段总线中的每个分段总线与标识符相关联，并且由所述一个或多个并行加法器产生的所述和是当前请求和所有在先请求的和且与所述多个全局分段总线中的、被分配给所述请求的总线的标识符相对应。
2.如权利要求1所述的方法，其特征在于，还包括：
当所确定的针对所述资源的请求处于所述限值时，通过所述互连结构来取消所述多个请求中的针对所述资源的请求。
3.如权利要求1所述的方法，其特征在于，所述一组逻辑结构包括一组加法器，其中所述一组加法器中的每个加法器对应于所述一个或多个资源中的一个资源。
4.如权利要求1所述的方法，其特征在于，所述一组逻辑结构包括OR和AND逻辑门对，其中每个OR和AND逻辑门对对应于所述一个或多个资源中的一个资源。
5.如权利要求1所述的方法，其特征在于，所述消费方是执行单元和地址计算单元中的一个。
6.如权利要求1所述的方法，其特征在于，所述一个或多个资源包括存储器片段、寄存器组片段、到存储器片段中的读/写端口、以及到寄存器组片段中的读/写端口中的一项或多项。
7.如权利要求1所述的方法，其特征在于，所述一个或多个资源之中的两个或多个资源构成所述处理器的虚拟核。
8.如权利要求1所述的方法，其特征在于，所述资源被所述消费方使用以用于执行所述一个或多个代码序列。
9.一种微处理器，所述微处理器包括：
调度器，用于接收对于一个或多个资源的多个请求，其中所述多个请求中的每一个是从一组一个或多个消费方中的一个消费方处接收的，并且所述一个或多个资源中的每个资源存储用于一个或多个代码序列的数据；
一组逻辑结构，用于确定所述多个请求中的针对所述一个或多个资源中的一个资源的请求的数量；
互连结构，用于当所确定的针对所述资源的请求的数量低于预定限值时，基于来自于所述一组一个或多个消费方中的所述消费方的所述多个请求中的针对所述资源的请求来分配所述资源给所述消费方，其中所述互连结构具有在每个时钟周期内能访问的有限数量的总线，并且其中所述互连结构包括多个全局分段总线，其中所述互连结构包括用于连接所述一组一个或多个消费方至所述一个或多个资源的路由矩阵，
其中所述资源的分配响应于所述多个请求使用一个或多个并行加法器竞争所述多个全局分段总线中的总线，其中所述一个或多个并行加法器基于由所述一个或多个并行加法器产生的和将全局分段总线分配给所述多个全局分段总线中的请求，
其中所述多个全局分段总线中的每个分段总线与标识符相关联，并且由所述一个或多个并行加法器产生的所述和是当前请求和所有在先请求的和且与所述多个全局分段总线中的、被分配给所述请求的总线的标识符相对应。
10.如权利要求9所述的微处理器，其特征在于，所述互连结构用于当所确定的针对所述资源的请求处于所述限值时，取消所述多个请求中的针对所述资源的请求。
11.如权利要求9所述的微处理器，其特征在于，所述一组逻辑结构包括一组加法器，其中所述一组加法器中的每个加法器对应于所述一个或多个资源中的一个资源。
12.如权利要求9所述的微处理器，其特征在于，所述一组逻辑结构包括OR和AND逻辑门对，其中每个OR和AND逻辑门对对应于所述一个或多个资源之中的一个资源。
13.如权利要求9所述的微处理器，其特征在于，所述消费方是执行单元和地址计算单元中的一个。
14.如权利要求9所述的微处理器，其特征在于，所述一个或多个资源包括存储器片段、寄存器组片段、到存储器片段中的读/写端口、以及到寄存器组片段中的读/写端口中的一项或多项。
15.如权利要求9所述的微处理器，其特征在于，所述一个或多个资源之中的两个或多个资源构成所述处理器的虚拟核。
16.如权利要求9所述的微处理器，其特征在于，所述资源被所述消费方使用以用于执行所述一个或多个代码序列。
17.一种计算机可读存储介质，其具有代码，所述代码当被执行时，使机器执行如权利要求1－8中任一项所述的方法。
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