TWI603198B - 以複數個引擎作資源與互連結構的分散式分配以支援指令序列的執行 - Google Patents

以複數個引擎作資源與互連結構的分散式分配以支援指令序列的執行 Download PDF

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TWI603198B
TWI603198B TW101117854A TW101117854A TWI603198B TW I603198 B TWI603198 B TW I603198B TW 101117854 A TW101117854 A TW 101117854A TW 101117854 A TW101117854 A TW 101117854A TW I603198 B TWI603198 B TW I603198B
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摩翰麥德 艾伯戴爾拉
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英特爾股份有限公司
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Description

以複數個引擎作資源與互連結構的分散式分配以支援指令序列的執行
本申請案係主張共同審查中且共同讓與之美國專利臨時申請案案號61/488,662的優先權，其專利名稱為「以複數個引擎作資源與互連結構的分散式分配以支援指令序列的執行(DECENTRALIZED ALLOCATION OF RESOURCES AND INTERCONNECT STRUCTURES TO SUPPORT THE EXECUTION OF INSTRUCTION SEQUENCES BY A PLURALITY OF ENGINES)」，由Mohammad A.Abdallah於2011年5月20日所申請，其整體內容係併入本文。
【相關美國專利申請案】
本申請案係關於共同審查中且共同讓與之美國專利公開號2010/0161948，其專利名稱為「用以處理在支援各種上下文切換模式及虛擬化方案之多線程架構中之複雜指令格式的裝置及方法(APPARATUS AND METHOD FOR PROCESSING COMPLEX INSTRUCTION FORMATS IN A MULTITHREADED ARCHITECTURE SUPPORTING VARIOUS CONTEXT SWITCH MODES AND VIRTUALIZATION SCHEMES)」，由Mohammad A.Abdallah於2007年11月14日所申請，其整體內容係併入本文。
本申請案係關於共同審查中且共同讓與之美國專利公開號2009/0113170其專利名稱為「用以處理指定相依操作中之平行之指令矩陣的裝置及方法(APPARATUS AND METHOD FOR PROCESSING AN INSTRUCTION MATRIX SPECIFYING PARALLEL IN DEPENDENT OPERATIONS)」，由Mohammad A.Abdallah於2007年4月 12日所申請，其整體內容係併入本文。
本發明一般係關於數位電腦系統，特別是關於用以選擇包含一指令序列之指令的系統及方法。
需要處理器來處理相關或完全無關的多樣任務。此類處理器的內部狀態通常由暫存器組成，其可保持在程式執行的每一特定瞬間之不同數值。在程式執行的每一瞬間，內部狀態影像係稱作處理器的架構狀態。
當編碼執行係切換以執行另一功能(例如另一線程、程序或程式)，則需儲存機器/處理器的狀態，使得新功能可利用內部暫存器來建立其新狀態。一旦新功能終止，則可拋棄其狀態，且先前上下文的狀態將恢復並重新開始執行。此一切換程序係稱作上下文切換，且通常包含數十或數百循環，特別是具有使用大量暫存器(如64、128、256)及/或無序執行的現代架構。
在線程感知硬體架構中，標準情況為硬體針對有限數量的硬體支援線程支援多個上下文狀態。在此情況中，硬體針對每一支援線程複製所有架構狀態元件。這消除了當執行一新的線程時上下文切換的需要。然而，這仍具有多個缺點，即針對硬體中所支援之每一額外線程而複製所有架構狀態元件(即暫存器)之面積、功率、及複雜度。此外，若軟體線 程的數量超過所明確支援之硬體線程的數量，則仍必須執行上下文切換。
這已成為普遍的，如同需要大量線程之精細粒度基礎(fine granularity basis)上所需之平行化。硬體線程感知架構與複製的上下文狀態硬體儲存無助於非線程軟體編碼，且僅降低線程化軟體之上下文切換的數量。然而，那些線程通常係針對粗粒平行化(coarse grain parallelism)而建構，且導致沉重的軟體花費以初始化及同步化，捨棄了細粒平行化(fine grain parallelism)，例如功能呼叫及迴圈平行執行，而無有效的線程初始化/自動產生。這類所描述的花費係伴隨這類編碼之自動平行化的困難，其針對非明確/簡易平行化/線程軟體編碼使用最新式的編譯器或使用者平行化技術。
在一具體實施例中，本發明係實施為一種用於在一積體電路(例如，微處理器等等)中之分散式資源分配的方法。方法包括從複數個可劃分引擎之複數個資源用戶接收複數個請求以存取複數個資源，其中資源係遍及複數個引擎且經由一通用互連結構存取。在每一資源，加入用以對該每一資源之存取的一些請求。在該每一資源，比較該一些請求與一臨界限制器。在該每一資源，刪除超過臨界限制器之所接收的一後續請求。接著，執行在一目前時脈循環內未被刪除的請求。
前述為發明內容，因此必然包含簡化、概括且省略細節。因此，熟此技藝者將了解，發明內容僅為說明性而無意 圖做任何方式的限制。本發明的其他態樣、發明特徵及優點係僅由申請專利範圍所定義，且在以下所提出之非限制性詳細說明中將變得明顯。
雖然本發明已相關於具體實施例而描述，本發明並不意欲限制於在本文中所提出之特定形式。相反地，本發明係意圖涵蓋可合理地包括於由後附申請專利範圍所定義之本發明範疇內之替代、修改及等效物。
在以下的詳細描述中，提出了許多具體的細節，像是特定的方法順序、結構、元件及連接。然而，應了解到，可不需利用這些及其他具體細節來實行本發明的具體實施例。在其他情況下，省略或沒有特別地詳細描述習知結構、元件、或連接，以避免不必要地模糊了說明內容。
說明書中所提到的「一個具體實施例(one embodiment)」或「一具體實施例(an embodiment)」係意指，關聯於一具體實施例而描述的特定特徵、結構或特性係包括於本發明之至少一個具體實施例中的一具體實施例。在本說明書中許多地方所出現的「在一個具體實施例中」一詞並不需全指相同的具體實施例，也不需是與其他具體實施例互相排斥的單獨或另外的具體實施例。此外，所描述的許多特徵可能會在某些具體實施例中呈現而沒有在其他具體實施例中呈現。類似地，所描述的許多需求可能為某些具體實施例的需求，但不為其他具體實施例的需求。
詳細說明的某些部分將於下文中以電腦記憶體內之資料位元上操作的程序、步驟、邏輯塊、處理、及其他符號表示。這些描述及表示為熟習資料處理技藝者所使用的手段，以最有效地將其工作的實質內容傳達給其他熟此技藝者。程序、電腦執行步驟、邏輯塊、處理等等於此處且一般而言係設想為導致所需結果之自相一致順序的步驟或指令。這些步驟為需要實體量的實體操作。通常情況下，但非必須，這些量的形式為電腦可讀儲存媒體的電性或磁性訊號，且能夠被儲存、轉移、結合、比較、或操作於電腦系統中。已證實有時(主要為了平常使用)將此等訊號稱作位元、值、元件、符號、字元、術語、數字或其類似者係便利的。
然而，應注意，所有這些或類似用語與適當實體量有關，且僅為應用到這些量的便利符號。於下討論中除非有特別指明，不然應知本發明中使用例如「處理(processing)」、「存取(accessing)」、「寫入(writing)」、「儲存(storing)」、「複製(replicating)」、或類似者等用語之討論，係指電腦系統或類似電子計算裝置的動作及程序，其將電腦系統暫存器及記憶體及其他電腦可讀媒體內表示為實體(電子)量的資料操控且轉換成在電腦系統記憶體或暫存器或其他此類資訊儲存、傳輸、或顯示裝置內類似地表示為實體量的其他資料。
本發明具體實施例利用一前端排程器、複數個區段暫存器檔案或單一暫存器檔案、一記憶體次系統以實施用於多核心處理器之多核心的片段位址空間。在一具體實施例中，分段藉由允許額外的虛擬核心(如軟核心)以協力地執行包含一或多個線程的指令序列而致能微處理器效能的尺度化(scaling)。分段階層在每一快取階層(如L1快取、L2快取) 為相同。分段快取使用位址位元將位址空間劃分為片段，其中位址位元係使用使得片段係由在快取線邊界之上以及頁邊界之下的位元所識別。每一片段係組態以利用一多埠庫結構供儲存。本發明具體實施例將在以下圖1A及1B中作進一步地描述。
圖1A顯示根據本發明一具體實施例之處理器的概要圖。如圖1A所繪示，處理器包括一通用前端抓取及排程器10及複數個可劃分引擎11至14。
圖1A顯示通用前端產生編碼區塊及遺傳向量以支援編碼序列於其個別可劃分引擎上之執行的方式的概要。每一編碼序列20至23可屬於相同邏輯核心/線程或屬於不同的邏輯核心/線程，其取決於特定的虛擬核心執行模式。通用前端抓取及排程器將處理編碼序列20至23以產生編碼區塊及遺傳向量。這些編碼區塊及遺傳向量係分配至特定的可劃分引擎11至14，如圖所示。
引擎根據一所選模式而執行虛擬核心。一引擎包括一區段、一片段、及一些執行單元。在引擎內的資源可用以執行具有多重模式的虛擬核心。當配置為虛擬核心模式，可實施一軟核心或許多軟核心以支援一邏輯核心/線程。在圖1A的具體實施例中，根據所選模式，虛擬核心可支援一邏輯核心/線程或四個邏輯核心/線程。在虛擬核心支援四個邏輯核心/線程的具體實施例中，每一虛擬核心的資源係散佈於每一可劃分引擎。在虛擬核心支援一邏輯核心/線程的具體實施例中，所有引擎的資源係專屬於該核心/線程。引擎係劃分使得每一引擎提供包含每一虛擬核心之資源的一子集。換言 之，虛擬核心將包含引擎11至14之每一者之資源的一子集。引擎11至14之每一者之資源之間的通訊係由一通用互連結構30所提供，以幫助此程序。或者，引擎11至14可用以實施引擎11至14之資源係專用以支援一專屬核心/線程之執行的一實體模式。在此方式中，由引擎所實施的軟核心包含具有散佈至每一引擎之資源的虛擬核心。虛擬核心執行模式將在以下圖式中進行進一步的描述。
應注意，在傳統的核心實施中，在一核心/引擎內的資源係單獨地分配至一邏輯線程/核心。相反地，在本發明具體實施例中，可劃分任何引擎/核心的資源(其與其他引擎/核心劃分協力)以實例化分配至一邏輯線程/核心的一虛擬核心。本發明具體實施例也可實施那些相同引擎可被劃分以支援許多專屬核心/線程或許多動態分配的核心/線程之多個虛擬執行模式、以及所有引擎的所有資源支援單一核心/線程之執行的組態。以下將進一步描述某些代表性具體實施例。在本發明的其他具體實施例中，本發明的技術可直接地應用至傳統的多核心實施，以致能多核心共享資源及互連的有效率競爭、保留及分配。類似地，本發明應用於單一核心或計算引擎內，以致能在核心內之任何共享資源或互連(即埠、匯流排、執行單元、快取、結構)的有效率競爭、保留及分配。
舉例來說，圖1A、圖1B、及圖5所示的具體實施例可由一典型的多核心設計所取代，其不具有通用前端或遺傳向量，而是具有實例化多核心或多線程(其具有對資源(如快取、共享互連(如網孔或網格)或共享多方向匯流排)的存取)的引擎。在這類具體實施例中，本發明仍可直接地應用以允 許有效率的資源及互連競爭、保留、及分配。類似地，本發明具體實施例可應用至每一核心或引擎，以競爭、保留、及分配資源或互連。
圖1B顯示根據本發明一具體實施例之可劃分引擎及其構件的概要圖，其包括針對一多核心處理器的區段排程器及暫存器檔案、通用互連、及片段記憶體次系統。如圖1B所繪示，顯示了四個片段101至104。分段階層在每一快取階層(如L1快取、L2快取、及載入儲存緩衝器)為相同。資料可經由記憶體通用互連110a在每一L1快取、每一L2快取、及每一載入儲存緩衝器之間交換。
記憶體通用互連包含一路由矩陣，其允許複數個核心(如位址計算及執行單元121-124)存取資料，資料可儲存於片段快取階層(如L1快取、載入儲存緩衝器及L2快取)中的任一點。圖1B也繪示每一片段101至104可由位址計算及執行單元121至124經由記憶體通用互連110a而存取的方式。
執行通用互連110b類似地包含一路由矩陣，允許複數個核心(如位址計算及執行單元121至124)存取可能儲存於任何區段暫存器檔案的資料。因此，核心具有經由記憶體通用互連110a或執行通用互連110b之對儲存於任何片段中之資料及對儲存於任何區段中之資料的存取。
圖1B更顯示一通用前端抓取及排程器150，其具有對整體機器的觀察且其管理暫存器檔案區段及分段記憶體次系統的使用。位址產生包含針對片段定義的基礎。通用前端 抓取及排程器係藉由分配指令序列至每一區段的劃分排程器而作用。共同劃分排程器接著配送在位址計算及執行單元121至124上用以執行的那些指令序列。
此外，應注意，圖1A所示的可劃分引擎可以階層方式嵌套(nested)。在此一具體實施例中，第一等級可劃分引擎係包括一本地前端抓取及排程器及與其連接之多個次級可劃分引擎。
圖2顯示根據本發明一具體實施例之概要圖，其繪示在圖1A及1B的討論中所描述之互連30的額外特徵及複數個本地互連40至42。圖2結構描述互連結構的一編排模式。圖2顯示連接至對應之複數個用戶的複數個資源。資源為可劃分引擎之每一者的資料儲存資源(如暫存器檔案、載入儲存緩衝器、L1快取及L2快取)。用戶為可劃分引擎之每一者的執行單元及位址計算單元。圖2更顯示複數個編排器21-23。
如上述，引擎11至14之每一者的資源之間的通訊係由一互連結構所提供。舉例來說，在圖2的具體實施例中，互連結構30為一專屬點對點匯流排。在圖2的具體實施例中，有六個跨越每一引擎之資源的匯流排。只有一個用戶/資源對可在每一循環利用六個匯流排的其中之一。用戶/資源對係經由圖10的OR-AND及臨界偵測邏輯而彼此競爭以使用六個匯流排。然而，可使用保留加法器及臨界限制或程序而達成針對一共享的多點匯流排組態之相同編排，如將進一步描述於圖9的討論中。
編排器21至23包含指示資源的路由至用戶的控制實體。舉例來說，在一具體實施例中，編排器可為一線程排程器，其安排預備好供執行的資源經由互連轉移至用戶。編排器(如線程排程器)識別正確的資源、保留必要的匯流排、並造成該資源轉移至一所選的用戶。在此方式中，編排器監視指令的準備就緒並選擇將用以執行指令的執行單元。此資訊係用以編排橫越互連之資源轉移至所選的執行單元(如所選的用戶)，其藉由使用圖9或圖10所描述之保留及分配邏輯而競爭在互連的請求。在此方式中，用戶本身的執行單元係視作需要由編排器使用如針對互連所描述之類似資源保留及分配方法而競爭的資源。在執行單元中係藉由競爭請求而保留及分配，請求係來自使用圖9或圖10之保留及分配邏輯之任一的所有編排器。
互連包含一路由矩陣，其允許複數個資源用戶(在此情況中為複數個核心(如位址計算及執行單元121至124))存取資源(在此情況中為資料，其可儲存於片段快取階層(如L1快取、載入儲存緩衝器及L2快取)中的任一點)。核心可類似地存取可能儲存於任何區段暫存器檔案的資料。因此，核心具有經由互連結構30之對儲存於任何片段中之資料以及對儲存於任何區段中之資料的存取。在一具體實施例中，互連結構包含兩個結構：記憶體互連110a及執行互連110b,如前文中在圖1B的討論中所顯示及描述。
圖2亦顯示複數個本地互連40至42。本地互連40至42包含一路由矩陣，其允許來自鄰近可劃分引擎的資源用戶快速地存取緊鄰之可劃分引擎的資源。舉例來說，一核心可使用本地互連40以快速地存取鄰近可劃分引擎的資源(如 暫存器檔案、載入儲存緩衝器等)。
因此，互連結構本身包含必須由每一可劃分引擎之每一核心所共享的一資源。互連結構30及本地互連結構40至42係實施允許來自任何可劃分引擎之核心存取任何其他可劃分引擎之資源的一互連結構。此互連結構包含傳輸線，其在互連結構的情況中係跨越積體電路裝置的所有可劃分引擎，且在本地互連結構的情況中係跨越在積體電路裝置的引擎之間。
本發明具體實施例係執行一非集中存取程序供使用互連及本地互連。通用匯流排及本地匯流排的有限數量包含必須有效率地由編排器共享的資源。此外，非集中存取程序係由編排器使用以有效率地共享有限數量的埠，其提供對每一可劃分引擎之資源的讀取/寫入存取。在一具體實施例中，非集中存取程序係由編排器保留進入到所需資源的一匯流排(如本地互連匯流排或互連匯流排)及一埠而實施。舉例來說，編排器21需保留一互連及一埠以供用戶1存取資源3，而編排器22需保留一互連及埠以供用戶存取資源2。
圖3顯示根據本發明一具體實施例之包含執行對一競爭資源之有效率存取的一資源保留機制的構件。如圖3所示，三個保留加法器301至303係顯示為耦合至臨界限制器311至313，其控制對四個埠之每一者對三個資源之每一者的存取。每一加法器輸出總和(若無刪除的話)亦作為針對每一存取的埠選擇器，使得成功的每一請求可使用由在該請求加法器之輸出的總和所指示之埠數目。應注意，如圖3中所示，每一個所繪示之加法器的總和亦針對非刪除的對應請求 指派埠數目。
應注意，此埠分配及保留問題可類似圖7之匯流排區段分配表格而描述，因此其實施邏輯也可類似於圖9，其中在此情況中的每一區段係反映一暫存器檔案區段而非一匯流排區段。以與此情況相同的類推，試圖存取多個暫存器檔案區段的指令僅可在其可保留所有其暫存器區段請求時成功，且若刪除針對該指令之任一暫存器區段存取時將失敗，類似於圖7中匯流排區段的描述。
本發明具體實施例執行非集中存取程序供使用互連及本地互連。請求、存取及控制可由多個非集中抓取器、傳送器、編排器、或代理器針對共享互連、資源或用戶而初始化。那些非集中請求、存取及控制係競爭共享資源，其係根據那些共享資源的拓樸及結構使用本發明所述之方法及邏輯實施的變化。舉例來說，引擎及其讀取/寫入埠的資源需由核心有效率地共享。此外，通用匯流排及本地匯流排的有限數量包含需被有效率共享的資源。在圖3的具體實施例中，非集中存取程序係經由保留加法器及臨界限制器而實施。在一具體實施例中，在每一競爭資源，保留加法器樹狀結構及臨界限制器控制對該競爭資源的存取。如本文中所使用，競爭資源一詞係指載入儲存緩衝器、記憶體/快取片段、暫存器檔案區段或L2快取、通用匯流排保留、或本地匯流排保留的讀取寫入埠。
保留加法器及臨界限制器控制對每一競爭資源的存取。如上述，為存取一資源，核心需保留必要的匯流排及保留必要的埠。在每一循環期間，編排器試圖保留執行其暫停 指令所需的資源。舉例來說，針對安排圖3所示之指令I1的編排器，該編排器將設定一旗標或一位元於其所需資源的保留加法器中。在此情況中，位元係設定於暫存器檔案1及暫存器檔案3中。其他編排器將類似地設定位元於其所需資源的保留加法器中。舉例來說，針對指令I2之一不同的編排器係針對暫存器檔案2設定兩個位元。當編排器請求其所需資源，保留加法器係總和請求直到其達到臨界限制器。在圖4的具體實施例中，對每一資源有四個埠。因此，保留加法器將從保留請求接受旗標直到四個埠皆保留。沒有其他旗標將被接受。
編排器將不接收確認以執行其指令，除非其所有需執行指令的旗標皆被設定。因此，若針對必要匯流排的旗標被設定且針對必要讀取寫入埠的旗標被設定，則編排器將接收確認以執行指令。若針對任何旗標接收到一刪除信號，則刪除針對該編排器之請求的所有旗標，且請求係佇列直到下一循環。
在此方式中，每一編排器在一循環週期基礎上針對資源彼此競爭。刪除的請求係佇列且在下一循環中給定優先性。這確保一特定核心未對大量的循環鎖定資源存取。應注意，在建議實施中的資源係自動地指派資源，例如若請求成功獲得一資源(如其未由加法器及臨界邏輯所刪除)，則對應該請求的加法器總和輸出表示指派給該請求的資源數目，因此完成資源指派而不需編排器的任何進一步參與。此保留及分配加法器及臨界限制器在分散式方式中公平地平衡對競爭資源的存取(例如不需要請求器/編排器主動地參與任何集中的仲裁)。每一遠端編排器傳送其請求至共享資源，成功的那 些資源將被自動地授予資源/匯流排。
圖4顯示根據本發明一具體實施例之互連及進入至記憶體片段之埠。如圖4所繪示，每一記憶體片段係顯示為具有四個讀取寫入埠，其提供對載入儲存緩衝器、L1快取、及L2快取的讀取/寫入存取。載入儲存緩衝器包括複數個項目且L1快取包含複數個路徑。
如上述，本發明具體實施例執行非集中存取程序供使用互連及本地互連。通用匯流排及本地匯流排的有限數量包含必須由核心有效率共享的資源。因此，保留加法器及臨界限制器控制對每一競爭資源的存取，在此情況中為到每一片段的埠。如上述，為存取資源，核心需要保留必要的匯流排並保留必要的埠。
圖5顯示根據本發明一具體實施例之互連及進入至記憶體區段之埠。如圖5所示，每一區段係顯示為具有4個讀取寫入埠，其提供對運算元/結果緩衝器、線程暫存器檔案、及共同劃分或排程器的讀取/寫入存取。圖5的具體實施例係顯示為包括一共同劃分或排程器於每一區段中。在此具體實施例中，共同劃分排程器係組態以與圖1B所示之通用前端抓取及排程器協力地作用。
用以使用互連及本地互連的非集中存取程序係利用保留加法器及臨界限制器控制對每一競爭資源的存取，在此情況中為到每一區段的埠。如上述，為存取資源，核心需要保留必要的匯流排並保留必要的埠。
圖6顯示繪示根據本發明一具體實施例之區段互連601的一圖式。如圖6所示，互連601係顯示為連接資源1-4至用戶1-4。互連601亦顯示為包含區段1、2、及3。
圖6顯示抓取模式互連結構的一範例。在圖6的具體實施例中，沒有編排器。在此具體實施例中，當用戶試圖抓取必要的資源以支援消耗(如執行單元)時，資源由用戶競爭。用戶傳送必要的抓取請求至保留加法器及臨界限制器。
互連結構包含複數個通用區段匯流排。本地互連結構包含複數個本地連接的引擎至引擎匯流排。因此，為平衡在效能及製造兩者中的成本，具有有限數量的通用匯流排及有限數量的本地匯流排。在圖6的具體實施例中，顯示了四個通用區段匯流排。
在一具體實施例中，通用匯流排可分區段為3個部分。分區段允許根據通用存取的距離調整通用匯流排的整體長度。舉例來說，由用戶1對資源4的存取係橫跨整體匯流排，因此未分區段。然而，由用戶1對資源3的存取未橫跨整體匯流排，因此通用匯流排可在資源3及資源4之間分區段。
在圖6的具體實施例中，互連601係顯示為具有4個匯流排。分區段可透過例如三狀態緩衝器而實施。分區段導致匯流排的更快且更省電的傳輸特性。在圖6的具體實施例中，每一匯流排包括一方向性三狀態緩衝器(如緩衝器602)及雙向三狀態緩衝器(如緩衝器603)。在圖6中，雙向三狀態緩衝器係以陰影表示。緩衝器係致能互連被分段以改善其信號傳輸特性。這些區段也包含必須由資源用戶競爭及分配 的資源。此程序係描述於以下的圖7。
圖7顯示一表格，其描述根據本發明一具體實施例之針對互連601之區段之請求所競爭及分配的方式。圖7表格的左手側顯示當請求於循環內被接收時如何排序。在此情況中，顯示了八個請求。當來自一資源用戶的請求想要保留一區段，該用戶設定一於所請求區段的保留表格中。舉例來說，針對請求1，用戶1想要保留區段1及區段2以存取資源3。因此，用戶1設定一旗標或一位元於區段1及區段2的請求行中，而區段3的行係保持為零。在此方式中，請求係加入於行內。請求係分配直到其超過通用匯流排的數量，在此情況中為4個。當請求超過通用匯流排的數量，其將刪除。這由因為超過限制而已刪除之請求數目6及請求數目7所顯示。
圖8顯示一表格，其描述根據本發明一具體實施例之處理針對點對點匯流排之請求的方式。與圖7的表格相反，圖8的表格顯示只有一用戶及只有一資源如何使用點對點匯流排(如圖2所示的互連)。請求來自想要經由點對點匯流排路由資源的多個編排器。在此情況中，點對點匯流排顯示可能的用戶資源對之數目(如從左至右的六行)以及從頂至底之請求1-8的數目。因為只有一資源用戶對可在任何給定時間使用一匯流排，在所有旗標因超過限制而刪除前，行可僅具有一請求旗標。因此，在每一行中，允許第一請求，而所有後來的請求係因超過限制而刪除。由於有六個通用點對點匯流排，有六個行可在每一循環中容納六個不同的請求。
圖9顯示根據本發明一具體實施例之執行圖7之表格之 功能的範例邏輯實施的圖式。如上述，圖7的表格描述根據本發明具體實施例之競爭及分配針對互連601之區段之請求的方式。特別地，圖9顯示用以分配相關於來自圖7表格之匯流排區段2之行的邏輯。
圖9的具體實施例顯示複數個平行加法器901-905。若超過限制則刪除兩個請求。如上述，有4個匯流排可用以實施區段2。可處理並允許前四個請求，因為即使他們都被標誌旗標(藉由以邏輯一標示請求)，其將不會超過限制。需要檢查剩下的請求是否將超過限制。這由平行加法器901-905所完成。在前三列之後的每一加法器係加入其本身及所有先前的列，並核對限制。若加法器超過限制，則刪除請求，如所示。加法器總和輸出也決定哪一特定的匯流排區段係分配至每一請求。在圖9的具體實施例中，這是藉由匯流排區段數目，如所示。
圖10顯示根據本發明一具體實施例之處理針對點對點匯流排之請求之方式之功能的範例邏輯實施的圖式。圖8的表格顯示只有一用戶及只有一資源如何可使用點對點匯流排。特別地，圖10顯示用以分配相關於來自圖8表格之匯流排行2-4之行的邏輯。
圖10的具體實施例顯示耦合至AND閘的複數個多輸入OR閘，如所示。如前述，一用戶以及僅一資源可使用一點對點匯流排。因為只有一資源/用戶對可在任何給定時間使用一匯流排，在所有後續請求因超過限制而刪除前，行可僅具有一請求旗標。因此，在每一行中，允許第一請求，而所有後續請求因為超過限制而刪除。在圖10的具體實施例 中，行的每一列係經由OR操作而與行的所有先前列邏輯地結合，且接著經由AND操作而與其本身邏輯地結合。因此，若任何先前列保留行，則刪除所有後續請求，如所示。
圖11顯示根據本發明一具體實施例之互連1101的圖式。互連1101包含五個共享互連結構，其由每一傳送器及每一接收器所共享。
圖11的具體實施例顯示傳送模式互連結構的一範例。舉例來說，傳送器包含引擎的執行單元。接收器包含引擎的記憶體片段及暫存器區段。在此模式中，傳送器發佈必要的請求至保留加法器及臨界限制器以保留用以執行其轉移的資源。這些資源包括進入接收器的匯流排及互連1101的複數個共享匯流排。
圖12顯示一表格，其描述根據本發明一具體實施例之圖11之傳送器模式互連結構作用的方式。表格顯示從所有傳送器所接收之請求。表格的右手側顯示互連分配。由於互連1101包含五個共享匯流排，前五個請求將被允許，且任何進一步的請求因超過限制而刪除。因此，請求1、請求3、請求4、請求5及請求6係被允許。然而，請求7因已超過限制而刪除。
圖13顯示根據本發明一具體實施例之範例邏輯實施的圖式，其執行處理針對共享匯流排互連結構之請求之方式的功能。
圖13顯示互連匯流排的分配如何由加法器901-905所 處理。此邏輯實施圖12的表格。當接收請求，設定對應的旗標。加法器加入其個別旗標與所有先前的旗標。旗標將與其匯流排數目一起由加法器所允許，只要其未超過限制，在此情況中為五個。如上述，超過限制的任何請求將刪除。
應注意，互連的傳送器模式及抓取模式可使用共同互連結構及共同競爭機制而被同時地支援。這由圖13之圖式對圖9之圖式的相似性所顯示。
應注意，對本發明之不同模式的通訊(傳送器、抓取、編排器等)及不同的互連拓撲(點對點匯流排、多重匯流排、及區段匯流排等)的描述不應解釋為適用於本發明的唯一通訊模式或唯一互連拓撲。相反地，熟此技藝者可輕易地混合及匹配本發明不同的競爭、保留及分配技術與任何通訊模式或匯流排拓撲。
更應注意，所描述之本發明具體實施例係呈現沿著資源的互連。這應理解為一般化的描述，其表示顯示更廣泛的可能性以實施本發明，但應注意本發明所使用之互連的意義並不限於在不同核心或計算引擎之間的互連或是暫存器檔案或記憶體片段之間的互連，而是也指承載請求至資源的控制互連以及從結構承載資料的實體互連(亦即，暫存器檔案埠、記憶體埠、陣列解碼器匯流排等)。舉例來說，此廣泛的含意係描述於圖3，其顯示只有當埠從每一暫存器檔案出來的互連。
圖14顯示根據本發明一具體實施例之範例微處理器管線1400的圖式。微處理器管線1400包含一抓取模組1401， 其執行程序之功能以識別及擷取包含一執行之指令，如前述。在圖14的具體實施例中，抓取模組係接著一解碼模組1402、分配模組1403、配送模組1404、執行模組1405、及引退模組1406。應注意，微處理器管線1400只是管線的一範例，其執行上述之本發明具體實施例的功能。熟此技藝者將了解到其他微處理器管線可實施為包含上述解碼模組之功能。
為解釋目的，前文之描述係指特定具體實施例，其無意為詳盡或限制本發明。在符合上述教示下可能有許多修改及變化。具體實施例係選擇及描述以最佳地解釋本發明的原理及其實際應用，以致能其他熟此技藝者最佳地使用本發明及其具有可適合於特定使用之各種修改的各種具體實施例。
10‧‧‧通用前端抓取及排程器
11-14‧‧‧引擎
20-23‧‧‧編碼序列、編排器
30‧‧‧通用互連結構
40-42‧‧‧本地互連
101-104‧‧‧片段
110a‧‧‧記憶體通用互連
110b‧‧‧執行通用互連
121-124‧‧‧位址計算及執行單元
150‧‧‧通用前端抓取及排程器
301-303‧‧‧保留加法器
311-313‧‧‧臨界限制器
601‧‧‧互連
602‧‧‧緩衝器
603‧‧‧緩衝器
901-905‧‧‧加法器
1101‧‧‧互連
1400‧‧‧微處理器管線
1401‧‧‧抓取模組
1402‧‧‧解碼模組
1403‧‧‧分配模組
1404‧‧‧配送模組
1405‧‧‧執行模組
1406‧‧‧引退模組
本發明係經由範例而非經由限制的方式而描述，在所附隨圖式之各圖中，類似的元件符號係指類似的元件。
圖1A顯示通用前端產生編碼區塊及遺傳向量以支援編碼序列於其個別引擎上之執行的方式的概要；圖1B顯示根據本發明一具體實施例之引擎及其構件的概要圖，其包括針對一多核心處理器的區段排程器及暫存器檔案、互連、及片段記憶體次系統；圖2顯示根據本發明一具體實施例之概要圖，其繪示在圖1A及1B的討論中所描述之互連的額外特徵及複數個本地互連；圖3顯示根據本發明一具體實施例之包含執行對一競爭資源之有效率存取的一資源保留機制的構件； 圖4顯示根據本發明一具體實施例之互連及進入至記憶體片段之埠；圖5顯示根據本發明一具體實施例之互連及進入至記憶體區段之埠；圖6顯示繪示根據本發明一具體實施例之區段互連的一圖式；圖7顯示一表格，其描述根據本發明一具體實施例之針對互連之區段之請求所競爭及分配的方式；圖8顯示一表格，其描述根據本發明一具體實施例之處理針對點對點匯流排之請求的方式；圖9顯示根據本發明一具體實施例之執行圖7之表格之功能的範例邏輯實施的圖式；圖10顯示根據本發明一具體實施例之處理針對點對點匯流排之請求之方式之功能的範例邏輯實施的圖式；圖11顯示根據本發明一具體實施例之互連的圖式；圖12顯示一表格，其描述根據本發明一具體實施例之圖11之傳送器模式互連結構作用的方式；圖13顯示根據本發明一具體實施例之範例邏輯實施的圖式，其執行處理針對共享匯流排互連結構之請求之方式的功能；以及圖14顯示根據本發明一具體實施例之範例微處理器管線的圖式。
301-303‧‧‧保留加法器
311-313‧‧‧臨界限制器

Claims (24)

  1. 一種用於在一積體電路中之分散式資源分配的方法，包含：從複數個可劃分引擎之複數個資源用戶接收複數個請求以存取複數個資源，其中該等資源係遍及該複數個可劃分引擎且經由一通用互連結構存取，且其中複數個線程排程器可操作以針對該複數個資源進行排程以用於經由該通用互連傳輸至該複數個資源用戶；在每一資源，使用一加法器來加入用以對該每一資源之存取的一些請求，其中該些請求係使用該複數個線程排程器而產生；在該每一資源，比較該一些請求與一臨界限制器；在該每一資源，刪除超過該臨界限制器之一後續請求；以及在該每一資源，執行在一目前時脈循環內未被刪除的請求，其中對應於一請求的該加法器的一總和表示用於存取對應於該請求的一資源的一埠數目。
  2. 如請求項1所述之方法，其中該複數個資源用戶包含該可劃分引擎之每一者的執行單元。
  3. 如請求項1所述之方法，其中該複數個資源包含該可劃分引擎之每一者的記憶體片段。
  4. 如請求項1所述之方法，其中該複數個資源包含該可劃分引擎之每一者的暫存器檔案區段。
  5. 如請求項1所述之方法，其中該複數個資源包含 讀取/寫入埠至該可劃分引擎之每一者的記憶體片段及暫存器檔案區段。
  6. 如請求項1所述之方法，其中該複數個資源包含該通用互連結構的匯流排。
  7. 如請求項1所述之方法，其中若用以執行一動作之一組相關請求之其中一者刪除，則不執行一請求，其中該組相關請求包括用於一讀取/寫入埠的一請求以及用於該通用互連結構之一匯流排的一請求。
  8. 如請求項1所述之方法，其中該通用互連結構包含複數個點對點匯流排，且其中該一些請求係經由耦合至一個別邏輯及操作的複數個多輸入邏輯或操作而加入。
  9. 一種用於在一微處理器中之分散式資源分配的方法，包含：從複數個可劃分引擎之複數個資源用戶接收複數個請求以存取複數個資源，其中該等資源係遍及該複數個可劃分引擎且經由一通用互連結構存取，且其中複數個線程排程器可操作以針對該複數個資源進行排程以用於經由該通用互連傳輸至該複數個資源用戶；其中該複數個資源用戶包含該可劃分引擎之每一者的執行單元，且其中該複數個資源包含該可劃分引擎之每一者的記憶體片段及暫存器檔案區段；在每一資源，使用一加法器來加入用以對該每一資源之存取的一些請求，其中該些請求係使用該複數個線程排程器而產生； 在該每一資源，比較該一些請求與一臨界限制器；在該每一資源，刪除超過該臨界限制器之一後續請求；以及在該每一資源，執行在一目前時脈循環內未被刪除的請求，其中對應於一請求的該加法器的一總和表示用於存取對應於該請求的一資源的一埠數目。
  10. 如請求項9所述之方法，其中該複數個資源更包含讀取/寫入埠至該可劃分引擎之每一者的記憶體片段及暫存器檔案區段。
  11. 如請求項9所述之方法，其中該複數個資源個更包含該通用互連結構的匯流排。
  12. 如請求項9所述之方法，其中若用以執行一動作之一組相關請求之其中一者刪除，則不執行一請求，其中該組相關請求包括用於一讀取/寫入埠的一請求以及用於該通用互連結構之一匯流排的一請求。
  13. 如請求項9所述之方法，其中該通用互連結構包含複數個點對點匯流排，且其中該一些請求係經由耦合至一個別邏輯及操作的複數個多輸入邏輯或操作而加入。
  14. 一種微處理器，包含：複數個資源，具有用以支援多個編碼序列之執行的資料；複數個可劃分引擎，用以執行該多個編碼序列的執行；複數個資源用戶，在該複數個可劃分引擎之每一者 內；一通用互連結構，用以耦合該複數個資源用戶與該複數個資源以存取該資料且執行該多個編碼序列，其中該等資源用戶經由該通用互連結構之每一循環利用而存取該等資源，且其中該等資源用戶包含該可劃分引擎的執行單元，且其中複數個線程排程器可操作以針對該複數個資源進行排程以用於經由該通用互連傳輸至該複數個資源用戶；以及其中該複數個資源係藉由以下而分配至該複數個資源用戶：在每一資源，使用一加法器來加入用以對該每一資源之存取的一些請求，其中該些請求係使用該複數個線程排程器而產生；在該每一資源，比較該一些請求與一臨界限制器；在該每一資源，刪除超過該臨界限制器之一後續請求；以及在該每一資源，執行在一目前時脈循環內未被刪除的請求，其中對應於一請求的該加法器的一總和表示用於存取對應於該請求的一資源的一埠數目。
  15. 如請求項14所述之微處理器，其中該複數個資源用戶包含該可劃分引擎之每一者的執行單元。
  16. 如請求項14所述之微處理器，其中該複數個資源包含該可劃分引擎之每一者的記憶體片段。
  17. 如請求項14所述之微處理器，其中該複數個資 源包含該可劃分引擎之每一者的暫存器檔案區段。
  18. 如請求項14所述之微處理器，其中該複數個資源包含讀取/寫入埠至該可劃分引擎之每一者的記憶體片段及暫存器檔案區段。
  19. 如請求項14所述之微處理器，其中該複數個資源包含該通用互連結構的匯流排。
  20. 如請求項14所述之微處理器，其中若用以執行一動作之一組相關請求之其中一者刪除，則不執行一請求，其中該組相關請求包括用於一讀取/寫入埠的一請求以及用於該通用互連結構之一匯流排的一請求。
  21. 如請求項14所述之微處理器，其中該通用互連結構包含複數個點對點匯流排，且其中該一些請求係經由耦合至一個別邏輯及操作的複數個多輸入邏輯或操作而加入。
  22. 一種用於在一積體電路中之分散式資源分配的方法，包含：從複數個可劃分引擎之一或多個資源用戶接收複數個請求以在一給定循環中存取複數個資源，其中該複數個資源係遍及該複數個可劃分引擎且經由一通用互連結構存取，而該通用互連結構在每一時脈循環中具有有限數量可存取的匯流排，其中該複數個資源包含該可劃分引擎之每一者的暫存器檔案區段與記憶體片段的至少其中之一以及讀取/寫入埠至該可劃分引擎之每一者的記憶體片段及暫存器檔案區段，其中該複數個資源用戶包含該可劃分引擎 之每一者的執行單元或位址計算單元的至少其中之一，其中複數個線程排程器之每一者可操作以識別所請求的資源並競爭以使用該通用互連結構的一或多個匯流排，以針對該複數個資源進行排程以用於經由該通用互連傳輸至該複數個資源用戶，其中該複數個資源被傳輸至該複數個資源用戶係透過以下步驟：在每一資源，使用一加法器來加入用以對該每一資源之存取的一些請求，其中該些請求係使用該複數個線程排程器而產生；在該每一資源，比較該一些請求與一臨界限制器；在該每一資源，刪除超過該臨界限制器之一或多個請求，其中被刪除的請求係佇列且在下一循環中給定優先性；以及在該每一資源，執行在一目前時脈循環內未被刪除的請求，其中該加法器在一輸出的一總和表示用於存取對應於一個別請求的一資源的一埠數目。
  23. 一種用於在一微處理器中之分散式資源分配的方法，包含：從複數個可劃分引擎之一或多個資源用戶接收複數個請求以在一給定循環中存取複數個資源，其中該等資源係遍及該複數個可劃分引擎且經由一通用互連結構存取，而該通用互連結構在每一時脈循環中具有有限數量可存取的匯流排，其中該複數個資源包含該可劃分引擎之每一者的暫存器檔案區段與記憶體片段的至少其中之一，其中該複 數個資源用戶包含該可劃分引擎之每一者的執行單元或位址計算單元的至少其中之一，其中複數個線程排程器之每一者可操作以識別所請求的資源並競爭以使用該通用互連結構的一或多個匯流排，以針對該複數個資源進行排程以用於經由該通用互連傳輸至該複數個資源用戶，其中該複數個資源被傳輸至該複數個資源用戶係透過以下步驟：在每一資源，加入用以對該每一資源之存取的一些請求，其中該些請求係使用該複數個線程排程器而產生；在該每一資源，比較該一些請求與一臨界限制器；在該每一資源，刪除超過該臨界限制器之一或多個請求，其中被刪除的請求係佇列且在下一循環中給定優先性；以及在該每一資源，執行在一目前時脈循環內未被刪除的請求，其中該加法器在一輸出的一總和表示用於存取對應於一個別請求的一資源的一埠數目。
  24. 一種微處理器，包含：複數個資源，具有用以支援多個編碼序列之執行的資料；複數個可劃分引擎之一或多個資源用戶，以在一給定循環中存取該複數個資源，其中該複數個資源係遍及該複數個可劃分引擎；一通用互連結構，該通用互連結構在每一時脈循環中具有有限數量可存取的匯流排，並用以耦合該一或多資源用戶與該複數個資源以存取該資料且執行該多個編碼序 列，其中該複數個資源包含該可劃分引擎之每一者的暫存器檔案區段與記憶體片段的至少其中之一，其中該複數個資源用戶包含該可劃分引擎之每一者的執行單元或位址計算單元的至少其中之一，其中複數個線程排程器之每一者可操作以識別所請求的資源並競爭以使用該通用互連結構的一或多個匯流排，以針對該複數個資源進行排程以用於經由該通用互連傳輸至該複數個資源用戶，其中該複數個資源被傳輸至該複數個資源用戶係透過以下步驟：在每一資源，加入用以對該每一資源之存取的一些請求，其中該些請求係使用該複數個線程排程器而產生；在該每一資源，比較該一些請求與一臨界限制器；在該每一資源，刪除超過該臨界限制器之一或多個請求，其中被刪除的請求係佇列且在下一循環中給定優先性；以及在該每一資源，執行在一目前時脈循環內未被刪除的請求，其中該加法器在一輸出的一總和表示用於存取對應於一個別請求的一資源的一埠數目。
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Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI506456B (zh) * 2013-05-23 2015-11-01 Chunghwa Telecom Co Ltd 基於Ｈａｄｏｏｐ多叢集環境的工作分派系統及方法
US9542269B1 (en) 2015-06-29 2017-01-10 SK Hynix Inc. Controller controlling semiconductor memory device and operating method thereof
US9921833B2 (en) * 2015-12-15 2018-03-20 International Business Machines Corporation Determining of validity of speculative load data after a predetermined period of time in a multi-slice processor
KR102391493B1 (ko) 2015-12-31 2022-04-28 에스케이하이닉스 주식회사 반도체 장치와 연결된 컨트롤러 및 그것의 동작 방법
US10929139B2 (en) * 2018-09-27 2021-02-23 Qualcomm Incorporated Providing predictive instruction dispatch throttling to prevent resource overflows in out-of-order processor (OOP)-based devices
CN111080510B (zh) * 2019-12-11 2021-02-12 海光信息技术股份有限公司 数据处理装置、方法、芯片、处理器、设备及存储介质
US11416148B2 (en) * 2020-01-10 2022-08-16 Samsung Electronics Co., Ltd. System and method of providing atomicity to large writes to persistent memory
CN111857992B (zh) * 2020-06-24 2024-04-16 厦门网宿有限公司 一种Radosgw模块中线程资源分配方法和装置

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030035422A1 (en) * 2000-03-10 2003-02-20 Hill Alan M Packet switching
US20030169626A1 (en) * 2002-03-06 2003-09-11 Burk Wayne Eric System and method for controlling a number of outstanding data transactions within an integrated circuit
CN1214666C (zh) * 2003-04-07 2005-08-10 华为技术有限公司 位置业务中限制位置信息请求流量的方法
US20080184211A1 (en) * 2007-01-26 2008-07-31 Nvidia Corporation Virtual architecture and instruction set for parallel thread computing
US20080256278A1 (en) * 2005-09-14 2008-10-16 Koninklijke Philips Electronics, N.V. Method and System for Bus Arbitration
US20090113170A1 (en) * 2006-04-12 2009-04-30 Mohammad A Abdallah Apparatus and Method for Processing an Instruction Matrix Specifying Parallel and Dependent Operations
US20100088443A1 (en) * 2007-03-27 2010-04-08 Arm Limited Data processing apparatus and method for arbitrating access to a shared resource

Family Cites Families (484)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US727487A (en) 1902-10-21 1903-05-05 Swan F Swanson Dumping-car.
US4075704A (en) 1976-07-02 1978-02-21 Floating Point Systems, Inc. Floating point data processor for high speech operation
US4228496A (en) 1976-09-07 1980-10-14 Tandem Computers Incorporated Multiprocessor system
US4245344A (en) 1979-04-02 1981-01-13 Rockwell International Corporation Processing system with dual buses
US4527237A (en) 1979-10-11 1985-07-02 Nanodata Computer Corporation Data processing system
US4414624A (en) 1980-11-19 1983-11-08 The United States Of America As Represented By The Secretary Of The Navy Multiple-microcomputer processing
US4524415A (en) 1982-12-07 1985-06-18 Motorola, Inc. Virtual machine data processor
US4597061B1 (en) 1983-01-03 1998-06-09 Texas Instruments Inc Memory system using pipleline circuitry for improved system
US4577273A (en) 1983-06-06 1986-03-18 Sperry Corporation Multiple microcomputer system for digital computers
US4682281A (en) 1983-08-30 1987-07-21 Amdahl Corporation Data storage unit employing translation lookaside buffer pointer
US4633434A (en) 1984-04-02 1986-12-30 Sperry Corporation High performance storage unit
US4600986A (en) 1984-04-02 1986-07-15 Sperry Corporation Pipelined split stack with high performance interleaved decode
JPS6140643A (ja) 1984-07-31 1986-02-26 Hitachi Ltd システムの資源割当て制御方式
US4835680A (en) 1985-03-15 1989-05-30 Xerox Corporation Adaptive processor array capable of learning variable associations useful in recognizing classes of inputs
JPS6289149A (ja) * 1985-10-15 1987-04-23 Agency Of Ind Science & Technol 多ポ−トメモリシステム
JPH0658650B2 (ja) 1986-03-14 1994-08-03 株式会社日立製作所 仮想計算機システム
US4920477A (en) 1987-04-20 1990-04-24 Multiflow Computer, Inc. Virtual address table look aside buffer miss recovery method and apparatus
US4943909A (en) 1987-07-08 1990-07-24 At&T Bell Laboratories Computational origami
US5339398A (en) 1989-07-31 1994-08-16 North American Philips Corporation Memory architecture and method of data organization optimized for hashing
US5471593A (en) 1989-12-11 1995-11-28 Branigin; Michael H. Computer processor with an efficient means of executing many instructions simultaneously
US5197130A (en) 1989-12-29 1993-03-23 Supercomputer Systems Limited Partnership Cluster architecture for a highly parallel scalar/vector multiprocessor system
US5317754A (en) 1990-10-23 1994-05-31 International Business Machines Corporation Method and apparatus for enabling an interpretive execution subset
US5317705A (en) 1990-10-24 1994-05-31 International Business Machines Corporation Apparatus and method for TLB purge reduction in a multi-level machine system
US6282583B1 (en) 1991-06-04 2001-08-28 Silicon Graphics, Inc. Method and apparatus for memory access in a matrix processor computer
US5539911A (en) 1991-07-08 1996-07-23 Seiko Epson Corporation High-performance, superscalar-based computer system with out-of-order instruction execution
JPH0820949B2 (ja) 1991-11-26 1996-03-04 松下電器産業株式会社 情報処理装置
JPH07502358A (ja) 1991-12-23 1995-03-09 インテル・コーポレーション マイクロプロセッサーのクロックに依るマルチプル・アクセスのためのインターリーブ・キャッシュ
KR100309566B1 (ko) 1992-04-29 2001-12-15 리패치 파이프라인프로세서에서다중명령어를무리짓고,그룹화된명령어를동시에발행하고,그룹화된명령어를실행시키는방법및장치
EP0638183B1 (en) 1992-05-01 1997-03-05 Seiko Epson Corporation A system and method for retiring instructions in a superscalar microprocessor
EP0576262B1 (en) 1992-06-25 2000-08-23 Canon Kabushiki Kaisha Apparatus for multiplying integers of many figures
JPH0637202A (ja) 1992-07-20 1994-02-10 Mitsubishi Electric Corp マイクロ波ｉｃ用パッケージ
JPH06110781A (ja) 1992-09-30 1994-04-22 Nec Corp キャッシュメモリ装置
US5493660A (en) 1992-10-06 1996-02-20 Hewlett-Packard Company Software assisted hardware TLB miss handler
US5513335A (en) 1992-11-02 1996-04-30 Sgs-Thomson Microelectronics, Inc. Cache tag memory having first and second single-port arrays and a dual-port array
US5819088A (en) 1993-03-25 1998-10-06 Intel Corporation Method and apparatus for scheduling instructions for execution on a multi-issue architecture computer
JPH0784883A (ja) 1993-09-17 1995-03-31 Hitachi Ltd 仮想計算機システムのアドレス変換バッファパージ方法
US6948172B1 (en) 1993-09-21 2005-09-20 Microsoft Corporation Preemptive multi-tasking with cooperative groups of tasks
US5469376A (en) 1993-10-14 1995-11-21 Abdallah; Mohammad A. F. F. Digital circuit for the evaluation of mathematical expressions
US5517651A (en) 1993-12-29 1996-05-14 Intel Corporation Method and apparatus for loading a segment register in a microprocessor capable of operating in multiple modes
US5956753A (en) 1993-12-30 1999-09-21 Intel Corporation Method and apparatus for handling speculative memory access operations
US5761476A (en) 1993-12-30 1998-06-02 Intel Corporation Non-clocked early read for back-to-back scheduling of instructions
JP3048498B2 (ja) * 1994-04-13 2000-06-05 株式会社東芝 半導体記憶装置
JPH07287668A (ja) 1994-04-19 1995-10-31 Hitachi Ltd データ処理装置
CN1084005C (zh) 1994-06-27 2002-05-01 国际商业机器公司 用于动态控制地址空间分配的方法和设备
US5548742A (en) 1994-08-11 1996-08-20 Intel Corporation Method and apparatus for combining a direct-mapped cache and a multiple-way cache in a cache memory
US5813031A (en) 1994-09-21 1998-09-22 Industrial Technology Research Institute Caching tag for a large scale cache computer memory system
US5640534A (en) 1994-10-05 1997-06-17 International Business Machines Corporation Method and system for concurrent access in a data cache array utilizing multiple match line selection paths
US5835951A (en) 1994-10-18 1998-11-10 National Semiconductor Branch processing unit with target cache read prioritization protocol for handling multiple hits
JP3569014B2 (ja) 1994-11-25 2004-09-22 富士通株式会社 マルチコンテキストをサポートするプロセッサおよび処理方法
US5724565A (en) 1995-02-03 1998-03-03 International Business Machines Corporation Method and system for processing first and second sets of instructions by first and second types of processing systems
US5644742A (en) 1995-02-14 1997-07-01 Hal Computer Systems, Inc. Processor structure and method for a time-out checkpoint
US5675759A (en) 1995-03-03 1997-10-07 Shebanow; Michael C. Method and apparatus for register management using issue sequence prior physical register and register association validity information
US5634068A (en) 1995-03-31 1997-05-27 Sun Microsystems, Inc. Packet switched cache coherent multiprocessor system
US5751982A (en) 1995-03-31 1998-05-12 Apple Computer, Inc. Software emulation system with dynamic translation of emulated instructions for increased processing speed
US6209085B1 (en) 1995-05-05 2001-03-27 Intel Corporation Method and apparatus for performing process switching in multiprocessor computer systems
US6643765B1 (en) 1995-08-16 2003-11-04 Microunity Systems Engineering, Inc. Programmable processor with group floating point operations
US5710902A (en) 1995-09-06 1998-01-20 Intel Corporation Instruction dependency chain indentifier
US6341324B1 (en) 1995-10-06 2002-01-22 Lsi Logic Corporation Exception processing in superscalar microprocessor
US5864657A (en) 1995-11-29 1999-01-26 Texas Micro, Inc. Main memory system and checkpointing protocol for fault-tolerant computer system
US5983327A (en) * 1995-12-01 1999-11-09 Nortel Networks Corporation Data path architecture and arbitration scheme for providing access to a shared system resource
US5793941A (en) 1995-12-04 1998-08-11 Advanced Micro Devices, Inc. On-chip primary cache testing circuit and test method
US5911057A (en) 1995-12-19 1999-06-08 Texas Instruments Incorporated Superscalar microprocessor having combined register and memory renaming circuits, systems, and methods
US5699537A (en) 1995-12-22 1997-12-16 Intel Corporation Processor microarchitecture for efficient dynamic scheduling and execution of chains of dependent instructions
US6882177B1 (en) * 1996-01-10 2005-04-19 Altera Corporation Tristate structures for programmable logic devices
US5754818A (en) 1996-03-22 1998-05-19 Sun Microsystems, Inc. Architecture and method for sharing TLB entries through process IDS
US5904892A (en) 1996-04-01 1999-05-18 Saint-Gobain/Norton Industrial Ceramics Corp. Tape cast silicon carbide dummy wafer
US5752260A (en) 1996-04-29 1998-05-12 International Business Machines Corporation High-speed, multiple-port, interleaved cache with arbitration of multiple access addresses
US5806085A (en) 1996-05-01 1998-09-08 Sun Microsystems, Inc. Method for non-volatile caching of network and CD-ROM file accesses using a cache directory, pointers, file name conversion, a local hard disk, and separate small database
US5829028A (en) 1996-05-06 1998-10-27 Advanced Micro Devices, Inc. Data cache configured to store data in a use-once manner
US6108769A (en) 1996-05-17 2000-08-22 Advanced Micro Devices, Inc. Dependency table for reducing dependency checking hardware
US5881277A (en) 1996-06-13 1999-03-09 Texas Instruments Incorporated Pipelined microprocessor with branch misprediction cache circuits, systems and methods
US5860146A (en) 1996-06-25 1999-01-12 Sun Microsystems, Inc. Auxiliary translation lookaside buffer for assisting in accessing data in remote address spaces
US5903760A (en) 1996-06-27 1999-05-11 Intel Corporation Method and apparatus for translating a conditional instruction compatible with a first instruction set architecture (ISA) into a conditional instruction compatible with a second ISA
US5974506A (en) 1996-06-28 1999-10-26 Digital Equipment Corporation Enabling mirror, nonmirror and partial mirror cache modes in a dual cache system
US6167490A (en) 1996-09-20 2000-12-26 University Of Washington Using global memory information to manage memory in a computer network
KR19980032776A (ko) 1996-10-16 1998-07-25 가나이 츠토무 데이타 프로세서 및 데이타 처리시스템
KR19990076967A (ko) 1996-11-04 1999-10-25 요트.게.아. 롤페즈 처리 장치 및 메모리내의 명령 판독
US6385715B1 (en) 1996-11-13 2002-05-07 Intel Corporation Multi-threading for a processor utilizing a replay queue
US5978906A (en) 1996-11-19 1999-11-02 Advanced Micro Devices, Inc. Branch selectors associated with byte ranges within an instruction cache for rapidly identifying branch predictions
US6253316B1 (en) 1996-11-19 2001-06-26 Advanced Micro Devices, Inc. Three state branch history using one bit in a branch prediction mechanism
US5903750A (en) 1996-11-20 1999-05-11 Institute For The Development Of Emerging Architectures, L.L.P. Dynamic branch prediction for branch instructions with multiple targets
US6212542B1 (en) 1996-12-16 2001-04-03 International Business Machines Corporation Method and system for executing a program within a multiscalar processor by processing linked thread descriptors
US6134634A (en) 1996-12-20 2000-10-17 Texas Instruments Incorporated Method and apparatus for preemptive cache write-back
US5918251A (en) 1996-12-23 1999-06-29 Intel Corporation Method and apparatus for preloading different default address translation attributes
US6016540A (en) 1997-01-08 2000-01-18 Intel Corporation Method and apparatus for scheduling instructions in waves
US6065105A (en) 1997-01-08 2000-05-16 Intel Corporation Dependency matrix
US5802602A (en) 1997-01-17 1998-09-01 Intel Corporation Method and apparatus for performing reads of related data from a set-associative cache memory
JP3739888B2 (ja) * 1997-03-27 2006-01-25 株式会社ソニー・コンピュータエンタテインメント 情報処理装置および方法
US6088780A (en) 1997-03-31 2000-07-11 Institute For The Development Of Emerging Architecture, L.L.C. Page table walker that uses at least one of a default page size and a page size selected for a virtual address space to position a sliding field in a virtual address
US6075938A (en) 1997-06-10 2000-06-13 The Board Of Trustees Of The Leland Stanford Junior University Virtual machine monitors for scalable multiprocessors
US6073230A (en) 1997-06-11 2000-06-06 Advanced Micro Devices, Inc. Instruction fetch unit configured to provide sequential way prediction for sequential instruction fetches
JPH1124929A (ja) 1997-06-30 1999-01-29 Sony Corp 演算処理装置およびその方法
US6128728A (en) 1997-08-01 2000-10-03 Micron Technology, Inc. Virtual shadow registers and virtual register windows
US6170051B1 (en) 1997-08-01 2001-01-02 Micron Technology, Inc. Apparatus and method for program level parallelism in a VLIW processor
US6085315A (en) 1997-09-12 2000-07-04 Siemens Aktiengesellschaft Data processing device with loop pipeline
US6101577A (en) 1997-09-15 2000-08-08 Advanced Micro Devices, Inc. Pipelined instruction cache and branch prediction mechanism therefor
US5901294A (en) * 1997-09-18 1999-05-04 International Business Machines Corporation Method and system for bus arbitration in a multiprocessor system utilizing simultaneous variable-width bus access
US6185660B1 (en) 1997-09-23 2001-02-06 Hewlett-Packard Company Pending access queue for providing data to a target register during an intermediate pipeline phase after a computer cache miss
US5905509A (en) 1997-09-30 1999-05-18 Compaq Computer Corp. Accelerated Graphics Port two level Gart cache having distributed first level caches
US6226732B1 (en) 1997-10-02 2001-05-01 Hitachi Micro Systems, Inc. Memory system architecture
US5922065A (en) 1997-10-13 1999-07-13 Institute For The Development Of Emerging Architectures, L.L.C. Processor utilizing a template field for encoding instruction sequences in a wide-word format
US6178482B1 (en) 1997-11-03 2001-01-23 Brecis Communications Virtual register sets
US6021484A (en) 1997-11-14 2000-02-01 Samsung Electronics Co., Ltd. Dual instruction set architecture
US6256728B1 (en) 1997-11-17 2001-07-03 Advanced Micro Devices, Inc. Processor configured to selectively cancel instructions from its pipeline responsive to a predicted-taken short forward branch instruction
US6260131B1 (en) 1997-11-18 2001-07-10 Intrinsity, Inc. Method and apparatus for TLB memory ordering
US6016533A (en) 1997-12-16 2000-01-18 Advanced Micro Devices, Inc. Way prediction logic for cache array
ATE301195T1 (de) * 1998-01-23 2005-08-15 Immunex Corp Acpl dna und polypeptide
US6219776B1 (en) 1998-03-10 2001-04-17 Billions Of Operations Per Second Merged array controller and processing element
US6609189B1 (en) 1998-03-12 2003-08-19 Yale University Cycle segmented prefix circuits
JP3657424B2 (ja) 1998-03-20 2005-06-08 松下電器産業株式会社 番組情報を放送するセンター装置と端末装置
US6216215B1 (en) 1998-04-02 2001-04-10 Intel Corporation Method and apparatus for senior loads
US6157998A (en) 1998-04-03 2000-12-05 Motorola Inc. Method for performing branch prediction and resolution of two or more branch instructions within two or more branch prediction buffers
US6115809A (en) 1998-04-30 2000-09-05 Hewlett-Packard Company Compiling strong and weak branching behavior instruction blocks to separate caches for dynamic and static prediction
US6205545B1 (en) 1998-04-30 2001-03-20 Hewlett-Packard Company Method and apparatus for using static branch predictions hints with dynamically translated code traces to improve performance
US6256727B1 (en) 1998-05-12 2001-07-03 International Business Machines Corporation Method and system for fetching noncontiguous instructions in a single clock cycle
JPH11338710A (ja) 1998-05-28 1999-12-10 Toshiba Corp 複数種の命令セットを持つプロセッサのためのコンパイル方法ならびに装置および同方法がプログラムされ記録される記録媒体
US6272616B1 (en) 1998-06-17 2001-08-07 Agere Systems Guardian Corp. Method and apparatus for executing multiple instruction streams in a digital processor with multiple data paths
US6988183B1 (en) 1998-06-26 2006-01-17 Derek Chi-Lan Wong Methods for increasing instruction-level parallelism in microprocessors and digital system
US6260138B1 (en) 1998-07-17 2001-07-10 Sun Microsystems, Inc. Method and apparatus for branch instruction processing in a processor
US6122656A (en) 1998-07-31 2000-09-19 Advanced Micro Devices, Inc. Processor configured to map logical register numbers to physical register numbers using virtual register numbers
US6272662B1 (en) 1998-08-04 2001-08-07 International Business Machines Corporation Distributed storage system using front-end and back-end locking
JP2000057054A (ja) 1998-08-12 2000-02-25 Fujitsu Ltd 高速アドレス変換システム
US8631066B2 (en) 1998-09-10 2014-01-14 Vmware, Inc. Mechanism for providing virtual machines for use by multiple users
US6339822B1 (en) 1998-10-02 2002-01-15 Advanced Micro Devices, Inc. Using padded instructions in a block-oriented cache
US6332189B1 (en) 1998-10-16 2001-12-18 Intel Corporation Branch prediction architecture
GB9825102D0 (en) 1998-11-16 1999-01-13 Insignia Solutions Plc Computer system
JP3110404B2 (ja) 1998-11-18 2000-11-20 甲府日本電気株式会社 マイクロプロセッサ装置及びそのソフトウェア命令高速化方法並びにその制御プログラムを記録した記録媒体
US6490673B1 (en) 1998-11-27 2002-12-03 Matsushita Electric Industrial Co., Ltd Processor, compiling apparatus, and compile program recorded on a recording medium
US6519682B2 (en) 1998-12-04 2003-02-11 Stmicroelectronics, Inc. Pipelined non-blocking level two cache system with inherent transaction collision-avoidance
US6477562B2 (en) 1998-12-16 2002-11-05 Clearwater Networks, Inc. Prioritized instruction scheduling for multi-streaming processors
US7020879B1 (en) 1998-12-16 2006-03-28 Mips Technologies, Inc. Interrupt and exception handling for multi-streaming digital processors
DE19860353C1 (de) * 1998-12-28 2000-06-21 Renk Ag Getriebe
US6247097B1 (en) 1999-01-22 2001-06-12 International Business Machines Corporation Aligned instruction cache handling of instruction fetches across multiple predicted branch instructions
US6321298B1 (en) 1999-01-25 2001-11-20 International Business Machines Corporation Full cache coherency across multiple raid controllers
JP3842474B2 (ja) 1999-02-02 2006-11-08 株式会社ルネサステクノロジ データ処理装置
US6327650B1 (en) 1999-02-12 2001-12-04 Vsli Technology, Inc. Pipelined multiprocessing with upstream processor concurrently writing to local register and to register of downstream processor
US6732220B2 (en) 1999-02-17 2004-05-04 Elbrus International Method for emulating hardware features of a foreign architecture in a host operating system environment
US6668316B1 (en) 1999-02-17 2003-12-23 Elbrus International Limited Method and apparatus for conflict-free execution of integer and floating-point operations with a common register file
US6418530B2 (en) 1999-02-18 2002-07-09 Hewlett-Packard Company Hardware/software system for instruction profiling and trace selection using branch history information for branch predictions
US6437789B1 (en) 1999-02-19 2002-08-20 Evans & Sutherland Computer Corporation Multi-level cache controller
US6850531B1 (en) 1999-02-23 2005-02-01 Alcatel Multi-service network switch
US6212613B1 (en) 1999-03-22 2001-04-03 Cisco Technology, Inc. Methods and apparatus for reusing addresses in a computer
US6529928B1 (en) 1999-03-23 2003-03-04 Silicon Graphics, Inc. Floating-point adder performing floating-point and integer operations
EP1050808B1 (en) 1999-05-03 2008-04-30 STMicroelectronics S.A. Computer instruction scheduling
US6449671B1 (en) 1999-06-09 2002-09-10 Ati International Srl Method and apparatus for busing data elements
US6473833B1 (en) * 1999-07-30 2002-10-29 International Business Machines Corporation Integrated cache and directory structure for multi-level caches
US6643770B1 (en) 1999-09-16 2003-11-04 Intel Corporation Branch misprediction recovery using a side memory
US6704822B1 (en) 1999-10-01 2004-03-09 Sun Microsystems, Inc. Arbitration protocol for a shared data cache
US6772325B1 (en) 1999-10-01 2004-08-03 Hitachi, Ltd. Processor architecture and operation for exploiting improved branch control instruction
US6457120B1 (en) 1999-11-01 2002-09-24 International Business Machines Corporation Processor and method including a cache having confirmation bits for improving address predictable branch instruction target predictions
US7441110B1 (en) 1999-12-10 2008-10-21 International Business Machines Corporation Prefetching using future branch path information derived from branch prediction
US7107434B2 (en) * 1999-12-20 2006-09-12 Board Of Regents, The University Of Texas System, method and apparatus for allocating hardware resources using pseudorandom sequences
JP4693326B2 (ja) 1999-12-22 2011-06-01 ウビコム インコーポレイテッド 組込み型プロセッサにおいてゼロタイムコンテクストスイッチを用いて命令レベルをマルチスレッド化するシステムおよび方法
US6557095B1 (en) 1999-12-27 2003-04-29 Intel Corporation Scheduling operations using a dependency matrix
JP2003519833A (ja) 2000-01-03 2003-06-24 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド 依存性連鎖の発行および再発行が可能なスケジューラ
US6542984B1 (en) 2000-01-03 2003-04-01 Advanced Micro Devices, Inc. Scheduler capable of issuing and reissuing dependency chains
US6594755B1 (en) 2000-01-04 2003-07-15 National Semiconductor Corporation System and method for interleaved execution of multiple independent threads
US6728872B1 (en) 2000-02-04 2004-04-27 International Business Machines Corporation Method and apparatus for verifying that instructions are pipelined in correct architectural sequence
GB0002848D0 (en) 2000-02-08 2000-03-29 Siroyan Limited Communicating instruction results in processors and compiling methods for processors
US6615340B1 (en) 2000-03-22 2003-09-02 Wilmot, Ii Richard Byron Extended operand management indicator structure and method
US6604187B1 (en) 2000-06-19 2003-08-05 Advanced Micro Devices, Inc. Providing global translations with address space numbers
US6557083B1 (en) 2000-06-30 2003-04-29 Intel Corporation Memory system for multiple data types
US6704860B1 (en) 2000-07-26 2004-03-09 International Business Machines Corporation Data processing system and method for fetching instruction blocks in response to a detected block sequence
US7206925B1 (en) 2000-08-18 2007-04-17 Sun Microsystems, Inc. Backing Register File for processors
US6728866B1 (en) 2000-08-31 2004-04-27 International Business Machines Corporation Partitioned issue queue and allocation strategy
US6721874B1 (en) 2000-10-12 2004-04-13 International Business Machines Corporation Method and system for dynamically shared completion table supporting multiple threads in a processing system
US7757065B1 (en) 2000-11-09 2010-07-13 Intel Corporation Instruction segment recording scheme
JP2002185513A (ja) 2000-12-18 2002-06-28 Hitachi Ltd パケット通信ネットワークおよびパケット転送制御方法
US6877089B2 (en) 2000-12-27 2005-04-05 International Business Machines Corporation Branch prediction apparatus and process for restoring replaced branch history for use in future branch predictions for an executing program
US6907600B2 (en) 2000-12-27 2005-06-14 Intel Corporation Virtual translation lookaside buffer
US6647466B2 (en) 2001-01-25 2003-11-11 Hewlett-Packard Development Company, L.P. Method and apparatus for adaptively bypassing one or more levels of a cache hierarchy
FR2820921A1 (fr) 2001-02-14 2002-08-16 Canon Kk Dispositif et procede de transmission dans un commutateur
US6985951B2 (en) 2001-03-08 2006-01-10 International Business Machines Corporation Inter-partition message passing method, system and program product for managing workload in a partitioned processing environment
US6950927B1 (en) 2001-04-13 2005-09-27 The United States Of America As Represented By The Secretary Of The Navy System and method for instruction-level parallelism in a programmable multiple network processor environment
US7707397B2 (en) 2001-05-04 2010-04-27 Via Technologies, Inc. Variable group associativity branch target address cache delivering multiple target addresses per cache line
US7200740B2 (en) 2001-05-04 2007-04-03 Ip-First, Llc Apparatus and method for speculatively performing a return instruction in a microprocessor
US6658549B2 (en) 2001-05-22 2003-12-02 Hewlett-Packard Development Company, Lp. Method and system allowing a single entity to manage memory comprising compressed and uncompressed data
US6985591B2 (en) 2001-06-29 2006-01-10 Intel Corporation Method and apparatus for distributing keys for decrypting and re-encrypting publicly distributed media
US7203824B2 (en) 2001-07-03 2007-04-10 Ip-First, Llc Apparatus and method for handling BTAC branches that wrap across instruction cache lines
US7024545B1 (en) 2001-07-24 2006-04-04 Advanced Micro Devices, Inc. Hybrid branch prediction device with two levels of branch prediction cache
US6954846B2 (en) 2001-08-07 2005-10-11 Sun Microsystems, Inc. Microprocessor and method for giving each thread exclusive access to one register file in a multi-threading mode and for giving an active thread access to multiple register files in a single thread mode
US6718440B2 (en) 2001-09-28 2004-04-06 Intel Corporation Memory access latency hiding with hint buffer
US7150021B1 (en) 2001-10-12 2006-12-12 Palau Acquisition Corporation (Delaware) Method and system to allocate resources within an interconnect device according to a resource allocation table
US7117347B2 (en) 2001-10-23 2006-10-03 Ip-First, Llc Processor including fallback branch prediction mechanism for far jump and far call instructions
US7272832B2 (en) 2001-10-25 2007-09-18 Hewlett-Packard Development Company, L.P. Method of protecting user process data in a secure platform inaccessible to the operating system and other tasks on top of the secure platform
US6964043B2 (en) 2001-10-30 2005-11-08 Intel Corporation Method, apparatus, and system to optimize frequently executed code and to use compiler transformation and hardware support to handle infrequently executed code
GB2381886B (en) 2001-11-07 2004-06-23 Sun Microsystems Inc Computer system with virtual memory and paging mechanism
US7092869B2 (en) 2001-11-14 2006-08-15 Ronald Hilton Memory address prediction under emulation
US7363467B2 (en) 2002-01-03 2008-04-22 Intel Corporation Dependence-chain processing using trace descriptors having dependency descriptors
US6640333B2 (en) 2002-01-10 2003-10-28 Lsi Logic Corporation Architecture for a sea of platforms
US7055021B2 (en) 2002-02-05 2006-05-30 Sun Microsystems, Inc. Out-of-order processor that reduces mis-speculation using a replay scoreboard
US7331040B2 (en) 2002-02-06 2008-02-12 Transitive Limted Condition code flag emulation for program code conversion
US6839816B2 (en) * 2002-02-26 2005-01-04 International Business Machines Corporation Shared cache line update mechanism
JP3719509B2 (ja) 2002-04-01 2005-11-24 株式会社ソニー・コンピュータエンタテインメント シリアル演算パイプライン、演算装置、算術論理演算回路およびシリアル演算パイプラインによる演算方法
US7565509B2 (en) 2002-04-17 2009-07-21 Microsoft Corporation Using limits on address translation to control access to an addressable entity
US6920530B2 (en) 2002-04-23 2005-07-19 Sun Microsystems, Inc. Scheme for reordering instructions via an instruction caching mechanism
US7113488B2 (en) * 2002-04-24 2006-09-26 International Business Machines Corporation Reconfigurable circular bus
US7281055B2 (en) 2002-05-28 2007-10-09 Newisys, Inc. Routing mechanisms in systems having multiple multi-processor clusters
US7117346B2 (en) 2002-05-31 2006-10-03 Freescale Semiconductor, Inc. Data processing system having multiple register contexts and method therefor
US6938151B2 (en) 2002-06-04 2005-08-30 International Business Machines Corporation Hybrid branch prediction using a global selection counter and a prediction method comparison table
US8024735B2 (en) 2002-06-14 2011-09-20 Intel Corporation Method and apparatus for ensuring fairness and forward progress when executing multiple threads of execution
JP3845043B2 (ja) 2002-06-28 2006-11-15 富士通株式会社 命令フェッチ制御装置
JP3982353B2 (ja) 2002-07-12 2007-09-26 日本電気株式会社 フォルトトレラントコンピュータ装置、その再同期化方法及び再同期化プログラム
US6944744B2 (en) 2002-08-27 2005-09-13 Advanced Micro Devices, Inc. Apparatus and method for independently schedulable functional units with issue lock mechanism in a processor
US6950925B1 (en) 2002-08-28 2005-09-27 Advanced Micro Devices, Inc. Scheduler for use in a microprocessor that supports data-speculative execution
US7546422B2 (en) 2002-08-28 2009-06-09 Intel Corporation Method and apparatus for the synchronization of distributed caches
TW200408242A (en) 2002-09-06 2004-05-16 Matsushita Electric Ind Co Ltd Home terminal apparatus and communication system
US6895491B2 (en) 2002-09-26 2005-05-17 Hewlett-Packard Development Company, L.P. Memory addressing for a virtual machine implementation on a computer processor supporting virtual hash-page-table searching
US7334086B2 (en) 2002-10-08 2008-02-19 Rmi Corporation Advanced processor with system on a chip interconnect technology
US7213248B2 (en) 2002-10-10 2007-05-01 International Business Machines Corporation High speed promotion mechanism suitable for lock acquisition in a multiprocessor data processing system
US6829698B2 (en) 2002-10-10 2004-12-07 International Business Machines Corporation Method, apparatus and system for acquiring a global promotion facility utilizing a data-less transaction
US7222218B2 (en) 2002-10-22 2007-05-22 Sun Microsystems, Inc. System and method for goal-based scheduling of blocks of code for concurrent execution
US20040103251A1 (en) 2002-11-26 2004-05-27 Mitchell Alsup Microprocessor including a first level cache and a second level cache having different cache line sizes
EP1570334A2 (en) 2002-12-04 2005-09-07 Koninklijke Philips Electronics N.V. Register file gating to reduce microprocessor power dissipation
US6981083B2 (en) 2002-12-05 2005-12-27 International Business Machines Corporation Processor virtualization mechanism via an enhanced restoration of hard architected states
US7073042B2 (en) 2002-12-12 2006-07-04 Intel Corporation Reclaiming existing fields in address translation data structures to extend control over memory accesses
US20040117594A1 (en) 2002-12-13 2004-06-17 Vanderspek Julius Memory management method
US20040122887A1 (en) 2002-12-20 2004-06-24 Macy William W. Efficient multiplication of small matrices using SIMD registers
US7191349B2 (en) 2002-12-26 2007-03-13 Intel Corporation Mechanism for processor power state aware distribution of lowest priority interrupt
US20040139441A1 (en) 2003-01-09 2004-07-15 Kabushiki Kaisha Toshiba Processor, arithmetic operation processing method, and priority determination method
US6925421B2 (en) 2003-01-09 2005-08-02 International Business Machines Corporation Method, system, and computer program product for estimating the number of consumers that place a load on an individual resource in a pool of physically distributed resources
US7178010B2 (en) 2003-01-16 2007-02-13 Ip-First, Llc Method and apparatus for correcting an internal call/return stack in a microprocessor that detects from multiple pipeline stages incorrect speculative update of the call/return stack
US7089374B2 (en) 2003-02-13 2006-08-08 Sun Microsystems, Inc. Selectively unmarking load-marked cache lines during transactional program execution
US7278030B1 (en) 2003-03-03 2007-10-02 Vmware, Inc. Virtualization system for computers having multiple protection mechanisms
US6912644B1 (en) 2003-03-06 2005-06-28 Intel Corporation Method and apparatus to steer memory access operations in a virtual memory system
US7111145B1 (en) 2003-03-25 2006-09-19 Vmware, Inc. TLB miss fault handler and method for accessing multiple page tables
US7143273B2 (en) 2003-03-31 2006-11-28 Intel Corporation Method and apparatus for dynamic branch prediction utilizing multiple stew algorithms for indexing a global history
US7058764B2 (en) 2003-04-14 2006-06-06 Hewlett-Packard Development Company, L.P. Method of adaptive cache partitioning to increase host I/O performance
US7139855B2 (en) 2003-04-24 2006-11-21 International Business Machines Corporation High performance synchronization of resource allocation in a logically-partitioned system
US7469407B2 (en) 2003-04-24 2008-12-23 International Business Machines Corporation Method for resource balancing using dispatch flush in a simultaneous multithread processor
EP1471421A1 (en) 2003-04-24 2004-10-27 STMicroelectronics Limited Speculative load instruction control
US7290261B2 (en) 2003-04-24 2007-10-30 International Business Machines Corporation Method and logical apparatus for rename register reallocation in a simultaneous multi-threaded (SMT) processor
US7055003B2 (en) 2003-04-25 2006-05-30 International Business Machines Corporation Data cache scrub mechanism for large L2/L3 data cache structures
US7007108B2 (en) 2003-04-30 2006-02-28 Lsi Logic Corporation System method for use of hardware semaphores for resource release notification wherein messages comprises read-modify-write operation and address
JP2007519052A (ja) 2003-06-25 2007-07-12 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ 命令制御式データ処理装置
JP2005032018A (ja) 2003-07-04 2005-02-03 Semiconductor Energy Lab Co Ltd 遺伝的アルゴリズムを用いたマイクロプロセッサ
US7149872B2 (en) 2003-07-10 2006-12-12 Transmeta Corporation System and method for identifying TLB entries associated with a physical address of a specified range
US7089398B2 (en) 2003-07-31 2006-08-08 Silicon Graphics, Inc. Address translation using a page size tag
US8296771B2 (en) 2003-08-18 2012-10-23 Cray Inc. System and method for mapping between resource consumers and resource providers in a computing system
US7133950B2 (en) 2003-08-19 2006-11-07 Sun Microsystems, Inc. Request arbitration in multi-core processor
US9032404B2 (en) 2003-08-28 2015-05-12 Mips Technologies, Inc. Preemptive multitasking employing software emulation of directed exceptions in a multithreading processor
JP4818919B2 (ja) 2003-08-28 2011-11-16 ミップス テクノロジーズ インコーポレイテッド プロセッサ内での実行の計算スレッドを一時停止して割り当て解除するための統合されたメカニズム
US7849297B2 (en) 2003-08-28 2010-12-07 Mips Technologies, Inc. Software emulation of directed exceptions in a multithreading processor
US7594089B2 (en) 2003-08-28 2009-09-22 Mips Technologies, Inc. Smart memory based synchronization controller for a multi-threaded multiprocessor SoC
US7111126B2 (en) 2003-09-24 2006-09-19 Arm Limited Apparatus and method for loading data values
JP4057989B2 (ja) 2003-09-26 2008-03-05 株式会社東芝 スケジューリング方法および情報処理システム
US7373637B2 (en) 2003-09-30 2008-05-13 International Business Machines Corporation Method and apparatus for counting instruction and memory location ranges
FR2860313B1 (fr) 2003-09-30 2005-11-04 Commissariat Energie Atomique Composant a architecture reconfigurable dynamiquement
US7047322B1 (en) 2003-09-30 2006-05-16 Unisys Corporation System and method for performing conflict resolution and flow control in a multiprocessor system
TWI281121B (en) 2003-10-06 2007-05-11 Ip First Llc Apparatus and method for selectively overriding return stack prediction in response to detection of non-standard return sequence
US8407433B2 (en) 2007-06-25 2013-03-26 Sonics, Inc. Interconnect implementing internal controls
US7395372B2 (en) 2003-11-14 2008-07-01 International Business Machines Corporation Method and system for providing cache set selection which is power optimized
US7243170B2 (en) 2003-11-24 2007-07-10 International Business Machines Corporation Method and circuit for reading and writing an instruction buffer
US20050120191A1 (en) 2003-12-02 2005-06-02 Intel Corporation (A Delaware Corporation) Checkpoint-based register reclamation
US20050132145A1 (en) 2003-12-15 2005-06-16 Finisar Corporation Contingent processor time division multiple access of memory in a multi-processor system to allow supplemental memory consumer access
US7310722B2 (en) 2003-12-18 2007-12-18 Nvidia Corporation Across-thread out of order instruction dispatch in a multithreaded graphics processor
US7293164B2 (en) 2004-01-14 2007-11-06 International Business Machines Corporation Autonomic method and apparatus for counting branch instructions to generate branch statistics meant to improve branch predictions
US20050204118A1 (en) 2004-02-27 2005-09-15 National Chiao Tung University Method for inter-cluster communication that employs register permutation
WO2005089241A2 (en) * 2004-03-13 2005-09-29 Cluster Resources, Inc. System and method for providing object triggers
US20050216920A1 (en) 2004-03-24 2005-09-29 Vijay Tewari Use of a virtual machine to emulate a hardware device
EP1731998A1 (en) 2004-03-29 2006-12-13 Kyoto University Data processing device, data processing program, and recording medium containing the data processing program
US7383427B2 (en) 2004-04-22 2008-06-03 Sony Computer Entertainment Inc. Multi-scalar extension for SIMD instruction set processors
US20050251649A1 (en) 2004-04-23 2005-11-10 Sony Computer Entertainment Inc. Methods and apparatus for address map optimization on a multi-scalar extension
US7418582B1 (en) 2004-05-13 2008-08-26 Sun Microsystems, Inc. Versatile register file design for a multi-threaded processor utilizing different modes and register windows
US7478198B2 (en) 2004-05-24 2009-01-13 Intel Corporation Multithreaded clustered microarchitecture with dynamic back-end assignment
US7594234B1 (en) 2004-06-04 2009-09-22 Sun Microsystems, Inc. Adaptive spin-then-block mutual exclusion in multi-threaded processing
US7284092B2 (en) 2004-06-24 2007-10-16 International Business Machines Corporation Digital data processing apparatus having multi-level register file
US20050289530A1 (en) 2004-06-29 2005-12-29 Robison Arch D Scheduling of instructions in program compilation
EP1628235A1 (en) 2004-07-01 2006-02-22 Texas Instruments Incorporated Method and system of ensuring integrity of a secure mode entry sequence
US8044951B1 (en) 2004-07-02 2011-10-25 Nvidia Corporation Integer-based functionality in a graphics shading language
US7339592B2 (en) 2004-07-13 2008-03-04 Nvidia Corporation Simulating multiported memories using lower port count memories
US7398347B1 (en) 2004-07-14 2008-07-08 Altera Corporation Methods and apparatus for dynamic instruction controlled reconfigurable register file
EP1619593A1 (en) 2004-07-22 2006-01-25 Sap Ag Computer-Implemented method and system for performing a product availability check
JP4064380B2 (ja) 2004-07-29 2008-03-19 富士通株式会社 演算処理装置およびその制御方法
US8443171B2 (en) 2004-07-30 2013-05-14 Hewlett-Packard Development Company, L.P. Run-time updating of prediction hint instructions
US7213106B1 (en) 2004-08-09 2007-05-01 Sun Microsystems, Inc. Conservative shadow cache support in a point-to-point connected multiprocessing node
US7318143B2 (en) 2004-10-20 2008-01-08 Arm Limited Reuseable configuration data
US20090150890A1 (en) 2007-12-10 2009-06-11 Yourst Matt T Strand-based computing hardware and dynamically optimizing strandware for a high performance microprocessor system
US7707578B1 (en) 2004-12-16 2010-04-27 Vmware, Inc. Mechanism for scheduling execution of threads for fair resource allocation in a multi-threaded and/or multi-core processing system
US7257695B2 (en) 2004-12-28 2007-08-14 Intel Corporation Register file regions for a processing system
US7996644B2 (en) 2004-12-29 2011-08-09 Intel Corporation Fair sharing of a cache in a multi-core/multi-threaded processor by dynamically partitioning of the cache
US8719819B2 (en) 2005-06-30 2014-05-06 Intel Corporation Mechanism for instruction set based thread execution on a plurality of instruction sequencers
US7050922B1 (en) 2005-01-14 2006-05-23 Agilent Technologies, Inc. Method for optimizing test order, and machine-readable media storing sequences of instructions to perform same
US7681014B2 (en) 2005-02-04 2010-03-16 Mips Technologies, Inc. Multithreading instruction scheduler employing thread group priorities
US7657891B2 (en) 2005-02-04 2010-02-02 Mips Technologies, Inc. Multithreading microprocessor with optimized thread scheduler for increasing pipeline utilization efficiency
JP2008530642A (ja) 2005-02-07 2008-08-07 ペーアーツェーテー イクスペーペー テクノロジーズ アクチエンゲゼルシャフト 低レイテンシーの大量並列データ処理装置
US7400548B2 (en) 2005-02-09 2008-07-15 International Business Machines Corporation Method for providing multiple reads/writes using a 2read/2write register file array
US7343476B2 (en) 2005-02-10 2008-03-11 International Business Machines Corporation Intelligent SMT thread hang detect taking into account shared resource contention/blocking
US7152155B2 (en) 2005-02-18 2006-12-19 Qualcomm Incorporated System and method of correcting a branch misprediction
US20060200655A1 (en) 2005-03-04 2006-09-07 Smith Rodney W Forward looking branch target address caching
US20060212853A1 (en) 2005-03-18 2006-09-21 Marvell World Trade Ltd. Real-time control apparatus having a multi-thread processor
US8195922B2 (en) 2005-03-18 2012-06-05 Marvell World Trade, Ltd. System for dynamically allocating processing time to multiple threads
GB2424727B (en) 2005-03-30 2007-08-01 Transitive Ltd Preparing instruction groups for a processor having a multiple issue ports
US8522253B1 (en) 2005-03-31 2013-08-27 Guillermo Rozas Hardware support for virtual machine and operating system context switching in translation lookaside buffers and virtually tagged caches
US20060230243A1 (en) 2005-04-06 2006-10-12 Robert Cochran Cascaded snapshots
US7313775B2 (en) 2005-04-06 2007-12-25 Lsi Corporation Integrated circuit with relocatable processor hardmac
US20060230409A1 (en) 2005-04-07 2006-10-12 Matteo Frigo Multithreaded processor architecture with implicit granularity adaptation
US8230423B2 (en) 2005-04-07 2012-07-24 International Business Machines Corporation Multithreaded processor architecture with operational latency hiding
US20060230253A1 (en) 2005-04-11 2006-10-12 Lucian Codrescu Unified non-partitioned register files for a digital signal processor operating in an interleaved multi-threaded environment
US20060236074A1 (en) 2005-04-14 2006-10-19 Arm Limited Indicating storage locations within caches
US7437543B2 (en) 2005-04-19 2008-10-14 International Business Machines Corporation Reducing the fetch time of target instructions of a predicted taken branch instruction
US7461237B2 (en) 2005-04-20 2008-12-02 Sun Microsystems, Inc. Method and apparatus for suppressing duplicative prefetches for branch target cache lines
US8713286B2 (en) 2005-04-26 2014-04-29 Qualcomm Incorporated Register files for a digital signal processor operating in an interleaved multi-threaded environment
GB2426084A (en) 2005-05-13 2006-11-15 Agilent Technologies Inc Updating data in a dual port memory
US7861055B2 (en) 2005-06-07 2010-12-28 Broadcom Corporation Method and system for on-chip configurable data ram for fast memory and pseudo associative caches
US8010969B2 (en) 2005-06-13 2011-08-30 Intel Corporation Mechanism for monitoring instruction set based thread execution on a plurality of instruction sequencers
GB2444455A (en) 2005-08-29 2008-06-04 Searete Llc Scheduling mechanism of a hierarchical processor including multiple parallel clusters
US7350056B2 (en) 2005-09-27 2008-03-25 International Business Machines Corporation Method and apparatus for issuing instructions from an issue queue in an information handling system
US7606975B1 (en) 2005-09-28 2009-10-20 Sun Microsystems, Inc. Trace cache for efficient self-modifying code processing
US7231106B2 (en) 2005-09-30 2007-06-12 Lucent Technologies Inc. Apparatus for directing an optical signal from an input fiber to an output fiber within a high index host
US7613131B2 (en) 2005-11-10 2009-11-03 Citrix Systems, Inc. Overlay network infrastructure
US7681019B1 (en) 2005-11-18 2010-03-16 Sun Microsystems, Inc. Executing functions determined via a collection of operations from translated instructions
US7861060B1 (en) 2005-12-15 2010-12-28 Nvidia Corporation Parallel data processing systems and methods using cooperative thread arrays and thread identifier values to determine processing behavior
US7634637B1 (en) 2005-12-16 2009-12-15 Nvidia Corporation Execution of parallel groups of threads with per-instruction serialization
US7673111B2 (en) * 2005-12-23 2010-03-02 Intel Corporation Memory system with both single and consolidated commands
US7770161B2 (en) 2005-12-28 2010-08-03 International Business Machines Corporation Post-register allocation profile directed instruction scheduling
US8423682B2 (en) 2005-12-30 2013-04-16 Intel Corporation Address space emulation
GB2435362B (en) 2006-02-20 2008-11-26 Cramer Systems Ltd Method of configuring devices in a telecommunications network
JP4332205B2 (ja) 2006-02-27 2009-09-16 富士通株式会社 キャッシュ制御装置およびキャッシュ制御方法
US7543282B2 (en) 2006-03-24 2009-06-02 Sun Microsystems, Inc. Method and apparatus for selectively executing different executable code versions which are optimized in different ways
US7577820B1 (en) 2006-04-14 2009-08-18 Tilera Corporation Managing data in a parallel processing environment
US7610571B2 (en) 2006-04-14 2009-10-27 Cadence Design Systems, Inc. Method and system for simulating state retention of an RTL design
CN100485636C (zh) 2006-04-24 2009-05-06 华为技术有限公司 一种基于模型驱动进行电信级业务开发的调试方法及装置
US7804076B2 (en) 2006-05-10 2010-09-28 Taiwan Semiconductor Manufacturing Co., Ltd Insulator for high current ion implanters
US8145882B1 (en) 2006-05-25 2012-03-27 Mips Technologies, Inc. Apparatus and method for processing template based user defined instructions
JP2008028836A (ja) * 2006-07-24 2008-02-07 Fujitsu Ltd 超伝導フィルタデバイスおよびその作製方法
US20080126771A1 (en) 2006-07-25 2008-05-29 Lei Chen Branch Target Extension for an Instruction Cache
CN100495324C (zh) 2006-07-27 2009-06-03 中国科学院计算技术研究所 复杂指令集体系结构中的深度优先异常处理方法
US7616826B2 (en) * 2006-07-28 2009-11-10 Massachusetts Institute Of Technology Removing camera shake from a single photograph using statistics of a natural image
US8046775B2 (en) 2006-08-14 2011-10-25 Marvell World Trade Ltd. Event-based bandwidth allocation mode switching method and apparatus
US7904704B2 (en) 2006-08-14 2011-03-08 Marvell World Trade Ltd. Instruction dispatching method and apparatus
US7539842B2 (en) 2006-08-15 2009-05-26 International Business Machines Corporation Computer memory system for selecting memory buses according to physical memory organization information stored in virtual address translation tables
JP4841358B2 (ja) * 2006-08-18 2011-12-21 富士通株式会社 リクエスト送信制御装置およびリクエスト送信制御方法
US7594060B2 (en) 2006-08-23 2009-09-22 Sun Microsystems, Inc. Data buffer allocation in a non-blocking data services platform using input/output switching fabric
US7752474B2 (en) 2006-09-22 2010-07-06 Apple Inc. L1 cache flush when processor is entering low power mode
US7716460B2 (en) 2006-09-29 2010-05-11 Qualcomm Incorporated Effective use of a BHT in processor having variable length instruction set execution modes
US7774549B2 (en) 2006-10-11 2010-08-10 Mips Technologies, Inc. Horizontally-shared cache victims in multiple core processors
TWI337495B (en) 2006-10-26 2011-02-11 Au Optronics Corp System and method for operation scheduling
US7680988B1 (en) 2006-10-30 2010-03-16 Nvidia Corporation Single interconnect providing read and write access to a memory shared by concurrent threads
US7617384B1 (en) 2006-11-06 2009-11-10 Nvidia Corporation Structured programming control flow using a disable mask in a SIMD architecture
EP2527972A3 (en) 2006-11-14 2014-08-06 Soft Machines, Inc. Apparatus and method for processing complex instruction formats in a multi- threaded architecture supporting various context switch modes and virtualization schemes
US7493475B2 (en) 2006-11-15 2009-02-17 Stmicroelectronics, Inc. Instruction vector-mode processing in multi-lane processor by multiplex switch replicating instruction in one lane to select others along with updated operand address
US7934179B2 (en) 2006-11-20 2011-04-26 Et International, Inc. Systems and methods for logic verification
US20080235500A1 (en) 2006-11-21 2008-09-25 Davis Gordon T Structure for instruction cache trace formation
JP2008130056A (ja) * 2006-11-27 2008-06-05 Renesas Technology Corp 半導体回路
US7783869B2 (en) 2006-12-19 2010-08-24 Arm Limited Accessing branch predictions ahead of instruction fetching
WO2008077088A2 (en) 2006-12-19 2008-06-26 The Board Of Governors For Higher Education, State Of Rhode Island And Providence Plantations System and method for branch misprediction prediction using complementary branch predictors
EP1940028B1 (en) 2006-12-29 2012-02-29 STMicroelectronics Srl Asynchronous interconnection system for 3D inter-chip communication
TW200833002A (en) 2007-01-31 2008-08-01 Univ Nat Yunlin Sci & Tech Distributed switching circuit having fairness
US20080189501A1 (en) 2007-02-05 2008-08-07 Irish John D Methods and Apparatus for Issuing Commands on a Bus
US7685410B2 (en) 2007-02-13 2010-03-23 Global Foundries Inc. Redirect recovery cache that receives branch misprediction redirects and caches instructions to be dispatched in response to the redirects
US7647483B2 (en) 2007-02-20 2010-01-12 Sony Computer Entertainment Inc. Multi-threaded parallel processor methods and apparatus
JP4980751B2 (ja) 2007-03-02 2012-07-18 富士通セミコンダクター株式会社 データ処理装置、およびメモリのリードアクティブ制御方法。
US20080250227A1 (en) 2007-04-04 2008-10-09 Linderman Michael D General Purpose Multiprocessor Programming Apparatus And Method
US7716183B2 (en) 2007-04-11 2010-05-11 Dot Hill Systems Corporation Snapshot preserved data cloning
US7941791B2 (en) 2007-04-13 2011-05-10 Perry Wang Programming environment for heterogeneous processor resource integration
US7769955B2 (en) 2007-04-27 2010-08-03 Arm Limited Multiple thread instruction fetch from different cache levels
JP2008293487A (ja) * 2007-04-27 2008-12-04 Panasonic Corp プロセッサシステム、バス制御方法および半導体装置
US7711935B2 (en) 2007-04-30 2010-05-04 Netlogic Microsystems, Inc. Universal branch identifier for invalidation of speculative instructions
US8555039B2 (en) 2007-05-03 2013-10-08 Qualcomm Incorporated System and method for using a local condition code register for accelerating conditional instruction execution in a pipeline processor
US8219996B1 (en) 2007-05-09 2012-07-10 Hewlett-Packard Development Company, L.P. Computer processor with fairness monitor
CN101344840B (zh) 2007-07-10 2011-08-31 苏州简约纳电子有限公司 一种微处理器及在微处理器中执行指令的方法
US7937568B2 (en) 2007-07-11 2011-05-03 International Business Machines Corporation Adaptive execution cycle control method for enhanced instruction throughput
US20090025004A1 (en) 2007-07-16 2009-01-22 Microsoft Corporation Scheduling by Growing and Shrinking Resource Allocation
US8108545B2 (en) 2007-08-27 2012-01-31 International Business Machines Corporation Packet coalescing in virtual channels of a data processing system in a multi-tiered full-graph interconnect architecture
US7711929B2 (en) 2007-08-30 2010-05-04 International Business Machines Corporation Method and system for tracking instruction dependency in an out-of-order processor
GB2452316B (en) * 2007-08-31 2009-08-19 Toshiba Res Europ Ltd Method of Allocating Resources in a Computer.
US8725991B2 (en) 2007-09-12 2014-05-13 Qualcomm Incorporated Register file system and method for pipelined processing
US8082420B2 (en) 2007-10-24 2011-12-20 International Business Machines Corporation Method and apparatus for executing instructions
US7856530B1 (en) 2007-10-31 2010-12-21 Network Appliance, Inc. System and method for implementing a dynamic cache for a data storage system
JP2011503710A (ja) * 2007-11-09 2011-01-27 プルラリティー リミテッド しっかりと連結されたマルチプロセッサのための共有メモリ・システム
US7877559B2 (en) 2007-11-26 2011-01-25 Globalfoundries Inc. Mechanism to accelerate removal of store operations from a queue
US8245232B2 (en) 2007-11-27 2012-08-14 Microsoft Corporation Software-configurable and stall-time fair memory access scheduling mechanism for shared memory systems
US7809925B2 (en) 2007-12-07 2010-10-05 International Business Machines Corporation Processing unit incorporating vectorizable execution unit
US8145844B2 (en) 2007-12-13 2012-03-27 Arm Limited Memory controller with write data cache and read data cache
US7831813B2 (en) 2007-12-17 2010-11-09 Globalfoundries Inc. Uses of known good code for implementing processor architectural modifications
US7870371B2 (en) 2007-12-17 2011-01-11 Microsoft Corporation Target-frequency based indirect jump prediction for high-performance processors
US20090165007A1 (en) 2007-12-19 2009-06-25 Microsoft Corporation Task-level thread scheduling and resource allocation
US8782384B2 (en) 2007-12-20 2014-07-15 Advanced Micro Devices, Inc. Branch history with polymorphic indirect branch information
US7917699B2 (en) 2007-12-21 2011-03-29 Mips Technologies, Inc. Apparatus and method for controlling the exclusivity mode of a level-two cache
US9244855B2 (en) 2007-12-31 2016-01-26 Intel Corporation Method, system, and apparatus for page sizing extension
US8645965B2 (en) 2007-12-31 2014-02-04 Intel Corporation Supporting metered clients with manycore through time-limited partitioning
US7877582B2 (en) 2008-01-31 2011-01-25 International Business Machines Corporation Multi-addressable register file
WO2009101563A1 (en) 2008-02-11 2009-08-20 Nxp B.V. Multiprocessing implementing a plurality of virtual processors
US7949972B2 (en) 2008-03-19 2011-05-24 International Business Machines Corporation Method, system and computer program product for exploiting orthogonal control vectors in timing driven synthesis
US7987343B2 (en) 2008-03-19 2011-07-26 International Business Machines Corporation Processor and method for synchronous load multiple fetching sequence and pipeline stage result tracking to facilitate early address generation interlock bypass
US9513905B2 (en) 2008-03-28 2016-12-06 Intel Corporation Vector instructions to enable efficient synchronization and parallel reduction operations
US8120608B2 (en) 2008-04-04 2012-02-21 Via Technologies, Inc. Constant buffering for a computational core of a programmable graphics processing unit
TWI364703B (en) 2008-05-26 2012-05-21 Faraday Tech Corp Processor and early execution method of data load thereof
US8131982B2 (en) 2008-06-13 2012-03-06 International Business Machines Corporation Branch prediction instructions having mask values involving unloading and loading branch history data
US8145880B1 (en) 2008-07-07 2012-03-27 Ovics Matrix processor data switch routing systems and methods
JP5733860B2 (ja) 2008-07-10 2015-06-10 ロケティック テクノロジーズ リミテッド 依存問題の効率的並列計算
JP2010039536A (ja) 2008-07-31 2010-02-18 Panasonic Corp プログラム変換装置、プログラム変換方法およびプログラム変換プログラム
US8316435B1 (en) 2008-08-14 2012-11-20 Juniper Networks, Inc. Routing device having integrated MPLS-aware firewall with virtual security system support
US8135942B2 (en) 2008-08-28 2012-03-13 International Business Machines Corpration System and method for double-issue instructions using a dependency matrix and a side issue queue
US7769984B2 (en) 2008-09-11 2010-08-03 International Business Machines Corporation Dual-issuance of microprocessor instructions using dual dependency matrices
US8225048B2 (en) * 2008-10-01 2012-07-17 Hewlett-Packard Development Company, L.P. Systems and methods for resource access
US9244732B2 (en) 2009-08-28 2016-01-26 Vmware, Inc. Compensating threads for microarchitectural resource contentions by prioritizing scheduling and execution
US7941616B2 (en) 2008-10-21 2011-05-10 Microsoft Corporation System to reduce interference in concurrent programs
US8423749B2 (en) 2008-10-22 2013-04-16 International Business Machines Corporation Sequential processing in network on chip nodes by threads generating message containing payload and pointer for nanokernel to access algorithm to be executed on payload in another node
GB2464703A (en) 2008-10-22 2010-04-28 Advanced Risc Mach Ltd An array of interconnected processors executing a cycle-based program
KR101374452B1 (ko) 2008-10-30 2014-03-17 노키아 코포레이션 데이터 블록을 인터리빙하기 위한 방법 및 장치
US8032678B2 (en) * 2008-11-05 2011-10-04 Mediatek Inc. Shared resource arbitration
US7848129B1 (en) 2008-11-20 2010-12-07 Netlogic Microsystems, Inc. Dynamically partitioned CAM array
US8868838B1 (en) 2008-11-21 2014-10-21 Nvidia Corporation Multi-class data cache policies
US8171223B2 (en) 2008-12-03 2012-05-01 Intel Corporation Method and system to increase concurrency and control replication in a multi-core cache hierarchy
US8200949B1 (en) 2008-12-09 2012-06-12 Nvidia Corporation Policy based allocation of register file cache to threads in multi-threaded processor
US8312268B2 (en) 2008-12-12 2012-11-13 International Business Machines Corporation Virtual machine
US7870308B2 (en) * 2008-12-23 2011-01-11 International Business Machines Corporation Programmable direct memory access engine
US8099586B2 (en) 2008-12-30 2012-01-17 Oracle America, Inc. Branch misprediction recovery mechanism for microprocessors
US20100169578A1 (en) 2008-12-31 2010-07-01 Texas Instruments Incorporated Cache tag memory
US20100205603A1 (en) 2009-02-09 2010-08-12 Unisys Corporation Scheduling and dispatching tasks in an emulated operating system
JP5417879B2 (ja) 2009-02-17 2014-02-19 富士通セミコンダクター株式会社 キャッシュ装置
JP2010226275A (ja) * 2009-03-23 2010-10-07 Nec Corp 通信装置および通信方法
US8505013B2 (en) 2010-03-12 2013-08-06 Lsi Corporation Reducing data read latency in a network communications processor architecture
US8805788B2 (en) 2009-05-04 2014-08-12 Moka5, Inc. Transactional virtual disk with differential snapshots
US8332854B2 (en) 2009-05-19 2012-12-11 Microsoft Corporation Virtualized thread scheduling for hardware thread optimization based on hardware resource parameter summaries of instruction blocks in execution groups
US8533437B2 (en) 2009-06-01 2013-09-10 Via Technologies, Inc. Guaranteed prefetch instruction
GB2471067B (en) 2009-06-12 2011-11-30 Graeme Roy Smith Shared resource multi-thread array processor
US9122487B2 (en) 2009-06-23 2015-09-01 Oracle America, Inc. System and method for balancing instruction loads between multiple execution units using assignment history
US8386754B2 (en) 2009-06-24 2013-02-26 Arm Limited Renaming wide register source operand with plural short register source operands for select instructions to detect dependency fast with existing mechanism
CN101582025B (zh) 2009-06-25 2011-05-25 浙江大学 片上多处理器体系架构下全局寄存器重命名表的实现方法
US8397049B2 (en) 2009-07-13 2013-03-12 Apple Inc. TLB prefetching
US8539486B2 (en) 2009-07-17 2013-09-17 International Business Machines Corporation Transactional block conflict resolution based on the determination of executing threads in parallel or in serial mode
JP5423217B2 (ja) 2009-08-04 2014-02-19 富士通株式会社 演算処理装置、情報処理装置、および演算処理装置の制御方法
US8127078B2 (en) 2009-10-02 2012-02-28 International Business Machines Corporation High performance unaligned cache access
US20110082983A1 (en) 2009-10-06 2011-04-07 Alcatel-Lucent Canada, Inc. Cpu instruction and data cache corruption prevention system
US8695002B2 (en) 2009-10-20 2014-04-08 Lantiq Deutschland Gmbh Multi-threaded processors and multi-processor systems comprising shared resources
US8364933B2 (en) 2009-12-18 2013-01-29 International Business Machines Corporation Software assisted translation lookaside buffer search mechanism
JP2011150397A (ja) * 2010-01-19 2011-08-04 Panasonic Corp バス調停装置
KR101699910B1 (ko) 2010-03-04 2017-01-26 삼성전자주식회사 재구성 가능 프로세서 및 그 제어 방법
US20120005462A1 (en) 2010-07-01 2012-01-05 International Business Machines Corporation Hardware Assist for Optimizing Code During Processing
DE102010036311A1 (de) * 2010-07-09 2012-01-12 Leica Biosystems Nussloch Gmbh Verfahren zur Reduktion der Verschleppung in einer Färbevorrichtung
US8312258B2 (en) 2010-07-22 2012-11-13 Intel Corporation Providing platform independent memory logic
US8751745B2 (en) 2010-08-11 2014-06-10 Advanced Micro Devices, Inc. Method for concurrent flush of L1 and L2 caches
CN101916180B (zh) 2010-08-11 2013-05-29 中国科学院计算技术研究所 Risc处理器中执行寄存器类型指令的方法和其系统
US8756329B2 (en) 2010-09-15 2014-06-17 Oracle International Corporation System and method for parallel multiplexing between servers in a cluster
US9201801B2 (en) 2010-09-15 2015-12-01 International Business Machines Corporation Computing device with asynchronous auxiliary execution unit
KR101685247B1 (ko) 2010-09-17 2016-12-09 소프트 머신즈, 인크. 조기 원거리 분기 예측을 위한 섀도우 캐시를 포함하는 단일 사이클 다중 분기 예측
US20120079212A1 (en) 2010-09-23 2012-03-29 International Business Machines Corporation Architecture for sharing caches among multiple processes
US9733944B2 (en) 2010-10-12 2017-08-15 Intel Corporation Instruction sequence buffer to store branches having reliably predictable instruction sequences
US9678755B2 (en) 2010-10-12 2017-06-13 Intel Corporation Instruction sequence buffer to enhance branch prediction efficiency
US8370553B2 (en) * 2010-10-18 2013-02-05 International Business Machines Corporation Formal verification of random priority-based arbiters using property strengthening and underapproximations
US9047178B2 (en) 2010-12-13 2015-06-02 SanDisk Technologies, Inc. Auto-commit memory synchronization
US8677355B2 (en) 2010-12-17 2014-03-18 Microsoft Corporation Virtual machine branching and parallel execution
WO2012103245A2 (en) 2011-01-27 2012-08-02 Soft Machines Inc. Guest instruction block with near branching and far branching sequence construction to native instruction block
EP2689326B1 (en) 2011-03-25 2022-11-16 Intel Corporation Memory fragments for supporting code block execution by using virtual cores instantiated by partitionable engines
CN108376097B (zh) 2011-03-25 2022-04-15 英特尔公司 用于通过使用由可分割引擎实例化的虚拟核来支持代码块执行的寄存器文件段
CN103547993B (zh) 2011-03-25 2018-06-26 英特尔公司 通过使用由可分割引擎实例化的虚拟核来执行指令序列代码块
US20120254592A1 (en) 2011-04-01 2012-10-04 Jesus Corbal San Adrian Systems, apparatuses, and methods for expanding a memory source into a destination register and compressing a source register into a destination memory location
US9740494B2 (en) 2011-04-29 2017-08-22 Arizona Board Of Regents For And On Behalf Of Arizona State University Low complexity out-of-order issue logic using static circuits
US8843690B2 (en) 2011-07-11 2014-09-23 Avago Technologies General Ip (Singapore) Pte. Ltd. Memory conflicts learning capability
US8930432B2 (en) 2011-08-04 2015-01-06 International Business Machines Corporation Floating point execution unit with fixed point functionality
US20130046934A1 (en) 2011-08-15 2013-02-21 Robert Nychka System caching using heterogenous memories
US8839025B2 (en) 2011-09-30 2014-09-16 Oracle International Corporation Systems and methods for retiring and unretiring cache lines
EP2783280B1 (en) 2011-11-22 2019-09-11 Intel Corporation An accelerated code optimizer for a multiengine microprocessor
KR101648278B1 (ko) 2011-11-22 2016-08-12 소프트 머신즈, 인크. 마이크로프로세서 가속 코드 최적화기 및 의존성 재순서화 방법
WO2013077876A1 (en) 2011-11-22 2013-05-30 Soft Machines, Inc. A microprocessor accelerated code optimizer
US8930674B2 (en) 2012-03-07 2015-01-06 Soft Machines, Inc. Systems and methods for accessing a unified translation lookaside buffer
KR20130119285A (ko) 2012-04-23 2013-10-31 한국전자통신연구원 클러스터 컴퓨팅 환경에서의 자원 할당 장치 및 그 방법
US9684601B2 (en) 2012-05-10 2017-06-20 Arm Limited Data processing apparatus having cache and translation lookaside buffer
US9996348B2 (en) 2012-06-14 2018-06-12 Apple Inc. Zero cycle load
US9940247B2 (en) 2012-06-26 2018-04-10 Advanced Micro Devices, Inc. Concurrent access to cache dirty bits
US9229873B2 (en) 2012-07-30 2016-01-05 Soft Machines, Inc. Systems and methods for supporting a plurality of load and store accesses of a cache
US9710399B2 (en) 2012-07-30 2017-07-18 Intel Corporation Systems and methods for flushing a cache with modified data
US9916253B2 (en) 2012-07-30 2018-03-13 Intel Corporation Method and apparatus for supporting a plurality of load accesses of a cache in a single cycle to maintain throughput
US9430410B2 (en) 2012-07-30 2016-08-30 Soft Machines, Inc. Systems and methods for supporting a plurality of load accesses of a cache in a single cycle
US9740612B2 (en) 2012-07-30 2017-08-22 Intel Corporation Systems and methods for maintaining the coherency of a store coalescing cache and a load cache
US9678882B2 (en) 2012-10-11 2017-06-13 Intel Corporation Systems and methods for non-blocking implementation of cache flush instructions
US10037228B2 (en) 2012-10-25 2018-07-31 Nvidia Corporation Efficient memory virtualization in multi-threaded processing units
US9195506B2 (en) 2012-12-21 2015-11-24 International Business Machines Corporation Processor provisioning by a middleware processing system for a plurality of logical processor partitions
US10275255B2 (en) 2013-03-15 2019-04-30 Intel Corporation Method for dependency broadcasting through a source organized source view data structure
US9632825B2 (en) 2013-03-15 2017-04-25 Intel Corporation Method and apparatus for efficient scheduling for asymmetrical execution units
US9904625B2 (en) 2013-03-15 2018-02-27 Intel Corporation Methods, systems and apparatus for predicting the way of a set associative cache
US9891924B2 (en) 2013-03-15 2018-02-13 Intel Corporation Method for implementing a reduced size register view data structure in a microprocessor
KR101800948B1 (ko) 2013-03-15 2017-11-23 인텔 코포레이션 레지스터 뷰, 소스 뷰, 명령어 뷰, 및 복수의 레지스터 템플릿을 가진 마이크로프로세서 아키텍처를 이용하여 명령어들의 블록들을 실행하는 방법
US9811342B2 (en) 2013-03-15 2017-11-07 Intel Corporation Method for performing dual dispatch of blocks and half blocks
WO2014150971A1 (en) 2013-03-15 2014-09-25 Soft Machines, Inc. A method for dependency broadcasting through a block organized source view data structure
EP2972845B1 (en) 2013-03-15 2021-07-07 Intel Corporation A method for executing multithreaded instructions grouped onto blocks
CN105247484B (zh) 2013-03-15 2021-02-23 英特尔公司 利用本地分布式标志体系架构来仿真访客集中式标志体系架构的方法
US9569216B2 (en) 2013-03-15 2017-02-14 Soft Machines, Inc. Method for populating a source view data structure by using register template snapshots
WO2014150806A1 (en) 2013-03-15 2014-09-25 Soft Machines, Inc. A method for populating register view data structure by using register template snapshots
US9886279B2 (en) 2013-03-15 2018-02-06 Intel Corporation Method for populating and instruction view data structure by using register template snapshots
WO2014150991A1 (en) 2013-03-15 2014-09-25 Soft Machines, Inc. A method for implementing a reduced size register view data structure in a microprocessor

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030035422A1 (en) * 2000-03-10 2003-02-20 Hill Alan M Packet switching
US20030169626A1 (en) * 2002-03-06 2003-09-11 Burk Wayne Eric System and method for controlling a number of outstanding data transactions within an integrated circuit
CN1214666C (zh) * 2003-04-07 2005-08-10 华为技术有限公司 位置业务中限制位置信息请求流量的方法
US20080256278A1 (en) * 2005-09-14 2008-10-16 Koninklijke Philips Electronics, N.V. Method and System for Bus Arbitration
US20090113170A1 (en) * 2006-04-12 2009-04-30 Mohammad A Abdallah Apparatus and Method for Processing an Instruction Matrix Specifying Parallel and Dependent Operations
US20080184211A1 (en) * 2007-01-26 2008-07-31 Nvidia Corporation Virtual architecture and instruction set for parallel thread computing
US20100088443A1 (en) * 2007-03-27 2010-04-08 Arm Limited Data processing apparatus and method for arbitrating access to a shared resource

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