JP4980751B2 - データ処理装置、およびメモリのリードアクティブ制御方法。 - Google Patents
データ処理装置、およびメモリのリードアクティブ制御方法。 Download PDFInfo
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- JP4980751B2 JP4980751B2 JP2007053127A JP2007053127A JP4980751B2 JP 4980751 B2 JP4980751 B2 JP 4980751B2 JP 2007053127 A JP2007053127 A JP 2007053127A JP 2007053127 A JP2007053127 A JP 2007053127A JP 4980751 B2 JP4980751 B2 JP 4980751B2
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- 230000015654 memory Effects 0.000 title claims description 38
- 238000000034 method Methods 0.000 title claims description 17
- 230000007704 transition Effects 0.000 claims description 11
- 238000010586 diagram Methods 0.000 description 19
- 238000001514 detection method Methods 0.000 description 16
- 230000000694 effects Effects 0.000 description 9
- 238000013500 data storage Methods 0.000 description 7
- 238000007796 conventional method Methods 0.000 description 5
- 230000004044 response Effects 0.000 description 5
- 230000003442 weekly effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3802—Instruction prefetching
- G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding
- G06F9/3806—Instruction prefetching for branches, e.g. hedging, branch folding using address prediction, e.g. return stack, branch history buffer
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0864—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using pseudo-associative means, e.g. set-associative or hashing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3802—Instruction prefetching
- G06F9/3814—Implementation provisions of instruction buffers, e.g. prefetch buffer; banks
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3842—Speculative instruction execution
- G06F9/3848—Speculative instruction execution using hybrid branch prediction, e.g. selection between prediction techniques
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/60—Details of cache memory
- G06F2212/6032—Way prediction in set-associative cache
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Description
ある。このプレディクションデータは、分岐命令の実行のたびに分岐(条件)の成立/不成立、すなわちTaken/Not Takenに対応してその値が変化する。その値は、分岐が成立した時には“1”が加算され、不成立の時には“1”が減算されるカウンタのカウント値に相当する。
S.McFarling:"Combining Branch Predictors",Technical Note TN−36,Western Research Laboratory(June 1993)
作成手段6から出力されるインデックスに対応して、分岐予測データ格納手段3から出力される分岐(条件)成立/不成立の予測データとメモリの予測データとを用いて、複数のメモリ1に対してリードアクティブ制御信号を出力するものである。
から出力され、キャッシュRAM210、211の中でタグアドレスに対応するエントリに有効な命令データが格納されていることを示すエントリ有効信号とが入力され、これらの入力信号がともに“H”である時に“H”が出力される。
C−missの状態に遷移する。またWeakly Takenの状態で分岐が成立し、かつ分岐命令のデータがキャッシュから読み出された場合には、WAY0、WAY1のいずれにヒットしたかが判明するので、その結果に対応した状態遷移が行われる。
ものとする。この分岐予測データは4サイクル目で出力され、その結果5サイクル目ではWAY1に対するリードアクティブ信号が“H”とされるが、WAY0に対するリードアクティブ信号は“L”のままとされる。
2 命令キャッシュメモリ
3 分岐予測データ格納手段
4 リードアクティブ制御手段
5 ヒット/ミス判定手段
6 インデックス作成手段
10 マイクロプロセッサ
11 外部ランダム・アクセス・メモリ
12 実行ユニット
13 命令キャッシュユニット
14 動的分岐予測器
20 命令アドレスレジスタ
21 キャッシュRAM
22 タグRAM
23 比較器
24 ブロック先頭検出部
25 ヒット/ミス判定論理回路
26 インバータ
27 セレクタ
28 ブランチ・ヒストリー・レジスタ(BHR)
29 排他的論理和演算器(XOR)
30 パターン・ヒストリー・テーブル(PHT)
35 リードアクティブ制御回路
Claims (2)
- nウェイの命令キャッシュメモリと、
分岐命令に対応するインデックスによって参照する分岐予測テーブルであって、各エントリに、2レベル分岐方向予測データと、前回の命令キャッシュヒット/ミスの情報と、該命令キャッシュヒット時のヒットしたウェイの情報とを統合してエンコードした状態ビットを格納する分岐予測テーブルを備え、
前記状態ビットは、2レベル分岐方向予測の「strongly taken」のステートを拡張して、「strongly takenであって前回C-miss」、「strongly takenであって前回WAY0でhit」、・・・「strongly takenであって前回WAYn-1でhit」のn+1個のステートとし、他のステート、即ち「strongly not taken」、「weakly not taken」、「weakly taken」と合わせて合計n+4個のステートに統合し、log2(n+4)ビット(整数に切り上げ)にエンコードして、分岐命令の実行結果(成立/不成立)と前記命令キャッシュのアクセス結果(ヒット/ミス、ヒット時のウェイ)によって状態遷移させるものであり、
また、前記状態ビットは、分岐方向がstrongly takenと予測する場合に、リードを必要とする命令キャッシュのウェイを予測し、strongly taken以外のステートではリードが必要となるウェイを予め決められた規則によって指示するものであり、
実行すべき命令が分岐命令である時、前記分岐予測テーブルの状態ビットに基づいて、必要とされるウェイに対してのみリード信号をアクティブに制御することを特徴とするデータ処理装置。 - nウェイの命令キャッシュメモリと、分岐命令に対応するインデックスによって参照する分岐予測テーブルであって、各エントリに、2レベル分岐方向予測データと、前回の命令キャッシュヒット/ミスの情報と、該命令キャッシュヒット時のヒットしたウェイの情報とを統合してエンコードした状態ビットを格納する分岐予測テーブルと、を備えるデータ処理装置のメモリのリードアクティブ制御方法であって、
前記状態ビットは、2レベル分岐方向予測の「strongly taken」のステートを拡張して、「strongly takenであって前回C-miss」、「strongly takenであって前回WAY0でhit」、・・・「strongly takenであって前回WAYn-1でhit」のn+1個のステートとし、他のステート、即ち「strongly not taken」、「weakly not taken」、「weakly taken」と合わせて合計n+4個のステートに統合し、log2(n+4)ビット(整数に切り上げ)にエンコードして、分岐命令の実行結果(成立/不成立)と前記命令キャッシュのアクセス結果(ヒット/ミス、ヒット時のウェイ)によって状態遷移させるものであり、
また、前記状態ビットは、分岐方向がstrongly takenと予測する場合に、リードを必要とする命令キャッシュのウェイを予測し、strongly taken以外のステートではリードが必要となるウェイを予め決められた規則によって指示するものであり、
実行すべき命令が分岐命令である時、前記分岐予測テーブルの状態ビットに基づいて、必要とされるウェイに対してのみリード信号をアクティブに制御することを特徴とするメモリのリードアクティブ制御方法。
Priority Applications (3)
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JP2007053127A JP4980751B2 (ja) | 2007-03-02 | 2007-03-02 | データ処理装置、およびメモリのリードアクティブ制御方法。 |
US12/040,269 US8667259B2 (en) | 2007-03-02 | 2008-02-29 | Data processor and memory read active control method |
CN200810083121.1A CN101256481B (zh) | 2007-03-02 | 2008-03-03 | 数据处理器以及存储器读激活控制方法 |
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JP2007053127A JP4980751B2 (ja) | 2007-03-02 | 2007-03-02 | データ処理装置、およびメモリのリードアクティブ制御方法。 |
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JP2008217353A JP2008217353A (ja) | 2008-09-18 |
JP4980751B2 true JP4980751B2 (ja) | 2012-07-18 |
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JP2007053127A Expired - Fee Related JP4980751B2 (ja) | 2007-03-02 | 2007-03-02 | データ処理装置、およびメモリのリードアクティブ制御方法。 |
Country Status (3)
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US (1) | US8667259B2 (ja) |
JP (1) | JP4980751B2 (ja) |
CN (1) | CN101256481B (ja) |
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2008
- 2008-02-29 US US12/040,269 patent/US8667259B2/en not_active Expired - Fee Related
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Publication number | Publication date |
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US8667259B2 (en) | 2014-03-04 |
JP2008217353A (ja) | 2008-09-18 |
CN101256481A (zh) | 2008-09-03 |
US20080215865A1 (en) | 2008-09-04 |
CN101256481B (zh) | 2015-07-08 |
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