CN107368285B - 多线程架构 - Google Patents
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Abstract
本申请涉及用于处理使用上下文切换的多线程架构中的指令的装置和方法。用于复杂指令格式的动态生成、执行、同步以及并行的统一架构包括虚拟寄存器文件、寄存器缓存以及寄存器文件层级。自生成和同步动态和静态线程的架构提供了高效的上下文切换。
Description
本申请是国际申请号为PCT/US2007/084710,国际申请日为2007/11/14,进入国家阶段的申请号为200780046679.6,题为“多线程架构”的发明专利申请的分案申请。
技术领域
本发明主要涉及数字电路。更具体地,本发明涉及改进的处理器设计。
背景技术
处理器需要过程相关的或者完全独立的多个任务。这种处理器的内部状态通常由寄存器集成,所述寄存器在程序执行的每个特定的时刻处可以具有不同的值。在程序执行的每个时刻处,将内部状态的图像称为处理器的架构状态。
当切换代码执行来运行另一个子例程(function)(例如,另一个线程、过程或者程序)时,则必需保存机械/处理器的状态,以便新的子例程可以使用内部寄存器来建立其新的状态。一旦新的子例程终止,则可以放弃其状态,并且恢复到之前上下文的状态并继续执行。将这种切换过程称为上下文切换,并且该过程通常包括特别是具有现代架构的几十个或者几百个周期,所述现代架构采用大量的寄存器(例如,64,128,256)和/或乱序执行。
在线程感知(thread-aware)硬件架构中,硬件一般支持有限数量的硬件支持的线程的多个上下文状态。在这样的情况下,硬件复制每个支持的线程的所有架构状态要件。当执行新的线程时,这不需要上下文切换。然而,这还是有多个弊端,即:复制在硬件中支持的每个额外的线程的所有架构状态要件(即,寄存器)的区域、能量、以及复杂度。此外,如果软件线程的数量超过明确支持的硬件线程的数量,则必须还是要进行上下文切换。这是因为基于精细度的并行往往需要大量的线程。对上下文状态的硬件存储进行复制的硬件线程感知架构无助于非线程的软件代码,并且只能为线程化的软件减少上下文切换的次数。然而,这些线程通常构建为粗粒度并行,并且导致初始和同步离开诸如子例程调用和循环并行执行之类的细粒度并行的沉重的软件开销,而无法进行高效的线程初始/自动生成。如此描述的开销使得使用现有技术的编译器来自动并行化这种代码困难,或者针对不明确的/易并行化的/线程的软件代码的用户并行化技术困难。
发明内容
用于复杂指令格式的动态生成、执行、同步以及并行的统一架构包括虚拟寄存器文件、寄存器缓存(register cache)以及寄存器文件层级。自生成和同步动态和静态线程的架构提供了高效的上下文切换。
附图说明
结合附图通过下面的详细描述,可以更加全面地理解本发明,在附图中:
图1示出了使用到寄存器文件的直连的寄存器状态的即时保存和恢复;
图2示出了根据本发明实施例的具有寄存器位置映射的虚拟寄存器文件;
图3示出了根据本发明实施例的具有用于推测的寄存器状态的临时存储装置的多个层级的寄存器文件;
图4示出了根据本发明实施例的用于对软件的上下文/线程进行虚拟化的寄存器缓存;
图5示出了根据本发明实施例的具有在上下文切换时溢出和重载寄存器的自动机制的寄存器缓存;
图6示出了根据本发明实施例的使用计数器模式的寄存器名称的错误相关性的方案;
图7示出了已知的超标量执行架构;
图8A示出了根据本发明实施例使用的执行架构;
图8B示出了根据本发明实施例的缓存、调度器以及存储继承信息的重排序单元;
图9A示出了根据本发明实施例的用以在跨一组核心的线程之间实施顺序一致性的全局前端和继承向量;
图9B示出了根据本发明实施例的允许跨核心的线程间和线程内的寄存器通信的寄存器互连拓扑;
图9C示出了根据本发明实施例的跨物理分段式架构的统一寄存器文件的基于位置的寄存器引用;
图10示出了根据本发明实施例的自动生成越过循环迭代和边界的线程的机制;
图11A示出了根据本发明实施例的自动生成跨越控制路径的线程的机制;
图11B示出了根据本发明实施例的测试和分支指令处理;
图12示出了根据本发明实施例的使用的具有单独标签和数据阵列的分段式/分布式缓存;
图13A示出了支持预取指令和其加载消耗指令之间的精确调度的映射机制;
图13B示出了根据本发明实施例的通过虚拟化硬件存储的到物理存储的Temp和Chain的动态分配;
图14示出了根据本发明实施例使用的在无需额外的物理寄存器的情况下使地址寄存器能够重新命名的调度器向量中的计数器机制;
图15示出了根据本发明实施例实施的绕过和检查机制。
在各个附图中,相似的附图标记指代相对应的部分。
具体实施方式
本发明的一个方面减小了上下文切换所带来的麻烦。由于保存架构状态(例如,数据寄存器、控制寄存器、程序计数器等)耗费时间,因而上下文切换带来了麻烦。在继续进行执行之前不得不恢复之前的上下文的状态。这意味着大量寄存器的许多加载/存储的出现有时就如同涉及的子例程调用一样常见。公开的架构状态的结构在架构状态上进行逐步的自上下文切换以及即时上下文切换。同样,引入虚拟寄存器文件和寄存器缓存的概念作为可能的实施组件。相比可能使用传统的硬件线程的支持来说,虚拟寄存器文件或者寄存器缓存还可以提供硬件中对虚拟的更大数量的线程或上下文的支持。多个层级的寄存器文件支持为寄存器文件提供更大的带宽。
还可以将该技术与线程支持相结合。架构状态的一部分将会经历即时硬件/软件支持的上下文切换,在所述上下文切换中,通过使用LIFO(后进先出)电路的硬件,来快速地/即时地保存所有架构状态。相对于寄存器文件或者随机存取存储器的实施,LIFO电路的使用允许更低的复杂度和高效的速度和区域的实现。将属于该类的每个接下来的上下文切换保存在LIFO中的旧的上下文切换的上面。这个技术非常适合递归式的子例程调用或者嵌套的并行循环,其中,在递归中的一个调用的上下文将会以LIFO的方式自然地进入和离开。图1示出了硬件上下文切换支持的一个实施例。
对架构状态进行这种快速保存的另一种方式是将寄存器文件的内容保存为存储器或缓存中的一个块(例如,一个缓存行或块)。一个寄存器批组为一系列后续的寄存器号码(例如,寄存器0到7可以为更大寄存器集0-64的子组),当出现涉及这8个寄存器的上下文切换时,可以将该一系列后续的寄存器号码存储为64字节大小的一个缓存行。相对于通常使用加载和存储来保存和恢复每个个别寄存器来说,寄存器文件具有在同一周期或少量周期中直接运送其所有内容的专门的宽总线101和102。寄存器文件的缓存传送的一个可能的实施是使用总线102和101来连接到填充缓冲区,所述填充缓冲区一般用来填充缓存行以作为后门路径来将寄存器直接移动到缓存。一个可选的实施可以使用写入/读取结合缓冲区,所述写入/读取结合缓冲区通常用来在部分数据作为简单事务而通过总线写到存储器之前,将它们存储和加载积累到缓冲区,而不是每个均形成部分总线事务。这种结合缓冲区可以具有经由101和102的侧门总线连接,用以将一系列寄存器结合到一个写入结合缓冲区,所述写入结合缓冲区随后可以将寄存器的整个缓存行的值传送到缓存或者存储器中,同时可以使用读取结合缓冲区来进行相反的传送。在另一个实施中,可以选择使用具有LIFO电路或者随机存取存储器缓冲区的专门局部存储器。LIFO电路更为简单,并且具有更少的实施限制,但却实行了严格的保存和恢复数据的顺序(后进先出)。另一方面,诸如对处理器缓存使用直接总线之类的随机存取存储器具有使用局部存储器的灵活性,但却实行了硬件实施限制,而允许以随机的顺序灵活地保存和恢复上下文。
当新的上下文取代旧的上下文时,可以逐步地保存和恢复架构状态的另一部分。换句话说,在新的或旧的上下文中使用个别寄存器时,由硬件来交换进和交换出/读进和读出该特定寄存器。这种逐步的上下文切换适合全局变量和通过上下文切换从一个子例程传送到另一个子例程的变量。它还适合当循环线程化时通过嵌套循环来传送的那些变量,这样,将内部循环指定给与外部循环不同的线程。还可以应用到下面的情况:其中,将循环的不同迭代指定给不同的线程并且这些迭代将各个变量从一个迭代传送到其它迭代(循环带来的相关性)。在所有的这些情况中,对寄存器进行逐步上下文切换是有益的,这是因为一般在线程之间使用的寄存器(在上下文之间传送数据的寄存器)的数量很大,因此可以共享那些寄存器并且不需要进行上下文切换,而剩下的寄存器可以逐步地按需进行交换。
本发明还可以使用虚拟寄存器来允许容纳比由指令集的架构直接支持的寄存器集更大的寄存器集。额外的寄存器成为硬件支持的上下文切换或者硬件/软件线程的部分。寄存器缓存或者寄存器层级的概念也适用于这样的情形。虚拟寄存器文件是一种如下的寄存器文件架构:其中,通过使用虚拟寄存器文件存储装置,来扩展对架构可视的指令集寄存器并且对架构始终可视。这便于对属于不同上下文切换或线程的相同架构的寄存器保留多个拷贝。这也使得具有比使用传统物理寄存器文件直接可访问的寄存器数量更多的或者可变的寄存器数量。在硬件正在生成线程/上下文(硬件线程)的情况中,结构寄存器的那些拷贝对硬件是可视的,并且当软件正在生成线程/上下文(软件线程)时,它们还可以用软件线程进行过载。
图2示出了通过使用寄存器文件的层级的这样的虚拟寄存器文件的一个实施例。较低层级级别的201为执行单元支持非常高的带宽。较高层级级别200支持较低带宽的访问。寄存器文件层级的一些级别包含由指令集的架构支持的基本寄存器集,而寄存器文件层级的其它级别包含基本寄存器集的虚拟拷贝。还可以允许复制基本寄存器集以支持多线程。
还可以在该层级中包括寄存器缓存,在所述寄存器缓存中,基于寄存器对当前上下文的关联性以及它们立即访问的需要,来将这些寄存器缓存到这些结构中或者从该结构中缓存出。实施这种虚拟寄存器文件和寄存器缓存的一种方式是给寄存器位置提供标签以便通过标签来访问它们,所述标签包括实际的寄存器号码以及额外的其它信息,例如:上下文ID号码或者静态线程号码和可能的存储器地址,在所述可能的存储器地址中,为上下文切换而保存它们。其他可选的技术同样于此描述,其中,索引映射202使用关于每个结构寄存器的基于位置的信息。将在层级中的寄存器拷贝的位置(地点)作为寄存器文件203的寄存器读取访问的解码阶段的部分进行查找。其它机制包括将寄存器的位置作为从寄存器的产生指令到其消耗指令的计分牌(score board)机制的部分来进行传送。消耗指令需要读取寄存器以便它们知道它们需要去访问该结构寄存器的哪个拷贝,但是在基于位置/地点的方案中,由于寄存器的访问是通过其寄存器号码和位置来进行的,所以不需要标签,其中,将特定的寄存器拷贝物理地位于多层级寄存器文件中的该寄存器的多个拷贝当中。
逐步上下文切换的机制可以使用类似的机制来对当前上下文切换进行个别寄存器的保存和恢复,但具有以下不同。当新的上下文试图使用个别寄存器并且局部拷贝属于旧的上下文时,该个别寄存器是由硬件交换/读取的。此时,将属于旧的上下文的寄存器与带入到局部寄存器文件201的属于新的上下文的200中的全局寄存器拷贝进行交换。在一个实施中,具有相同寄存器号码但不同的上下文ID标签的多个寄存器可以共存。标签方案的一个实施例可以类似于呈现来自不同上下文的相同寄存器的虚拟寄存器文件。虚拟寄存器文件是值得引起注意的,因为它允许大的虚拟寄存器文件被实施为具有不同带宽和容量变化的多级寄存器文件的层级。下面的示例示出了呈现子例程的不同情形。假设随后调用在单一程序/任务内的不同子例程调用。
Function 1(values,references)
{
a-d:local variables
X-Z:global variables
Code
}
Function 2(values,references)
{
a-d:local variables
X-Z:global Variables
Code
}
Function 3(values,references)
{
a-d:local variables
X-Z:global variables
If(condition)then call Function 3()
}
Main{
Function 1()
…
Function 2()
Function 3()
…
}
如果不需要旧的上下文,则需要将局部寄存器文件中的旧的局部变量作为一个整体来保存,此处使用上下文即时保存是有意义的,需要保存整个上下文的其它情况为操作系统调用新的独立过程的时候。
另一方面,如果不需要保存所有的旧的上下文的寄存器,则只将需要保存的那些与新的上下文寄存器的值进行逐步交换。这是子例程1和2一起共存于同一局部寄存器文件中并且在全局寄存器文件中共享相同的全局寄存器的情况。这是针对细粒度线程的情况。在这样的情况中,当需要访问特定的上下文中的特定寄存器时,将它的上下文ID与在局部寄存器文件中存在的那个进行核对。如果它们匹配,则可以使用它,否则需要从(诸如全局寄存器文件或者寄存器缓存之类的)更高的存储层级中带来/读取它,并且可以与在局部层级存储(例如,临时局部寄存器)中的进行交换。
在子例程的调用处,将写在子例程作用域(scope)之内的新的变量指定给(具有与子例程外部作用域相比而言新的上下文/线程ID的)新的寄存器拷贝。可以通过硬件管理单元(HMU)或者通过为该架构生成代码的编译器/程序设计器来指定那些新的寄存器名称的拷贝。在HMU的情况中,进入子例程代码(调用和返回指令之间的一个)时,HUM单元将新的上下文/线程ID号码指定给写在子例程作用域之内的每个寄存器名称,从而生成寄存器名称的拷贝。当到达返回指令时,该上下文/线程ID变为空闲以重新指定并且所有的寄存器名称的拷贝可以再一次重新使用。由于硬件自动地管理寄存器名称的这些临时拷贝的指定和释放,所以在创建和同步这些临时上下文中没有开销。
当指令架构允许使用上下文/线程ID号码来扩展寄存器名称时,编译器可以在不同的上下文中操纵寄存器名称的管理。将指令写进具体寄存器名称的这种方式也指明了指令写给的和指令从其上进行读取的上下文/线程。考虑具有3个源(S1,S2,S3)和一个目的地(Dest)的一般指令作为下述编码:
Dest/S1←ADD(S2,S3)
在这个示例中,将寄存器和其对线程的关联格式化为:
Thy:Rx←ADD(Thz:Ri,Thw:Rk)
这示出了指令架构如何允许指明上下文/线程ID,即Thy(其中y表示线程ID)和具有寄存器名称x的寄存器Rx的关联。编译器和程序设计器可以指明寄存器名称所属于的上下文/线程号码。当编译了子例程代码时,编译器可以使用专门指令来增加线程ID计数器,以增加上下文/线程ID号码;当使用减少指令来退出子例程调用时,则减少该计数器。指令架构可以使用的另一个机制是实施空闲线程选择器指令。编译器/程序设计器使用该指令来轮询硬件以找到其可以使用的空闲上下文/线程ID。当从子例程返回时,它可以使用诸如上下文/线程空闲指令之类的另一个指令。下面示出了这两个方法。
增加线程ID计数器
Function A:((Th+:Ry←Move Th:Ry)
{
Function body
}
Return(Th-:Ri←Move Th:Ri)
减少线程ID计数器
在子例程调用之前进行增加和在返回之后进行减少的原因是允许在调用方和被调用方之间传送值。增加创建新的上下文/线程号码而减少则释放它。
执行相同任务的可选方法使用了选择空闲的上下文/线程号码的指令和释放该上下文/线程号码的另一个指令。
J=当前线程号码
I=选择空闲的线程ID号码
Function A:(Th{I}:Ry←Move Th{J}:Ry)
{
Function body
}
Return(Th{J}:Rx←Move Th:Rx)
Free thread ID number{I}
为了减少与每个寄存器名称相关联的上下文/线程号码的编码空间,指令架构可以指明:将寄存器与父线程或者当前子线程相关联;这可以用一位来编码(我们将父/子位称为:“P/C”位)。每个新生成的线程将指明其父线程(用过的线程)。将父ID号码与其他线程状态保持在一起。可以使用混合方案,在所述混合方案中,指令可以指明来自使用父/子位的当前子或父线程的一个/多个源,和来自使用明确的线程号码和该源的寄存器名称的另一个不相关的线程的一个/多个源。下面的指令集的架构示出了这种混合方案:
P/C:Rx←ADD(P/C:Ri,P/C:Rj,Thw:Rk)
“P/C”位指明寄存器是否属于父线程或者子线程。可以一般化这个方案,其中,可以在更高级别的上下文之内指定更多位来对活动线程进行编码。接下来示出这个更加一般的方案。高级别的上下文在其状态内定义很少的线程。处理器架构允许可以由指令集缩减的小规格存储状态。假设处理器硬件可以支持总共N个线程,则指令集可以支持这些线程的缩减,这使得M个线程在指令集编码中通过寄存器进行相互通信,其中M<N。这将使得由指令集的架构支持的线程数量大于经缩减的编码位允许的线程数量。例如,假设硬件可以支持128个线程(N=128)。可以将指令集编码定义为只具有4个线程(M=4)的编码,这样,可以由128个线程当中的4个活动线程来同时访问那些线程的寄存器。根据程序的活动区,该4个编码可以在128个线程当中轮换。可以使用很少的位(T1…Tlog M)来在指令中编码M个线程。在本示例中使用2位T1T2来编码4个线程。
T1T2:Rx←ADD(T1T2:Ri,T1T2:Rj,Thw:Rk)
可以将程序区内的活动线程映射到由硬件支持的线程的所有组,下面示例性示出映射或者指定指令:
Map(T1T2=00),TH=0001101
Map(T1T2=01),TH=1001000
Map(T1T2=10),TH=1010101
Map(T1T2=11),TH=0111100
01:Rx←ADD(01:Ri,10:Rj,1000110:Rk)
在上面代码的示例中,指令将硬件线程映射到由映射指令的2位T1T2表示的经缩减的编码。经由示例,添加的指令为每个源和目的地的线程编码为只2个经缩减的位。然而,第三源明确地编码其源的线程。在指令集中编码以缩减线程而对位数的决定,是可以从一个架构变化到另一个的实施决定,同样,包括第三源或者具有其所明确编码的线程也是实施的选择。
为了实施这种指令或微操作(指令的微代码实施)的处理器的流水线,该流水线将存储这些映射,并且当处理器执行指令以编码经缩减的线程位时,使用这些映射来访问正确的线程状态。这些映射状态可以扩展寄存器分配算法以将单一线程变量映射到寄存器,其中编译器可以将更大的线程组分配给有限数量的映射状态,并且随后在每个线程之内进行寄存器分配。通过使用与寄存器的生命范围相类似的线程的生命范围,这种方式可以将映射状态在程序中重新分配给新的线程。
如果该处理器为乱序处理器,则它还可以允许对那些缩减映射进行重新命名以允许更多的那些主动区线程同时执行。例如,在这种乱序处理器中,将会解码上面的代码,来将实际微操作编码内部的那些经缩减的位重新命名为完整的线程号码。在这种乱序的机器中,还实施临时推测寄存器来保留那些重新命名的寄存器和状态。图3实施了临时寄存器,其中,在将诸如301之类的临时存储器交调拨给全局寄存器文件之前,推测状态可以位于临时寄存器中。
所描述的一般方案使细粒度线程能够无需通过存储器而在寄存器级别执行上进行通信、协作、和同步执行,而在同时具有通过给线程提供寄存器关联而极度紧密的指令集编码,并减小了指令编码空间。上面描述的所有方案需要编译器插入指令以管理线程并且设置扩展位,这可以由硬件管理单元来进行,所述硬件管理单元对指令执行类似的动作和管理这些扩展位的设置(如通篇本文所描述的那样)。
我们一般化上面的机制来操纵超出子例程调用的细粒度线程,以包括跨循环边界的线程并在循环体和循环体之外的代码之间创建的线程。考虑下面的代码:
Loop(j=1to 100)
{
Instruction A
Instruction B
Loop(j=1to j)
{
Instruction 1
Instruction 2
}
Instruction C
}
通过使用编译器或者硬件管理单元,可以将表示内部循环体的线程(指令1和2)和表示内部循环体之外的指令的线程映射为硬件支持的线程。
经由示例,在下面的实施表示的一个方案中,可以使那些细粒度线程位于寄存器文件/寄存器缓存中,并且可以交换进和交换出到更高级别的寄存器文件层级和存储器层级。假设,将编译器设计为使用一些规范,所述规范依靠在被调用的子例程中使用的寄存器的数量来保存上下文。因此它可以以增加的方式来保存若干寄存器。例如,如果设计规范以8为增量使用寄存器批组,则当子例程需要使用在1和8个寄存器之间的若干寄存器时,其将会保存旧的上下文的寄存器1到8(并且当它恢复旧的上下文时恢复它们)。如果子例程需要使用在1和16个寄存器之间的若干寄存器时,则它将会保存寄存器1至16等等,以完整的程度保存由架构支持的全部寄存器。允许建立虚拟寄存器文件的另一个方案是,对不同的上下文/线程的寄存器进行混叠(aliasing),其需要比由指令架构提供的寄存器数量更少的寄存器。例如,小子例程调用或者工作线程可能只需要使用所有寄存器的子集,例如,指令集可使用的32个寄存器当中的8个寄存器(寄存器0到7)。如果是这种情况,则硬件/编译器将这8个逻辑寄存器批组混叠在另一个空闲的物理寄存器批组的上面,线程映射到的寄存器批组不需要和相同的寄存器号码在一起;即,可以将寄存器0-7映射到在另一个上下文物理状态存储中可使用的物理寄存器8-15或16-23或24-31上。
图4示出这样的情形。将由寄存器0-7组成的线程5的状态402混叠在空闲的物理寄存器批组8-15的上面。这意味着可以比将每个线程映射到全部32个寄存器状态上的一般情况容纳更多的线程。在图4中,由于32个寄存器中只有4组可以同时使用,所以一般只有4个线程可以在同一时刻共存。然而如果大多数额外线程(除了自身可能需要32个寄存器大状态的主线程之外)需要小组寄存器,并且它们的每个均可以和8个寄存器小状态共存,则可以同时处理总共13个线程。可以在这8个寄存器批组的混叠配置中共存的同时线程的最大数量是16个小状态线程。显然,我们不需要为了示例性的目的而像图中所示出的那样存储每个寄存器的标签。在高效的实施中,可以存储每个批组(在本示例中8个寄存器)的线程标签,或者可选地可以根据号码混叠方案来分配线程,在所述号码混叠方案中,线程的号码在8的倍数的边界处开始。例如,如果我们基于这个方案来开始分配寄存器,则图4示出软件线程号码0、1、3、4、5、6、7和9。如上面所描述,(经由编译器)通过指令集或者通过硬件管理单元来将软件线程映射给物理硬件线程。混叠方案现在允许将16个硬件线程映射到软件线程。在这样的情形中,软件线程0保留硬件线程0、1、2和3,因为它需要全部32个寄存器大状态,并且因此使用8寄存器的4个批组中的每一个。然而,软件线程1只保留一个小状态硬件线程存储并因此映射在硬件线程4上。将软件线程5映射到硬件线程5上,将软件线程3映射在硬件线程6上并且将软件线程6映射在硬件线程12上(在图中示出为点400)。
在指令集或微指令编码中,为了支持上面描述的混叠方案,对线程-寄存器对的引用(reference)可以是位的连续编码,其中,顶上的4位为硬件线程号码(指示了8个寄存器的哪个批组被线程引用),而较低的3位指示寄存器批组0-7中的个别寄存器。
作为示例,假设软件需要进行接下来在不同的线程中添加特定寄存器的高级别线程的任务,并且将结果写进软件线程1的寄存器2中,如图4中的403所示如下:
Th1:R2←ADD(Th0:R13,Th3:R2,Th6:R3)
随后,通过编译器或者硬件管理单元来将软件线程映射到硬件线程。这种映射确保需要超过8个寄存器的软件线程保留不止仅一个硬件-线程存储,因而其他的软件线程不能使用那些保留的硬件线程来映射到其上。任务的实际指令编码如下:
0100010←ADD(0001101,0110010,1100011),其解码如下:
HWTh4:R2←ADD(HWTh1:R5,HWTh6:R2,Th12:R3)
注意,由于将软件线程的映射混叠在4个小状态线程0、1、2、3上,其中的每个具有只8个寄存器的批组,所以将软件线程0寄存器13编码为硬件线程1(401)寄存器5(0001101,前4位为硬件线程号码而后3位为寄存器号码)。可选地,可以将相同的编码读作硬件线程0寄存器13(00 01101,前2位为大状态硬件线程号码(具有32个寄存器状态),而后5位为32个寄存器当中的寄存器号码)。
如图所示,可以在之前寄存器缓存方案上面实施的另一个方案在这个寄存器缓存和存储器缓存之间提供自动存储加载机制,以当上下文切换和线程上下文交换时,允许寄存器缓存自动地溢出和重新加载寄存器。
下面代码示出了方案、以及图5中描述的硬件如何工作来允许无缝多线程的上下文切换。(类似于一般与组和方式相关联的缓存而建立的)寄存器缓存具有牵引部分、标签阵列和数据阵列。对数据阵列的访问类似于对任何线程的寄存器阵列的访问;当任何指令访问该线程寄存器时,进行寄存器读取。然而,当任何加载或存储指令是上下文切换的一部分时,对标签阵列进行访问,这也被认为是保存和恢复上下文。当存储的寄存器的当前线程上下文(保存上下文)实现,由于在寄存器文件缓存中的那个特定寄存器集中仍具有闲置的空间,因而不需要将值实际地存储到存储器上的时候,针对该特定寄存器,使用当前堆栈存储器地址来只更新寄存器缓存的标签部分。稍后,当在寄存器缓存中没有空闲的空间来存储需要分配相同寄存器名称的新的线程时,使用这个标签来实际地收回寄存器。下面代码示出这些:
在上面代码中,编译器希望将由线程1、4和6重写的线程0的寄存器R0到R7,保存到存储器堆栈上。在这个方案中,分配堆栈中的存储器区域来容纳寄存器批组(0-7),但是当线程1、4和6相遇时,硬件没有真正地进行将线程0的寄存器存储到存储器/存储器缓存。这是因为多上下文的寄存器文件缓存能够将存储501提供给那些线程所需的额外8个寄存器(0-7),而没有破坏原来线程(线程0)的寄存器0-8。只要多上下文的寄存器文件缓存可以容纳那些寄存器,它就使用由存储指令意图执行的堆栈存储器地址来只更新寄存器缓存中的标签阵列。注意当遇到线程8时(“子例程foo”),因为寄存器缓存的空间都为寄存器批组0-7占据,所以必需进行线程0的寄存器0-7的存储,并且事实上这类似于在一般缓存中的收回过程,其中,将线程0的寄存器0-7收回到实际堆栈存储器/缓存层级存储500,而寄存器文件缓存在这之后在存储区域502中包括线程8的寄存器0-7的值。
对上下文切换的机制还可以促进诸如动态自生成和线程同步之类的其他技术。单一任务或程序的不同部分的并发执行当前需要乱序“超标量”处理器架构的实施。然而,乱序执行需要相当大的硬件投入和复杂度。下面是使用了乱序微架构的这种并发执行所需要的一般性的实施组件:
1.分配逻辑,其以程序的序列顺序来分配所有资源。
2.重新命名逻辑和寄存器映射,其将逻辑寄存器映射处分配处的物理寄存器,并且在物理寄存器的退回(retirement)处更新逻辑寄存器。
3.保留站,其根据资源的可用性并且在动态解决相关性之后来乱序地分派操作。
4.重排序缓冲区,其允许将所述结果退回到架构状态之前,以初始的序列顺序对结果重新排序。所述重排序缓冲区还保持精确异常行为。
5.存储器重排序缓冲区,其对乱序分派的存储器访问进行重新排序,以保持相同一致的模式就如同它们按顺序分派一样,例如,在存储到相同地址之后对加载进行检查。还有必要像存储器映射的I/O一样来为专门寄存器访问保持访问的顺序。
很少的架构能够利用乱序机器的超标量的特性和它们的能力来分派指令的多个独立流,以允许多个软件线程在机器中同时地执行。这个同时多线程需要为每个硬件支持的线程复制机器的架构状态,并且分割线程之间的微架构资源,并且共享存储器结构就像那些线程之间的缓存一样。尽管事实是那些机器是乱序的,但它们并不由乱序硬件本身来在线程之间初始、自分派、同步或者进行并发。于此形成对比,将所有的那些任务留给软件,当(例如,通过使用界限)满足了线程的分派条件/相关性时,由软件初始/生成并且分派那些线程。当线程之间具有集中控制或相关性时,软件(例如使用锁定)同步它们。软件还决定它们之间的并发性。前面提及的软件可以为实际主线程编码或者为试图静态地并行化非线程代码的编译器。由于自动并行化这些代码的困难度,通常可以使用粗粒度并行来实施这些线程,而使细粒度并行没有高效线程初始。
下面的论述示出了,通过使用硬件/软件的新的示例,即使没有使用精细的乱序微架构支持,也可以实现自动并行化。通过动态地检测对控制条件和/或相关性的解决,并且/或者通过允许线程之间的寄存器的交叉引用,还通过消除跨线程的存储器引用的歧义,新的硬件生成、同步、并行化、并且并发地执行那些细/粗粒度静态和动态线程。通过硬件监视与触发线程相关联的控制条件,或者监视当前线程所依靠的交叉引用的寄存器的值的回写来实现。
当所有线程相关的寄存器和/或控制条件,特别是交叉引用特性的那些(例如,线程间寄存器)满足时,触发了通过硬件来动态地初始/生成线程。这可以通过该线程所依靠的源的明确列表来监视。可以将这些硬件初始的动态线程看作,或者实际地作为子例程调用、或者以重复的子例程调用的形式封装(encapsulate)的方法或者子程序或者甚至循环实例。该子例程调用具有其执行所依靠的参数列表。监视这些参数列表或者寄存器中出现的它们的回写阶段的。一旦每个参数/寄存器在其更新的指令执行之后被回写,则设置标志。当设置了这些参数/寄存器的所有标志时,则由硬件来动态地分派子例程/线程。对在(硬件生成的和软件生成的)不同线程之间的寄存器或虚拟寄存器的交叉引用和/或存储器的引用的允许,通过使用自然相关的解决方法,例如用于通过使用寄存器来创建程序的一致执行,以对相关性进行通信的方法等,来建立一种方式来生成、同步、并行化、以及并发地执行那些线程。
上面提及的缓慢逐步上下文切换还帮助允许通过使用如上面所示出的其他存在的动态/静态线程,来建立/交换那些动态生成的或软件静态的线程的新的状态。
图6示出了在那些线程的动态执行期间,对相同名称的寄存器解决错误相关的一个可能的机制。这还可以通过给寄存器号码增加在机器中的指令分配时刻用标签标记以示区分的位字段,来保持寄存器更新的序列顺序。在前端处,每个寄存器具有对应于该位字段的2个计数器的值。在将该寄存器作为指令的目的地的每个新指定处增加一个计数器的值(领先计数器)601。在将对应寄存器调拨给架构状态的每个调拨处增加另一个指针602(滞后计数器)。滞后计数器永远不会超过领先计数器。领先计数器可以在到达最大值之后,环绕到初始的值;滞后计数器具有相同的功能。可以将这些计数器扩展到具体的线程,这样每个线程拥有自己的计数器。
当相同寄存器的新的时刻作为目的地指定给新指令时,特定寄存器的领先计数器601持续增加。每次在将寄存器作为目的地来重新指定给新分配的指令603时,(在机器的前端中)增加该寄存器的位字段,并且将该位字段附着到硬件指令605上。使用这个寄存器作为源606的每个接下来的指令将会使用新增加的寄存器号码的扩展字段。当该寄存器调拨给最终的架构状态的时候,则增加在前端处的该寄存器的位字段的滞后计数器602。使用和增加滞后计数器的原因是,(在指令寄存器读取阶段)通过将硬件指令的寄存器的扩展字段,与来自滞后计数器指针的那个寄存器的滞后计数器作比较,来判断特定的寄存器的值是否需要从推测重排序缓冲区或者从退回的寄存器文件中读取。滞后计数器602在退回流水线阶段604处增加。该机制还可以应用到个别指令,并且不限于子例程的调用或线程。
可以使用继承向量来取代图6中示出的领先计数器和滞后计数器表,所述继承向量具有针对每个结构寄存器的字段。在分配时刻,该向量将增加的值从每个指令转发到下一个,而每个指令增加与其目的地寄存器相关的位字段中的值。在图8.a/8.b中示出了类似的概念,区别是针对一组指令而非仅一个指令。
在下面的段落中,描述优选的方法,来随同上面描述的上下文切换的操纵一起,来对自动/动态线程的生成和同步进行统一。此外,披露了物理-分段-架构-统一的寄存器的概念和非常适合于这个实施例的寄存器层级。
架构还可以包括指令矩阵/块/桶架构(可更换地使用矩阵、块或者桶),其中,指令是超大指令矩阵(Ultra Large Instruction Matrix)的部分,请参见同一发明人的申请号为PCT/US2007/066536的先前发明来了解作为“ULIM架构”的所述超大指令矩阵,通过引用的方式将该申请包含在本文中。指令矩阵/桶/块是指令的集合,其可以完全地相互相关或者完全地独立或者介于二者之间(一些指令依靠其他指令,而一些指令相对于其他指令独立)。通常指令矩阵/块以矩阵的格式来封装指令,在所述矩阵的格式中,相关的指令必须占据矩阵之内的一列,而独立的指令占据行或者列。可以从将架构映射给其硬件执行单元的少数可能的配置中选择矩阵的维(行、列)。矩阵/块/桶架构的概念允许代替个别源而在指令块/桶本身的级别上来传送相关性。因而,架构高效地移除了与CAM(内容可寻址的匹配)相关联的复杂度,所述CAM在大标量并发指令执行架构中匹配源和目的地。可以在没有明确的使用ULIM架构或者甚至指令桶/块下,通过使用替代的虚拟标识符,来设计本发明,所述虚拟标识符提供与块/桶相类似的作用,这样,没有真正的形成矩阵或块而是通过使用简单指令组,所述虚拟标识符在源组的级别上追踪(track)和解决相关性(dependency)。本实施相对于现有方案的优势在于,其对每个单一指令中使用个别源的相关性追踪和解决。
在指令桶之内和桶之间,可以将指令组合为VLIW或者SIMD或者MIMD。随后将桶作为动态线程来分派或执行。此外,静态软件线程可以共享动态线程的相同的机制,而不同之处在于其生成是基于软件应用线程的。
图7示出了如本领域相关技术所描述的传统的超标量乱序架构。个别指令使用重命名表(图中未示出)来重新命名,所述重命名表将架构寄存器映射到物理的寄存器池中,随后调度、执行并且退回指令。图7中示出的是具有3个分派端口704的一般指令调度器701。通过使用这些端口,可以以程序的乱序顺序来调度和分派至多3个指令,以在3个执行单元702上执行。通过使用回写端口705,指令在每个周期将它们的结果回写到重排序缓冲区703。随后至多3个指令可以从指令重排序/退回缓冲区703上退回,这样它们的目的地寄存器可以非推测地并且持久地更新架构状态。
与图7的乱序硬件的一般实施形成对照,如图8.a所示,本发明描述了动态调度乱序架构,其通过使用指令矩阵/桶和组级别相关性检查以及指令组分派和执行的概念来更好地定标。指令矩阵缓冲区和调度器801存储那些指令矩阵/块/桶。
在一个示例中,确定指令桶806来满足其相关性源并且从而准备进行分派,桶808和809也是如此。如果内部潜在的硬件允许,则这些桶可以在单一周期中执行,或者它们可以以流水线或者非流水线的方式经由多个推测周期来在执行单元802上逐步执行。在这些桶的执行结束之后,将它们的结果写入到指令矩阵退回寄存器文件803。通过使用回写端口805,将它们写作表示桶的一组寄存器。这些桶的目的地寄存器驻留在桶退回缓冲区,直到桶作为一个整体可以以程序的原序列顺序来更新架构状态为止。
于此描述的这个概念的一个可能的实施例具有3个组件:
1-前端
2-调度器和执行
3-后端退回
前端包括:推测线程桶-指针,桶源和目的地列表。调度器和执行桶包括桶分派选择器以及虚拟寄存器匹配和读取,包括可能的寄存器层级和寄存器缓存。后端是将执行的桶记录,并且在退回之前加强了异常排序。寄存器层级/缓存还为执行的桶的结果充当中间存储,直到该结果是非推测的并且可以更新架构状态为止(类似于图8.a示出的803)。下面公开了前端、分派阶段、以及后端的一个可能的实施,其中,记录了执行的桶。这些在图8.b中示出。
通过拾取新的线程矩阵/块/桶,过程开始,并且随后将新的线程桶指定到桶缓冲区中的空桶槽当中。在线程分配指针阵列852中的每个线程分配指针包括桶的间隔,在所述间隔中,允许线程物理地放置其指令的块/桶。每个这样的线程以轮转(round-robin)的方式将桶持续分配到在其对应的临近空间间隔内部的桶缓冲区阵列中。给每个线程空间内部的桶/块指定新号码852,其在指定新的桶/块的每个时刻增加。对于在桶850中的每个有效的源,每个桶的有效的源具有有效的读取位“Rv”,其指示了该源在这个桶内部所需要的指令。通过相同的规范,经由指令在该桶中回写的每个目的地寄存器在这个桶中具有有效的位“Wv”集,并且它具有目的地继承向量853中的字段。当将新的桶拾取到桶缓冲区时,它从之前分配的桶上继承目的地继承向量,所述之前分配的桶由线程桶分配指针852来指明。从之前分配的桶上拷贝继承向量,并且随后所述继承向量重写那些有效的目的地字段,所述有效的字段对应于由那些桶指令更新的寄存器。当从桶内部的对应的继承向量上拷贝无效的目的地时,使用当前桶的号码来标记有效的目的地。随后通过增加线程桶指针,来为新拾取的桶更新线程桶指针(其在内部环绕)。
在桶分派和执行阶段,当在没有任何异常操纵下执行桶时,则设置(包括桶号码的)桶执行标志854,在整个桶缓冲区中广播它,并且在每个桶之内锁住和监视它,所述每个桶具有源和作为源的桶号码。还可以根据桶的号码传送其他相关的信息,例如关于虚拟寄存器位置的信息等。当在桶之内设置了源桶的所有的执行标志时,则设置这个桶的就绪位855,并且准备好对桶进行分派和执行。当桶没有任何异常地执行,并且准备好以程序的序列顺序来更新架构状态时,则它退回桶,并且将退回线程指针857增加到阵列中的下一个桶。可以将退回的桶的位置指定给新的桶。
所有的这些密切相关的线程可以在矩阵/桶/块缓冲区内部共存;每个线程将占据属于该线程的连续的桶的间隔。该线程的分配指针以轮转的方式在桶的该间隔内部移动,来拾取新的指令桶并且以所描述的轮转的方式在线程的间隔之内分配它们。使用这样的间隔区域,将整个桶缓冲区动态地划分为不同的或者相同的间隔长度的桶。
此处引入了指令桶和线程的继承向量的概念。每个指令矩阵/块/桶写入到结构寄存器当中的特定寄存器中。在分配阶段上的每个新桶通过将线程和其所拥有的桶号码写入到继承向量来更新这个继承向量,并且保留没有写入而未更新的寄存器字段。该桶继承向量B_iv 856以程序的顺序从每个桶转发到下一个。在图8.b中,当在矩阵中的指令写入到寄存器中时,每个矩阵将其自己的号码写入到架构目的地寄存器中,否则它从该线程中的之前桶的B_iv上继承值。
经由图9中的实施例所示出,这个概念从管理少量密切耦合的线程的桶缓冲区上,按比例缩放到管理多个桶缓冲区和线程的硬件电路上。将可以扩展来处理具有更少紧密作用的更多线程的那些电路,描述为全局前端,所述全局前端处理线程头(header)902,而无需处理线程内的实际指令,来加强这些远线程的相关性的检查。线程的头和它的桶的子头只包括关于线程和桶写入到的结构寄存器(那些指令的目的地寄存器)的信息,而不需要那些线程头包括实际指令或指令的源。实际上,对那些目的地寄存器和位向量进行列表是足够的,在所述位向量中,为成为指令的目的地的每个寄存器设置每个个别位。不需要将头物理地放置为指令的头;它可以为任何格式的包或者紧密表示,或者在线程内的指令的目的地寄存器的头,其可以或者不可以用其余的指令信息存储。
该全局前端以程序的顺序只拾取线程/块的头,并且生成动态线程和/或桶继承向量901(Tiv和/或Biv)。如903所示,在分配新的线程的每个时刻,通过对当前线程桶没有写到或者更新的旧的字段进行保留,来转发继承向量。将那些继承向量分发给很多个引擎/核心或者处理器904,其中的每一个可以包括局部前端和拾取单元(所述拾取单元将会拾取和存储为每个桶产生相关性向量的实际指令)以及具有局部寄存器文件905的局部矩阵/块/桶缓冲区。随后,局部前-端拾取实际指令并且使用从全局前端获得的继承向量的信息,来为指令的指令源填充相关性信息,所述指令源带入到引擎中来执行。图9示出了全局前端实施例,以及只使用关于指令的简明信息(即是这些指令写入到的寄存器)来将继承向量散布到不同引擎904的方式。放置在头中的其他有用信息是关于线程内的或跨线程的控制路径的变更信息。可以使用全局分支预测器来预测跨这些线程的控制流。这样,头可以包括分支目的地和偏移量。除了用分支预测器确定控制流之外,硬件/编译器可以决定跨2个分支控制路径来分派独立线程。在这样的情况下,如图11所示,它将使用继承向量来稍后合并那2个路径的执行。图9还示出当由全局前部来拾取新的线程的头时的转发过程,例如,线程2(906)将更新对应的继承向量901,将所述继承向量901转发至结果的向量910,在所述向量910中,使用T2标记来更新寄存器1,2,3,4,6,0和7。注意T2桶没有写进910中的寄存器5,所以从之前的继承向量继承其标记。
一个值得注意的观察结果是寄存器文件允许进行跨核心/引擎之间的通信。只要将线程的指令桶拾取并且分配在局部桶缓冲区中,就可以安排跨引擎所需的寄存器的早期请求(以减小访问等待时间),此时填入源的相关性信息,这样在为执行分派实际指令之前,此刻跨引擎的线程引用发布得可能很长。在任何情况下,指令将不会分派直到转发和到达了交叉引用的源为止。可以将交叉引用的源存储在局部多线程寄存器文件或者寄存器缓存中。尽管可以将该交叉引用的源存储在类似于加载存储缓冲区的缓冲区中(它可以重新使用加载存储缓冲区的物理存储装置和相关性检查机制,只是由寄存器加载代替存储器加载)。可以使用许多拓扑结构来连接跨引擎/核心的寄存器文件,所述拓扑结构可以为环式拓扑结构或是纵横式(cross bar)拓扑结构或者网状路由式互连。
下面的论述示出如何在引擎内部以及跨引擎来使用寄存器文件分段。当对桶进行分派时,将其源(同时地或顺序地)发送到寄存器文件和寄存器缓存这二者上。如果将寄存器文件物理地统一并且具有对线程的直接支持,则从对应的线程寄存器区域直接读取操作数。如果寄存器文件是虚拟寄存器,包括使用了标签的物理分段的寄存器文件,则必须进行标签匹配以作为虚拟寄存器读取的一部分。如果标签是匹配的,则从分段的寄存器进行读取。
图9.b示出了总的虚拟寄存器文件和寄存器缓存。其还示出了执行的分段和低级别的寄存器文件。SIMD或者MIMD指令在每个区域访问对应的SIMD/MIMD寄存器数据段,而VLIW指令在每个段中独立地访问不同的寄存器。在线程模式中,每个区域独立地具有单独的指令,所述单独的指令独立地访问寄存器并且可以以统一的视点跨段寄存器来访问。图1-5中示出了线程如何使用寄存器文件层级的更多方式。
在不允许硬件独立地重新安排区域桶的情况下,为了允许保留指令调度的选择权,以作为由编译器自动并行化或者VLIW或者SMID/MIMD的合成物的组成,通过使用位或者标志来利用锁合机制,所述锁合机制将4个桶锁合在一起以作为超桶。如果设置了该位或标志,则超桶之内的所有桶(在这个情况中4个桶)将在相同的周期之内并行地执行。如果没有设置标志,则不将那些桶锁合来一起执行,并且可以在各个时刻独立地执行。
由线程或者乱序执行或者VLIW架构而导致的增加的并行给有限的带宽的寄存器文件带来了巨大的压力。通常将寄存器文件设计为统一资源以允许访问所有寄存器。分段的寄存器文件已经在前进行了设计,但是它们需要在架构/软件级别处跨读/写进行操作,这阻止它们用作资源的统一集,并且增加了跨读/写的开销。
本发明所公开的寄存器架构支持软件线程、硬件生成的线程、VLIW执行、SIMD&MIMD执行、以及乱序超标量执行的模拟。尽管它是物理分段的,但可以将其看作统一的架构资源。该分段的寄存器是虚拟寄存器文件的部分,其可以包括寄存器层级和寄存器缓存以及存储和检查寄存器标签的机制。如果我们使用利用相关性继承向量的基于位置的方案,则无需访问标签。方案这样工作:当在分派阶段期间广播所执行的桶的号码时,接下来的指令的所有源进行CAM(Content Addressable Match,内容可寻址匹配),所述CAM将它们的源的桶与刚分派的/执行的桶作比较,来为该源设置准备好的标志。此处,还可以将该桶执行的物理位置随同寄存器号码一起进行传播,以便解决任何不确定点。例如,在图9.c中,有4个寄存器文件段,其中每个包括16个寄存器。例如,当将桶#x分派给区域2时,将桶的号码x广播到桶缓冲区,并且还将段#2和其一起广播,这样与桶x相关的所有源将会记录:该桶写入了段2中的其所有的寄存器。当时间逐渐开始分派这些指令时,指令知道它们需要从段2而非其它段上读取它们的寄存器,即使相同的寄存器号码存在于其它段上时也是如此。这还可以应用到寄存器缓存上来避免使用标签。我们可以将这个概念扩展到全局前端,其中除了线程信息以外,继承向量可以指明在哪个引擎中,分配了写到这个寄存器的指令桶。
下面描述能够发布SIMD/MIMD、VLIW、ULIB桶指令以及动态和静态线程的统一动态执行架构的描述。该架构在没有明确的乱序组件支持下,还支持对超标量乱序实施的模拟。本发明还可以包括物理分段的、架构的统一寄存器文件以及可能的寄存器缓存层级。
本发明公开的技术允许使用一个统一的方法和实施,来执行软件初始的线程(静态线程)和硬件生成的线程(动态线程)。如上面所提及的,在软件静态最优化级别处识别细粒度并行是困难的,并且因而动态线程是这样一种方式:硬件可以通过将动态线程上下文指定给诸如子例程调用、方法子程序/步骤、独立对象代码或并行循环之类的软件桶,来生成该细粒度并行。这使用公开的实施和方法,通过将一些线程和它们的位标识字段保留给动态线程来实现。例如,在上面的实施例中,可以向硬件动态线程指定可使用的“m”个线程之内的子集线程组。硬件可以使用那些分配的线程保留来动态地生成和/或发布硬件线程。例如,在(如集合的“Call”指令所指示的)子例程调用或子程序调用中,硬件可以将新的硬件线程指定给这样的调用并且最终在返回子例程之后可以要求收回线程保留。相同的情况也适用于循环,在所述循环中,可以在(如集合的“循环”指令所指示的)循环的入口处生成硬件线程并且可以在循环到达其末端指令之后收回硬件线程。还可以将其它指令用作可能的硬件线程机会,其直接映射为软件线程可应用的事件,例如面向对象的方法执行或者对象关联代码或者任何高级别或面向对象的编程线程机会等。在所有情况中,可以通过寄存器/桶的交叉引用和控制标志来解决那些线程的同步,这可以通过上面描述的机制来追踪和解决。图10示出了硬件(或者编译器或者运行时间系统)如何可以使用动态硬件线程来在在循环体内和周围不同的地区重叠指令的执行。
再一次地,线程头封装在循环体1004之内的每个桶的目的地寄存器以及在循环体之外的代码。在这样的情况下,硬件或者编译器将线程T1分配到循环体之前的代码,并且作为示例只有一个线程分配到循环体T2(通过将循环划分为多个迭代直到可以将每个循环迭代指定给一个线程的程度,可以将多个线程指定给循环体,循环线程的数量是可以在运行时或基于编译器分析来决定的动态决定),而将循环之后的代码指定给线程T3。
注意,由反馈回循环体自身T2的循环体的桶生成的继承向量1005,与转发到循环体T3之外的线程的那个继承向量1005些许有些不同。这是因为T3需要由循环上迭代的寄存器的最后拷贝,该最后拷贝通过n指示在继承向量1002中。当到达循环的最后迭代时,在该最后迭代中的所有桶运送标志n,所述标志n设置为桶号码的一部分(即,最高有效位)。
依靠循环体T2的T3寄存器将依靠这个迭代循环T2的最后迭代n。这也将记录在转发给T3的继承向量中。此处假设T2内部没有任何控制路径来在不同的迭代而非最后迭代处改变循环寄存器的更新,则可以使用预测来解决这种控制路径(如果它存在于循环体的内部的话)。可以将标识符n作为如1003中的继承向量的一部分来运送和转发。这本质上指代由循环的最后迭代所构成的桶。此外,可以将这些动态线程指定到分支代码(分支或控制变更接下来的代码)。
可以使用该技术来发布2个线程,其中的一个沿着2个可能分支的每一个。在这样的情况下,一旦架构地解决了分支,则线程中的一个调拨,而另一个则丢弃。考虑到2个不同的控制路径影响不同的寄存器的情况,正在转发向量的继承将指明标志控制F,所述继承将标志控制F嵌入到其桶号码字段1101中。在这样的情况下,在这个控制路径上的相关的桶中的每个源将为由可变的控制路径影响的那些源的寄存器,来指明在继承向量1102之内的条件标志。将标志与桶的号码一起来广播,所述桶的号码在CAM分派匹配期间将该标志执行/解决到所有相关的桶。这在图11中示出。标志的意图是远离的桶目前不知道哪个线程将转发它们所需要的特定寄存器的值(直到执行和决定了标志条件为止)。沿着2个可能的分支路径的线程沿着其路径继续执行,直到解决了标志并且线程中的一个(沿着错过预测的路径)被毁灭为止。但是在沿着这2个路径的执行期间,拾取了和分配了沿着支路方向的许多其他桶,并且它们的继承向量转发。它们需要标志,这样它们可以使用从沿着正确的执行路径的控制线程而来的正确的桶号码,来代替该标志(且等待它们的相关性来解决)。注意我们还可以利用线程和桶的头来找到需要的信息。
另一个创新是在每个结构寄存器之内包含标志字段,这样每个架构或者物理寄存器具有作为可视状态的部分的标志字段。这允许简单的预测机制,来为了指令的条件执行以及能够为分支指令容易地创建延迟槽。例如,在循环中,对循环末端条件进行测试的测试指令必须先于分支指令而在二者之间没有其他标志修改指令。使用寄存器标志字段,并且通过指明这个分支依靠特定寄存器的标志(在这个示例中为测试指令的目的地),测试条件可以放置在循环的开始处,而实际分支可以在循环的末端处。因此,到分支指令在机器的前端处的时候,已经执行了测试指令并且分支可以在前端阶段处而非执行阶段处执行,因而排除了气泡。这些寄存器标志还方便简单指令预测或者线程预测,其中,可以基于特定指令的结果,来对指令或者特定线程中的指令进行预测,该结果不需要在执行序列中立即先于它。这在图11.b中示出。在分支位置处的前面执行测试指令1150。基于其结果,测试指令1150将拾取正确的程序指令路径,并且将它们保留在一边,直到将分支指令1151分配在前端处为止,并且随后它在流水线中供给这些指令。该架构还可以在分支1152之后预测指令,并且在分支之前执行它们,并且在执行分支之后使用有条件的移动。如图11.b所示,还可以与执行的2个可能的控制路径并排来发布2个线程。
此外如图11.b所示,测试指令1150可以推测地执行,即使其源是推测的或者由硬件或编译器来预测也是如此,但该测试指令1150写入到推测的标志F2中,当先于分支1151的实际测试指令执行时,它写入到标志F1中,此时,将2个标志进行比较,并且如果它们匹配与测试指令1150一起开始的推测的执行线程,则该线程继续存在于正确的控制路径中,而其他线程使用在图11.a示出的继承合并机制来停止拾取指令。如果标志没有匹配,则其他线程继续拾取,并且早期测试的线程停止。这允许线程推测和从错过的推测中快速恢复(对于早期的分支推测没有等待时间惩罚)。
通过线程的寄存器交叉引用的操作是在线程自动生成和/自动同步中的另外一个关键要素。可以通过使用经由加载和存储的存储器访问,来进行这些引用。
在图12中,我们大体上示出了全面的方案以及在线程之间和/或在加载和存储之间的同步方案的实施。方案描述了优选的方法,用于跨加载/存储架构的存储器引用和/或跨存储器引用和/或线程的存储器访问的同步和消除歧义。在图12中,我们示出了寄存器文件(地址或数据寄存器)的多个段、执行单元、地址计算单元、第1级缓存和/或加载存储缓冲区和第2级缓存和地址寄存器互连1200和地址计算单元互连1201。通过将一个核心/处理器的集中资源分段和分发给各个引擎,可以在一个核心/处理器内构建这些分段要件,或者从多核心/多处理器配置中的不同的核心/处理器要件来构建它们。在图中将段1211中的一个段示为段号1;可以将该段按比例缩放到大的号码上(通常到如图中示出的N段)。
这个机制还当作对于这些引擎/核心/处理器之间的存储器架构的一致方案。这个方案由地址请求开始,所述地址请求来自于一个段/核心/处理器中的地址计算单元之中的一个。例如,假设由段1(1211)来请求地址。通过使用属于其自己段的地址寄存器,和/或使用地址互连总线1200从跨其他段的寄存器上,段1可以获得并且计算它的地址。在计算地址之后,它创建用于访问缓存和存储器的32位地址或64位地址的基准地址。通常将该地址切分为标签字段以及集和行字段。该特定的段/引擎/核心将地址存储到它的加载存储缓冲区和/或L1和/或L2地址阵列1202中,同时,通过使用压缩技术,它将创建标签的压缩版本(具有比地址的原标签字段更少的位)。更多的,不同的段/引擎/核心/处理器将集字段或集字段的子集用作索引来识别地址保持在哪个段/核心/处理器中。通过地址集字段位,该段的索引确保在特定的段/核心/引擎中的地址的所有权的排他性,即使与该地址相对应的存储器数据可以存在于另一个或多个其他的段/引擎/核心/处理器中也是如此。即使在每个段中均示出了地址CAM/标签阵列1202/1206与数据阵列1207相耦合,但它们的耦合也只是布置和规划的物理近似,或者即使源于二者都属于特定的引擎/核心/处理器的事实,但是在一个段内的地址阵列中保留的地址和数据阵列中的数据之间也没有关系。在形成压缩的地址标签之后,使用集的字段位来识别请求寻址到的特定地址CAM阵列1202。假设其表明是那些集字段位将段/引擎/核心/处理器N认作是拥有地址作用域的那个,则将经压缩的标签发送到该段/引擎/核心/处理器(段N)L1CAM和/或相对应的L2CAM阵列,该阵列随后将在到来的压缩标签和每个存储在其阵列中的压缩标签之间进行内容地址匹配(CAM)。由于这是经压缩的标签,因而CAM阵列的宽度是最小的并且因而能够负担对Cam阵列的构造,所述CAM阵列具有与数据阵列相似的项号码(通常CAM阵列是非常昂贵并且耗能的)。在CAM匹配完成之后,其结果可以是命中(hit)或错过或多个命中(优良的压缩技术应该减少多个命中的数量)。随后在命中/多个命中的情况中,读取在段N中对应于CAM命中项的Loc阵列(位置阵列)1203,以识别属于该地址CAM命中的存储器数据的位置。将这个位置发送回至在请求段(本示例中的段1)中的请求地址计算单元。通过使用互连1205的地址总线,该地址计算单元请求缓冲区1204将完整的地址发送到该位置1206的地址/标签阵列。随后进行标签的查询和比较,以确保准确的/唯一的命中。随后,如果确定命中,则使用互连1205的数据总线来返回数据。如果在CAM或是完整标签阵列中发生错过,则代表请求段来放置对于主存储器的请求。如前面所描述,还可以(通过使用作为索引的集字段位)削减更多的等待时间并且将完整的地址发送到拥有地址作用域的段上,并且在该段处,经压缩的标签形成并且首先访问CAM阵列,而完整的地址保持在那直到检查了CAM的结果为止,并且读取位置阵列1203来识别在标签阵列1206中的项号码,所述标签阵列1206在压缩标签1202中命中。随后使用与CAM相对的比较器,来在完整的地址上完成了完整比较。CAM阵列1202的实施并不需要真正地进行CAM,由于这个比较可以在从完整的标签上获得的并且经过压缩的少数位上进行,所以CAM阵列可以实施为直接索引的寄存器阵列(RAM)或寄存器文件,例如,如果经压缩的标签形成为8位字,则可以将每个段的整个CAM阵列构建为256项RAM阵列,当8位经压缩的标签到来时,它直接进行解码来读取位置阵列1202的256个项中的一个(事实上,在这种8位经压缩的标签的情况中,CAM阵列不需要存在为物理阵列),因此它实际只需要用作对于未知阵列1203的解码器。
下面所要描述的方案,通过定义称为“Temp”和“Chain”的临时存储变量,来在没有增大寄存器压力的情况下,经由发布(issue)存储器加载时间头,来定义存储器等待时间的减少。只使用一次Temp,来允许指令指代存储器中的位置并且将其预取到缓存缓冲区中的特定位置。这不同于将数据预取到缓存的一般方案,因为使用了Temp和Chain,在Temp预取的值和其消耗指令之间是直接1对1的映射;这类似于寄存器指定可以实现的。相反地,在一般的缓存预取方案中,将存储器数据预取到缓存中的地址位置,消耗指令可以通过数据的存储器地址只引用这个预取的数据。消耗指令的调度器并不知道,因而当它执行时消耗指令没有关于发现数据的控制。在此处描述的新的Temp和Chain的方案的情况中,将存储器数据带入到缓存缓冲区中(加载到缓存中)并且指定一个名称“例如,Temp 0”,这个加载的数据的消耗指令现在可以明确地指代Temp 0这个名称,并且当它执行时,期望以绝对的保证在Temp 0的位置中发现它。因为将Temp号码指示为在消耗指令中的相关性的源,所以调度器将不会发布该指令直到Temp是有效的为止(将数据从高级别缓存或存储器实际地加载),这类似于当将存储器的值加载到寄存器中时所发生的。如图12所示,除了精确预取(1对1映射)和消耗指令的精确调度之外,这还具有额外的益处,其允许等待时间可变的分布式缓存。
为了防止Temp和Chain在它们的消耗者指令释放它们之前毁灭,编译器确保它将不会重新指定这个寄存器,直到它的消耗者指令消耗它为止。
在寄存器指定和Temp指定之间的不同很少;使用Temp来将所需要的数据带入到缓存缓冲区中的临时位置,其根据消耗指令(引用该临时位置的指令)消耗的值,来自动地进行解除分配。这将确保该Temp的生命范围很短,并且因此可以非常高效的使用。可以在程序中指定Temp的一个方式是通过使用与加载地址计算指令(或地址计算指令桶)相配的标记,即:
Label Temp 0:Load@Address(R5,R2,offset)
..........
..........
R10←R17,Temp 0
在代码段或子例程中使用的Temp的标记必须在它们使用之前分配。所以,如果编译器意图使用10个Temp位置来预取其数据,它应该使用分配指令/例行程序,来在缓存/缓冲区中分配这些Temp位置。在每个指令消耗其Temp之后,Temp位置将会空闲。硬件可以通过上下文切换来为另一个子例程重新分配这些Temp位置/标记;可以通过使用缓存/缓冲区来实现,所述缓存/缓冲区存储和线程ID标签一起分配的Temp数据。当遇到新的子例程的标记分配指令时,硬件将指定新的线程ID和新的Temp位置。如果在缓存/缓冲区中没有空间来供新的线程占据时,则在分配指令/例行程序的执行期间,非闲置的Temp位置(由于它们的指令还没有消耗它们)将和正在切换的其余的旧的线程上下文一起,在存储器中进行保存/存储。当带回该旧的线程上下文来继续执行时,需要回复和载回这些Temp数据。这将考虑到意料之外的上下文切换的执行(例如,在对异常句柄的调用或系统调用时)。
Chain类似于Temp,但具有两个不同:Chain是相对于只一个的位置序列;第二是无论具有多少要件“位置”,整个Chain都用一个标记进行标记。通过使用类似于Temp的分配指令/例行程序,来分配Chain。类似地,当执行该分配指令时,如果在缓存/缓冲区中没有针对Chain的新的线程空间可以指定给新的线程Chain,则检查该特定Chain要件以找到哪些已经释放(由于它们的消耗指令已经使用了它们),将没有释放的那些保存到存储器并且新的线程Chain可以使用那些空间。Chain允许在一列预取/加载指令和消耗指令之间创建1对1的映射,以允许获得类似于具有可变名称号码的寄存器(例如,R(i))的效果。这在循环内部访问阵列是有作用的,其中,在远远先于消耗指令在循环中需要值之前Chain可以在循环内部开始对值进行预取,而没有产生寄存器压力。可以使用缓存架构或缓存缓冲区来存储这些Temp和Chain要件。图13以乱序执行的方式示出了对于这种概念的实施。在这里,我们再一次示出指令调度器/块缓冲区1304以及转发继承向量。一旦分配了Chain,则它在继承向量中具有重置为0的它的写计数器1300。对于通过加载而到Chain的每个新的指定,写计数器增加并且从而写到Chain要件的每个指令中的目的地要件将得到这个新增加的号码,例如,在3个指定将3个寄存器位置加载到缓存缓冲区之后,计数器的值将会为3个1301。在循环代码内部和对于每个循环迭代,通过每个Chain加载指令,写计数器将继续增加;加载到Chain中的这些展开的动态指令将具有这些增加的号码。在消耗指令方面,具有读计数器1303,当遇到从Chain要件读取的每个消耗指令时,读计数器1303也保持增加。例如,引用Chain 0来读取其第一要件的第一指令将读计数器从0增加到1,随后,从Chain读取的下一个消耗指令将计数器增加到2并且因而它知道它需要从Chain 0第二要件读取。在没有真正依赖于实际的加载地址下,写计数器和读计数器的方案确保在Chain要件的加载和它们的消耗指令之间的隐含的同步。这将具有可变寄存器索引(例如,R(i))的类似效果。
图13.b示出在缓存或缓冲区1351中的项(例如示出为1350的Temp 16)如何依靠由编译器/硬件插入的分配指令1352来动态地指定给Temp和Chain。在图中,将Chain A指定给硬件Chain 0、1、2、3(其中每个在缓冲区中均具有4个位置,通过结合它们的存储1353,因而总共给Chain A分配16个单位)。在图中还示出了Chain和Temp的存储如何覆盖在彼此的上面,从而可以将存储在同时指定给一个或其他。
图14所描述的机制使用地址寄存器,来提供乱序执行以对存储器地址进行计算,而不需要过多的存储空间来重命名那些地址寄存器。该方案利用下述事实:地址寄存器一般通过增加或减少它们来更新1400,而可以通过增加和按比例缩放多个这种地址寄存器来构建完整的寄存器地址以形成完整地址(例如,将基本寄存器添加到索引寄存器并且使用缩放比例因数和偏移量)。方案使用硬件调度器/指令桶缓冲区1401以及继承向量1402来存储增加/减少计数器1403,即,每次地址寄存器增加或减少时,继承向量记录进行那个更新的指令/桶,并且在调度器/桶缓冲区内部对增加/减少事件的计数器1403进行追踪。每个地址寄存器的名称只有一个实际的物理地址寄存器,(所以不存在多个物理寄存器,可以如同在一般重命名的方案中所使用的那样,来指代相同寄存器名称)。为了加载其他的值或者进行更新而不是增加或减少寄存器地址,则必须使用常规的数据寄存器(因为它们是重命名的并且可以存储寄存器名称和值的多个版本)。当执行这样的引入的更新指令时,将数据寄存器的拷贝发送给一个地址寄存器,并且随后,如描述的那样可以使用继承向量来增加或减少地址寄存器,以对更新进行追踪。
图15扩展了加载的用法,以允许对传送较早存储指令1500的数据进行推测的预取/加载(它们以程序顺序先于加载而存储)。
方案在Temp指定指令1503(预取/加载指令)中使用限定符。该Temp指定/预取指令将数据带入到缓存中的临时位置,它对地址没有执行任何次序检查(发现id,加载的地址与还没有执行的存储的那个进行匹配。进行这个次序检查来阻止所述加载从存储器带进数据,所述存储器还没有由在序列执行中先于加载的存储更新)。当消耗指令1504执行时进行顺序检查,此时,如果顺序检查发现:预取的地址正在从在前的存储的相同地址上加载,则消耗指令1504将使用绕过机制(bypass mechanism)来得到存储的值而不是Temp的值。通过为匹配的地址检验存储缓冲区,可以将绕过机制随着次序检查处理来实施,该处理执行为消耗指令1504的执行阶段的部分,并且如果发现了针对在Temp指令加载来自存储器的数据之后执行的较早的存储指令的那个,则该存储的值将会绕到消耗指令而不是Temp的值。可以通过使用相同线程控制预测来在存储指令前面预测地执行消耗指令自身,通过对次序检查发布和有条件的执行预取/加载线程,在图11中论述了所述相同线程控制预测,当先前存储1500执行时,明确地或者隐含地执行所述次序检查。
在本发明的描述中,通过示例示出使用了Temp、Chain、和指令桶的实施方案,通常可以将本文描述的方案应用到加载或简单指令上。
而且,所示的同步和一致方案并不仅仅应用到分布式缓存或单独地址寄存器文件上,还可以将它们使用在不同处理器之间的集中缓存中,并且还可以部分地或通过对方案进行轻微修改来使用它们。
本发明的一个实施例涉及具有计算机可读介质的计算机存储产品,所述计算机可读介质上有计算机代码,以进行各种计算机实施的操作。该介质和计算机代码可以是为了本发明的目的而专门设计和构建的,或者它们可以是公知的并且对计算机软件领域的技术人员来说是可得到的。计算机可读介质的示例包括但不限于:诸如硬盘、软盘、磁带之类的磁介质;诸如CD-ROM、DVD和全息装置之类的光介质;磁-光介质;以及专门配置为存储和执行诸如专用集成电路(“ASIC”)、可编程的逻辑装置(“PLD”)以及ROM和RAM装置之类的程序代码的硬件装置。计算机代码的示例包括:诸如由编译器等产生的机器代码,以及包含更高级别代码的文件,所述更高级别代码通过使用解释器由计算机来执行。例如,可以使用Java、C++、或者其他面向对象的程序语言和开发工具来实施本发明的实施例。可以使用硬件实现的电路代替或结合机器可执行的软件指令,来实施本发明的另一个实施例。
用于解释目的的上文描述使用了具体的术语来提供对于本发明的全面理解。然而,对本领域技术人员显而易见的是,实施本发明无需这些具体的细节。因而,将本发明的具体实施例的上文描述表示为示例和描述的目的。其目的并不在于穷举举例或是将本发明限制到所公开的准确形式;显然,可以根据上面的教诲来进行各种修改和变化。为了最佳地解释本发明的主旨和其实际的应用,来选择和描述实施例,因此它们使本领域的其他技术人员能够最佳地使用本发明和各个实施例来进行各种修改,以适合所预期的特定使用。由所附权利要求和其等价物来限制本发明的范围。
Claims (25)
1.一种用于指令处理的系统,包括:
缓存,其适于存储用于消耗指令的预取值,其中所述缓存将预取值与对应的名称相关联,并且其中所述消耗指令明确地引用所述对应的名称而不是存储器地址,其中所述对应的名称是与在程序内的加载地址计算指令相关联的标记,所述程序被执行以获取所述预取值;以及
调度器,其用于在所述预取值被加载到所述缓存中后发布所述消耗指令,并且用于在执行单元利用所述预取值执行所述消耗指令后释放在所述缓存中的所述预取值的位置。
2.根据权利要求1所述的系统,其中所述对应的名称指示所述消耗指令的相关性源。
3.根据权利要求1-2中任何一项所述的系统,其中在所述执行单元执行所述消耗指令前,所述调度器确认从更高的存储器有效地加载了所述预取值。
4.根据权利要求1所述的系统,其中使用响应于对异常句柄的调用或系统调用的上下文切换来释放所述预取值的所述位置。
5.根据权利要求1所述的系统,进一步包括具有标志字段的物理寄存器,以便于指令的条件执行以及用于分支指令的延迟槽。
6.根据权利要求1所述的系统,进一步包括指令拾取单元,其用于响应于对标志字段的求值而选择性地执行条件分支指令。
7.根据权利要求1所述的系统,
其中所述缓存适于存储用于消耗指令的序列的预取值的序列,其中不管预取值的数量如何,所述预取值的序列具有单一的对应的名称,
其中所述执行单元适于使用所述预取值的序列执行所述消耗指令的序列,以及
其中所述调度器适于在所述执行单元执行所述消耗指令的序列后释放在缓存中的所述预取值的序列的位置。
8.根据权利要求7所述的系统,其中使用所述预取值的序列来访问循环内的矩阵。
9.根据权利要求7-8中任何一项所述的系统,其中当所述预取值的序列被分配时,调度器重置在继承向量中的写计数器。
10.根据权利要求8所述的系统,其中所述调度器为循环的每次迭代增加写计数器。
11.根据权利要求7所述的系统,其中所述调度器为每个消耗指令维护读计数器。
12.根据权利要求11所述的系统,其中所述调度器为从所述消耗指令的序列读取的每个消耗指令增加所述读计数器。
13.根据权利要求7所述的系统,其中所述缓存存储所述预取值的序列,而不进行顺序检查。
14.根据权利要求13所述的系统,其中当消耗指令执行时所述调度器针对存储进行顺序检查。
15.根据权利要求14所述的系统,其中所述调度器包括绕过机制以选择性地拾取存储的值而不是预取值。
16.根据权利要求7所述的系统,其中所述执行单元通过线程控制推测在存储的指令前推测性地执行消耗指令。
17.根据权利要求16所述的系统,其中在顺序检查时所述执行单元有条件地执行预取线程,所述顺序检查是执行在先存储时所作出的。
18.一种由处理器实现的方法,包括:
在缓存中存储用于消耗指令的预取值,其中所述缓存将所述预取值与对应的名称相关联,并且其中所述消耗指令明确地引用所述对应的名称而不是存储器地址,其中所述对应的名称是与在程序内的加载地址计算指令相关联的标记,所述程序被执行以获取所述预取值;
在所述预取值被加载到所述缓存中后,发布所述消耗指令;以及
在使用所述预取值执行所述消耗指令后,释放在所述缓存中所述预取值的位置。
19.根据权利要求18所述的方法,其中所述对应的名称指示所述消耗指令的相关性源。
20.根据权利要求18-19中的任何一项权利要求所述的方法,进一步包括:
在执行所述消耗指令前,确认从更高的存储器有效地加载了所述预取值。
21.根据权利要求18所述的方法,其中用响应于对异常句柄的调用或系统调用的上下文切换来释放所述预取值的位置。
22.根据权利要求18所述的方法,进一步包括:
在所述缓存中存储用于消耗指令的序列的预取值的序列,其中不管预取值的数量如何,所述预取值的序列具有单一的对应的名称;
使用所述预取值的序列执行所述消耗指令的序列;以及
在执行所述消耗指令的序列后释放在缓存中的所述预取值的序列的位置。
23.根据权利要求22所述的方法,其中所述预取值的序列用于访问循环内的矩阵。
24.一种其中存储有代码的机器可读介质,当所述代码被执行时,使处理器执行如权利要求18-23中任何一项所述的方法。
25.一种计算装置,包括多个模块以用于执行如权利要求18-23中任何一项所述的方法中的对应步骤。
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EP2527972A2 (en) | 2012-11-28 |
EP2122461A2 (en) | 2009-11-25 |
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