200833002 九、發明說明： 【發明所屬之技術領域】 本發明係有關一種具公平性之分散式交換電路，其兼具集 中式演算法之公平性、可以避免後到之輸入資料插隊之情形， 以及模組化的設計使交換電路佈設容易等優點。 【先前技術】 由於製程技術進步，單一晶片裡可併入之智產核心（即π Core)越來越多，彼此的資料交換也越趨頻繁，傳統的單—匯 流排已無法滿足多個智產核心的頻寬需求；因此，利用晶片網 路骨幹來代替傳統單一匯流排的設計已是時勢所趨。 在晶片網路骨幹中，扮演資料交換傳遞的主要角色便是交 換is(Switch) ’交換器的效能越高，晶片網路骨幹的效能也越 高；而交換電路為交換器裡的一個重要部份；因此，如何設計 一個精良之交換電路，便成為一個重要的課題；而傳統之交換 電路中的排程器所採用之排程演算法分為集中式 (Centralized)與分散式(Distributed)兩大類；集中式排程演 #法代表為「輪流式」（或稱R〇und_R〇bin式），而分散式排程 法代表為「乒乓仲裁式」（或稱pingp〇ng八汁丨廿扣。 土參閱第一人、第一 B及第一 C圖，第一種習知技術採用「輪 々•L式」决异法的交換電路，其至少具有一個集中式 tralized)之仲裁器84，分別控制複數個多工器82以及 一輸出點83，進而服務所有的（此例為8個）輸入端81A、81B、 5 200833002 81C、81D、⑽、⑽、81G及·，其仲裁方式是採用輪流的 方式伽8U之後謂、然後81C..·.到⑽全 部輪元後再重新回到輸入端81A，一直重覆； 若在此定義所謂『仲裁週期』，是指從選定被服務的輸入 端開始’聰務完所有選定被服務之輸人端的㈣。那麼华中 式仲裁器在每-個仲__必絲得知每個輪人端^求 狀態，再依此需求狀態輪詢服務。 而、 如第- B圖所示’係為f用八個輸入端之典型範例，第— c圖表示傳遞之過程，其第—輪之輸出依序為Μ% 輪=是0-4-5-7 ’此時，輸入端〇、4、5、7分別為挪 種演算法的優點在於輯的公平，但缺點是完成—次仲裁計曾 所需時間較長，服務對象越多，仲裁時間越長。 4 如果以N代表服務對象的數目，則電路運算複雜 〇jN);另—缺點是若N的數量越大，例如16、32或更多^200833002 IX. Description of the invention: [Technical field of the invention] The present invention relates to a decentralized switching circuit with fairness, which combines the fairness of a centralized algorithm, avoids the situation in which input data is inserted, and The modular design makes the switching circuit easy to lay out. [Prior Art] Due to the advancement of process technology, more and more intellectual cores (ie, π Core) can be incorporated into a single chip, and data exchange between them is more frequent. The traditional single-bus bar cannot satisfy multiple wisdoms. The core bandwidth requirements; therefore, the use of the chip network backbone to replace the traditional single bus design is a trend. In the backbone of the chip network, the main role of the data exchange is to exchange the is (Switch) 'the higher the performance of the switch, the higher the performance of the chip network backbone; and the switching circuit is an important part of the switch Therefore, how to design a sophisticated switching circuit becomes an important issue; while the scheduling algorithm used in the traditional switching circuit is divided into two types: centralized (distributed) and distributed (distributed). Large class; centralized scheduling performance is represented as "rotational" (or R〇und_R〇bin), while decentralized scheduling is represented by "ping-pong arbitration" (or pingp〇ng eight juice) Referring to the first person, the first B and the first C picture, the first conventional technique adopts a "rim L L type" variant exchange circuit having at least one centralized tralized arbiter 84, Controlling a plurality of multiplexers 82 and an output point 83 respectively, thereby serving all (in this case, eight) input terminals 81A, 81B, 5 200833002 81C, 81D, (10), (10), 81G and ·, the arbitration mode is adopted The way of taking turns is gamma 8U Then 81C..·. to (10) all the rounds and then return to the input terminal 81A, repeating; if the definition of the so-called "arbitration cycle", it means starting from the selected input of the service (four) being served by the person. Then, the Huazhong arbitrator knows the status of each round in each __ _ _ _ _, and then polls the service according to the demand status. However, as shown in Figure-B, the system is a typical example of eight inputs. The figure c shows the process of transmission. The output of the first wheel is Μ% round = 0-4-5. -7 ' At this time, the advantages of the input terminals 〇, 4, 5, and 7 respectively for the seeding algorithm are the fairness of the series, but the disadvantage is that the completion-time arbitrage meter takes a long time, the more service objects, the arbitration time The longer it is. 4 If N represents the number of service objects, the circuit operation is complicated 〇jN); the other disadvantage is that if the number of N is larger, for example, 16, 32 or more ^
電路之佈線設計變得非常複雜。 、J 丘仲2弟一A、第二β及第二C圖，第二_知技術採用「丘 乓仲裁式」演算法則，是將一仲掷 節點（即分別㈣相對庫之夕 功能分散於各個父 —相對應之多工器92)，當兩邊都有要求時， 母^點則綱其卜邊，下她輪—邊，像兵丘 一，’以便控職數輸人端91之資觀依-定之規則傳2 預疋之輪出點93 ;所以不需要中控式仲裁器。 " 6 200833002 ”也由於每辦鑛服務縣減少，所以其完成—次仲裁計 异所需時附目雜短，此外，電路之雜設計也較單純，·第一 B圖士係表示制為八個輸人端之典型範例，當條件同前段之： 形時’其傳遞過程如第二c圖所示，第一輪之輸出依序^ 0 4-0-7，第二輪則是〇_5_〇_7。此時，輸入端〇、心5、7分 別為5⑽、12. 5%、12. 5%及辦，形成不公平之情形(輪入端刀〇 最多，佔去1，相當不公平）；如果以N代表服務對象的數 目’則電路運算複雜度為G(lQg2N)。但由於仲裁器已經分散， 所以只能知道自己服務對象的要求狀況。 " 因此無法公平控管所有的服務對象，進而造成不公平的仲 裁，或是有插隊情形發生，造成輸出順序的改變；總之，分散 =排“异法雖然改善了集中式排程演算法的仲裁計算時 衍生請裁不公平之缺點，最主要的朗在於傳統分 放式排程雜法無法處雖人端持續提轉麵情形，一 旦有輸入簡續糾贿要求，_持魏 :以獲得較多的服務，造成整體的服務不公平;或者：二 端在仲裁週期開始時並未提出則 " 要求’造成插隊情形，進而影響了輪出的順序。 因此，有必要研發新技術以解決上述 【發明内容】 ' 本發明之主要目的，在於提 電路，其具有集中式演算法之^性平性之分散式交換 200833002 本發明之次-目的，在於提供—種具鮮性之分散式交換 電路，其可以避免後到之輸入資料插隊之情形。 本發明之又-目的，在於提供—種具公雜之分散式交 換電路’其模組化的設計使交換電路佈設容易。 本發明係提供-種具公平性之分散式域電路，其包括： 複數個輸入部，其數量為N且N為2的M次方，當該輸入The wiring design of the circuit becomes very complicated. , J Qiuzhong 2 brothers A, second β and second C map, the second _ knowing technology adopts the "Qiu Pang Arbitration" algorithm, which is to divide the function of a singularly thrown node (ie, respectively (4) relative to the library Each parent - the corresponding multiplexer 92), when both sides have requirements, the mother ^ point is the outline of the side, the next round - side, like the martial one, 'to control the number of positions to lose the 91 The view-by-fix rule 2 passes the pre-emption round out of 93; therefore, there is no need for a centrally controlled arbiter. " 6 200833002 ” also because each mining service county is reduced, so its completion - the arbitral assessment needs to be short-sighted, in addition, the circuit's miscellaneous design is relatively simple, · the first B chart system is A typical example of eight input terminals, when the conditions are the same as those in the previous paragraph: When the shape is 'the transmission process is as shown in the second c picture, the output of the first round is in the order ^ 0 4-0-7, and the second round is 〇 _5_〇_7. At this time, the input end 〇, heart 5, 7 are 5 (10), 12. 5%, 12. 5% and do, forming an unfair situation (the most in the end of the wheel, taking up 1 , quite unfair); if N represents the number of service objects' then the circuit operation complexity is G(lQg2N). However, since the arbitrator is already dispersed, it can only know the requirements of its own service object. Manage all the service objects, which will lead to unfair arbitration, or there will be a queue situation, resulting in a change in the output order; in short, the dispersion = row "although the law has improved the arbitration calculation of the centralized scheduling algorithm. The unfair disadvantage, the most important thing is the traditional split scheduling Although the legal department continues to raise the situation, once there is a request for continuous bribery, _ Wei: to obtain more services, resulting in unfair service; or: the second end did not propose at the beginning of the arbitration cycle Then " requires 'causes the queue situation, which in turn affects the order of rotation. Therefore, it is necessary to develop a new technology to solve the above [invention] The main purpose of the present invention is to provide a circuit with a centralized algorithm for the flatness of the decentralized exchange 200833002. The second objective of the present invention is to provide A kind of decentralized switching circuit with freshness, which can avoid the situation of input data entering the queue. Still another object of the present invention is to provide a distributed switching circuit of the present type, which has a modular design that facilitates the layout of the switching circuit. The present invention provides a decentralized domain circuit with fairness, comprising: a plurality of input parts, the number of which is N and N is 2, the power of the power, when the input
部内有資料要傳送時，則會發出一服務要求信號；” J 複數個多工器及同數量之解多工器，共級，後一級 之數量係前-級之-半：每―多工器均具有兩健至前一級之 貧料輸入端及-個接至後—級之資料輪出端；每—解多工哭均 具有兩個接至前—級之回流輸㈣及—個接至後-級之回流 輸入端； N個遮罩電路，每—遮罩電路具有·· 山^個―對一之多工器’係至少具有兩個訊號輸入 山為虎輸出端及一切換選擇端，·其中一訊號輸入端係連接 至該輸入部，另—訊號輸人端則連接至_之〇值； p〜㈣型正反器構成之暫存部，係至少具有-暫存 淳、暫存部重設部、—暫存部資料輸人料—暫存部 貝/埠；卿存部_卩_，人-鱗啟動新循環信 號；以及 们_JD閘，係至少具有一要求端、一資料認可 8 200833002 端、及閘輪出端·’該要求端係連接至相對應之輸入部之服務 要求信號，該:#料認可端侧以讀人後-級解多工ϋ傳回之資 料認可喊’銜出端則連接至簡存部設定蟑； 複數個微型排程器電路，共分成Μ級，次-級之數量係為 、 半，母微型排程器電路具有兩個連接到前一級之 要求輸入端、-個連接到後__級之要求輸出端及兩個選擇信號 輸出端； 13 個輸出’係與最末級之多工器之資料輸出端相連接； 當資料接收完成時，則會發出—資料認可訊號，連接至最末級 之解夕工…經由相對應之解多工器使該遮罩電路控制相對應 之微型排㈣電路選擇錢輸出端發出娜錢； ^ 又’當在—仲__之所有應被服務的輸人部都被服務 完後，最後-_微型排程器電路之要求輸出端輸出便會為邏 輯〇 ’此時所有遮罩電路的暫存部重設部會收到這個邏輯〇传 號，便會重新開啟服務，展開新的仲裁週期。 。 上本發明之上述目的與優點，不難從下述所選用實施例之詳 細說明與附圖中，獲得深入瞭解。 兹以下列實施例舰合圖式詳細說明本發明於後： 【實施方式】 本發明係為-種具公平性之分散式交換電路，參閱第三 圖，其第一實施例包括： 複數個輸入部10，其數量為Ν且Ν為2的Μ次方，當該 9 200833002 輸入部1〇内有資料要傳送時，則會發出一服務要求信號；在 第—貝知例=’知4，所以M=2，且為方便解釋可暫時被當成 是第0級之資料輪出端； 稷數個夕工器2〇(簡稱Mux)及同數量之解多工器別（簡稱When there is data in the department to be transmitted, a service request signal will be issued;" J Multiple multiplexers and the same number of multiplexers, common level, the number of the latter level is pre-level - half: each - multi-work The devices have two inputs to the poor input of the first stage and one to the data wheel of the post-stage; each of the solutions has two connections to the front-stage reflow (four) and one to Back-stage reflow input; N mask circuits, each-mask circuit has ··山^-one-to-one multiplexer' has at least two signal input mountains for the tiger output and a switch selection , wherein one of the signal input terminals is connected to the input portion, and the other signal input terminal is connected to the value of _; the p~(four) type positive and negative device constitutes a temporary storage portion, which has at least - temporary storage, temporary The resetting department of the depository department, the temporary data storage unit, the temporary storage department, the 卿 , 、, the human-scale, the new cycle signal; and the _JD gate, which has at least one request end, A data approval 8 200833002 end, and the end of the brake wheel · 'The request end is connected to the corresponding input part of the service request signal, : #料认可端端After reading the person-level solution multiplexed ϋ 之 之 之 认可 认可 ' ' 衔 衔 衔 衔 衔 衔 衔 衔 衔 衔 衔 衔 衔 衔 衔 衔 衔 衔 蟑 蟑 蟑 蟑 蟑 蟑 蟑 蟑 蟑 蟑 蟑 蟑 蟑 蟑 蟑 蟑The number of stages is half, the mother micro-schedule circuit has two required inputs connected to the previous stage, one required output connected to the latter __ stage and two selection signal outputs; 13 outputs' It is connected with the data output end of the last stage multiplexer; when the data is received, it will send out a data approval signal, which is connected to the last stage of the solution... by the corresponding solution multiplexer The mask circuit controls the corresponding micro-row (four) circuit to select the money output end to send money; ^ and 'when the input part of the -zhong __ should be served, the last -_ micro-schedule The output of the circuit requires that the output of the circuit be logic 〇 'At this time, the temporary resetting section of all the mask circuits will receive the logical semaphore, and the service will be restarted to start a new arbitration cycle. The above purposes and advantages are not difficult to implement from the following options. The detailed description and the drawings are to be understood in detail. The following is a detailed description of the present invention in the following embodiments: [Embodiment] The present invention is a fair-type decentralized switching circuit, see the third The first embodiment of the present invention includes: a plurality of input units 10, the number of which is Ν and Ν is 2, and a service request signal is sent when there is data to be transmitted in the input section of the 200833002002 In the first-be-known example = 'know 4, so M = 2, and for convenience of explanation can be temporarily regarded as the data round of the 0th level; 稷 several 夕工器 2〇 (referred to as Mux) and the same number Solution multiplexer (referred to as
DeMUX) ’共分成M級’後—級之數量係為前一級之一半，在第 -實施财，由於N=4，M=2，所以分成第—級(2個)與第二級 (1個）’每夕工益2Q均具有兩個接至前一級之資料輸入端 及们接至後一級之資料輸出端22;每一解多工器均具 有兩個接至前-級之喊輸出端31及—健至後—級之回流 輸入端32 ; N個遮罩電路4Q ’於第—實施例巾係為四個（參閱第四 圖），每一遮罩電路4〇具有： [a] —個二對一多工器41，其具有兩個訊號輸入端411 、一訊號輸出端412及-切換選擇端413 ;其中一訊號輸入端 411係連接至該輸入部1〇，另_訊號輸入端财接至固定 之0值； [b] —由D型正反器構成之暫存部42，該暫存部42至 /具有一暫存部設定埠42S、一暫存部重設部42R、一暫存部 貝料輸入埠42D及一暫存器資料輸出埠4% ;該暫存部重設部 42R係用以讀入一重新啟動新循環信號（即信號）； [c] 一個NAND閘43 ;該NAND閘43至少具有一要求端 200833002 43卜一資料認可端432及一閘輸出端433 ;該要求端431係 連接至相對應之輸入部10之服務要求信號，該資料認可端432 係用以讀入後一級解多工器30傳回之資料認可訊號(GrantDeMUX) 'The total of M-level' is the first-and-a-half of the previous level. In the first implementation, since N=4 and M=2, it is divided into the first level (2) and the second level (1). (2) Every night work 2Q has two data input terminals connected to the previous level and the data output terminals 22 connected to the next level; each solution multiplexer has two shout outputs connected to the front-level The end 31 and the back-to-stage reflow input 32; the N mask circuits 4Q' are four in the first embodiment (see the fourth figure), and each mask circuit 4〇 has: [a] a two-to-one multiplexer 41 having two signal input terminals 411, a signal output terminal 412 and a switching selection terminal 413; wherein a signal input terminal 411 is connected to the input portion 1〇, and another signal input The terminal is connected to a fixed value of 0; [b] a temporary storage unit 42 composed of a D-type flip-flop, the temporary storage unit 42 to/having a temporary storage unit setting 42S and a temporary storage unit resetting unit 42R a temporary storage unit feed input 42D and a temporary register data output 埠 4%; the temporary storage unit reset unit 42R is used to read in a restart new cycle signal (ie, signal); [c] a NAND The NAND gate 43 has at least a request end 200833002 43 a data approval end 432 and a gate output end 433; the request end 431 is connected to a corresponding service request signal of the input unit 10, and the data approval end 432 is The data approval signal (Grant) used to read back the multiplexer 30
Signal)，該閘輸出端433則連接至該暫存部設定埠42s ; 複數個微型排程器電路50(Tiny Scheduler ,簡稱TS)， 如第五圖所示，共分成Μ級，後一級之數量係為前一級之一 半；在第一實施例中，由於Ν=4，Μ=2，所以分成第一級(2個） 與第二級（1個）；每一微型排程器電路50具有兩個連接到前 一級之要求輸入端501、一個連接到後一級之要求輸出端 502(簡稱Ζ· Req)及兩個選擇信號輸出端5〇3(分別連接至相鄰 之多工器20及解多工器30，簡稱MUX.sel); 更詳細的說’该微型排程器電路50包括一個或邏輯閘51 及一反相器52，其中，該或邏輯閘51之兩個輸入端係連接到 該要求輸入端501 ’該或邏輯閘51之輸出端則連接至該要求 輸出端502 ’且邊反相恭52之輸入係連接至該要求輸入端 501，而該反相器52之輸出係連接至兩個選擇信號輸出端5〇3; 一輸出部60 ’其係與最末級之多工器20之資料輸出端22 相連接；當將某一輸入部之資料接收完成時，則會發出一 資料認可訊號，並連接至最末級之解多工器30，經由相對應 之解多工器30使該遮罩電路40控制相對應之微型排程器電路 50的選擇信號輸出端503發出切換信號。 200833002 〜又’，在仲裁週期内之所有應被服務的輸入部ι〇都被服 務元後’最後-級賴型馳器電路5()之要求輸出端卿即 Z.Req)輸出便會為邏輯〇，此時所有遮罩電路仙的暫存部重 设部42R會收到這個邏輯〇信號，便會重新開啟服 新的仲裁週期。 又 藉此’來改善傳統分散式交換電路雜不具公平性，以及 輸出順序不同之缺點。 在第一實施例中，假設本發明之具公平性之分散式交換電 路具有四個輸入部1()(如第三及第四圖所示），則每一輸入部 10皆會配置-個遮罩電路4Q，其至少包括—個二對一多工器 41、一暫存部42(D型正反器）及一個NAND閘43，其中： ^亥輸入部1〇之服務要求信號(此叫⑺七Signai)係接到讀 二對一多工器41的其中一個訊號輸入端411，另一個訊號輪 入端411則固定設為「邏輯〇」，藉此讓下一級微型排程器電 路50(即TS電路)判斷服務要求的狀況； 該NAND閘43的要求端431是接到此遮罩電路40服務的 訊號輸入端411，至於NAND閘43的資料認可端432則是經由 解多工器30(DeMUX)的回流輸出端31，再經由NOT閘接到該魂 罩電路40之資料認可訊號(Grant signal)輸入。 另外’三個微型排程器電路50(如第五圖所示），係用來 接收及傳送服務要求信號(Request Signal)，並控制三個多工 12 200833002 益2〇及解多工器3〇 ’進而控制「f料」以及「資料認可訊號」 麟向^者’各個輸人部H)的資料匯流排直接連接到對應 多工器2〇進行資料交換；而三個解多工器30，則是用來傳 达貧料認可職至相對應之鮮 4()，進行财訊號輸入 端411服務要求之動作；而最後—級的微型排程器電路別的 要求輸出端502(即Z.Req輸出）’則接到所有遮罩電路4〇的 暫存部重設部42R (即Unmask輸入），使遮罩電路4()可以重 啟輸入端的服務。 請配合第七圖，本發明之動作原理詳細說明如下·· [步驟1]假設有編號0到3的四個輸入部1〇，此四個輸 入部ίο都要傳出資料（即路徑DU、D12、D13、D14動作）且都 提出服務要求（即路徑則卜R12、R13、R14動作），一開始， 該遮罩電路40裡的暫存部42(D型正反器）均被重置為〇，所 以暫存部42的暫存器資料輸出璋獨之輸出也為Q，該遮罩 電路40裡的暫存部42輸出會被該二對一多工器41切換到接 收服務要求處；所以，當編號〇之輸入部1〇提出服務要求時， 便可以通過遮罩電路4〇的二對一多工器41，往下一級之微型 排程器電路50前進（即路徑R21)。 [步驟2]通過該遮罩電路4〇之二對一多工器&的服務 要求，便進到了該微型排程器電路5〇中，該微型排程器電路 50會依知、苐六圖中的演算法，決定哪一個輸入的資料可以通 13 200833002 過由該微型排程器電路50所控制之多工器2〇,並同時將該解 多工器30切換至該輸入所屬路徑，使得資料認可訊號(GrantSignal), the gate output terminal 433 is connected to the temporary storage portion setting 埠 42s; a plurality of micro scheduler circuits 50 (Tiny Scheduler, referred to as TS), as shown in the fifth figure, are divided into Μ level, the latter level The number is one half of the previous stage; in the first embodiment, since Ν=4, Μ=2, it is divided into the first stage (2) and the second stage (1); each micro-schedule circuit 50 There are two required input terminals 501 connected to the previous stage, a required output end 502 connected to the next stage (referred to as Ζ·Req) and two selection signal output ends 5〇3 (connected to the adjacent multiplexer 20 respectively) The resolving multiplexer 30, referred to as MUX.sel); in more detail, the micro-scheduler circuit 50 includes an OR logic gate 51 and an inverter 52, wherein the two inputs of the OR logic gate 51 Is connected to the request input terminal 501 'the output of the logic gate 51 is connected to the request output terminal 502 ' and the input of the opposite phase switch 52 is connected to the request input terminal 501, and the inverter 52 is The output system is connected to two selection signal output terminals 5〇3; an output portion 60' is associated with the data of the last stage multiplexer 20. The output terminal 22 is connected; when the data of an input part is received, a data approval signal is sent and connected to the final stage multiplexer 30, and the corresponding multiplexer 30 is used to The mask circuit 40 controls the selection signal output terminal 503 of the corresponding micro-schedule circuit 50 to issue a switching signal. 200833002 ~ Again, all the input parts that should be served during the arbitration cycle are output by the service element, and the output of the final output of the final-level circuit (5) is Z.Req. Logic 〇, at this time, all the mask circuit reset section 42R will receive the logic 〇 signal, and will restart the new arbitration cycle. In turn, it is used to improve the disadvantages of traditional distributed switching circuits, such as fairness and different output sequences. In the first embodiment, assuming that the fairness decentralized switching circuit of the present invention has four input units 1() (as shown in the third and fourth figures), each input unit 10 will be configured with one The mask circuit 4Q includes at least a two-to-one multiplexer 41, a temporary storage portion 42 (D-type flip-flop), and a NAND gate 43, wherein: a service request signal of the input unit 1 Called (7) Seven Signai) is connected to one of the signal input terminals 411 of the two-to-one multiplexer 41, and the other signal wheel-in terminal 411 is fixed to "logic", thereby allowing the next-stage micro-scheduler circuit 50 (ie, the TS circuit) determines the status of the service request; the request terminal 431 of the NAND gate 43 is connected to the signal input terminal 411 served by the mask circuit 40, and the data approval terminal 432 of the NAND gate 43 is demultiplexed. The return output 31 of the device 30 (DeMUX) is connected to the Grant signal input of the soul mask circuit 40 via the NOT gate. In addition, 'three micro-scheduler circuits 50 (as shown in the fifth figure) are used to receive and transmit the request signal (Request Signal), and control three multiplexes 12 200833002 yi 2 〇 multiplexer 3 〇' and then control the "f material" and "data approval signal" The data bus of the squadron 'the input unit H' is directly connected to the corresponding multiplexer 2 for data exchange; and the three multiplexers 30 , is used to convey the poor material approval to the corresponding fresh 4 (), the action of the financial number input 411 service requirements; and the final - level micro-relay circuit requires the output 502 (ie Z The .Req output)' is connected to the temporary storage portion reset unit 42R (i.e., Unmask input) of all the mask circuits 4, so that the mask circuit 4() can restart the service of the input terminal. Please refer to the seventh figure, the operation principle of the present invention is described in detail below. [Step 1] Assume that there are four input units 1 to 0, and the four input units ίο have to transmit data (ie, path DU, D12, D13, D14 action) and all request service (that is, the path is R12, R13, R14 action), initially, the temporary storage part 42 (D-type flip-flop) in the mask circuit 40 is reset Therefore, the output of the temporary data output of the temporary storage unit 42 is also Q, and the output of the temporary storage unit 42 in the mask circuit 40 is switched to the receiving service request by the two-to-one multiplexer 41. Therefore, when the input unit 1 of the number 〇 requests the service request, the two-to-one multiplexer 41 of the mask circuit 4 can be advanced to the micro-schedule circuit 50 of the next stage (ie, the path R21). [Step 2] The service request of the two-to-one multiplexer & amp of the mask circuit 4 is entered into the micro-schedule circuit 5 ,, the micro-schedule circuit 50 will be known, The algorithm in the figure determines which input data can pass through the multiplexer 2 controlled by the micro-scheduler circuit 50, and simultaneously switches the de-multiplexer 30 to the path to which the input belongs. Make the data approval signal (Grant
Signal)可以正確的回到所應該到達的遮罩電路4〇，以啟動遮 罩功能。 如第五圖所示’如果該微型排程器電路5〇的兩個要求輸 入端5G1(_ A及B)都有提出要求，那麼位於上方的要求^ 入端501(也可以講是a輸入端）’其資料可以先通過該多工器 I即Z相為i Mux Sel為〇 ;如果是上面的要求輸入端 50U也可以講是a輸人端)提出要求，而下面的要求輸入端 501(也可辑是B輸人端）沒有提㈣求，職社方的要求 輸入端5〇1，其資料可以先通過該多工器2〇，即z. _為工且 Mux Sel為〇 ;如果是下面的要求輸入端5〇ι提出要求而上面 的要求輸入端5G1沒有，則位於下方的要求輸入端5()ι， 料就可以通過該多工器2G，即❿為丨且仙伽為^如 果這兩個要麵人端5_及咖沒_要求，那麼該微 型排程器電⑽㈣往下—級提峨，所 〇 且Mux Sel為卜 0 微型排㈣電路5G的服務 ::吻到下-級的微型排程器電路_^ _叫’可以通過該微型排程器電路5〇控_多卫 之輸入端㈣便也會_彳績進（即職_，就_ 200833002 著一級直到該輸出部60 ;資料流向路徑為D11=>D21=〉D31 ;以 及服務要求之流向路徑為R11=>R2»R31=>R41。 [步驟3]當該輸出部60接收到傳遞過來的資料之後，便 會回送一個資料認可訊號(Grant Signal)，此資料認可訊號便 會經過G31=>G21=>G11之路徑往回傳遞，先前該微型排程器電 路50已經切換好該解多工器30之選擇路徑，所以該資料認可 訊號(Grant Signal)便可以正確無誤的回到當初被服務的輸 入部10之遮罩電路40(即路徑G31=>G21=>G11)。當資料認可 訊號到達該遮罩電路40後，該遮罩電路4〇便啟動遮罩功能， 如第四圖中一對一之多工器41的路徑便會切換到邏輯〇(即 Const· 0)輸出，也就是遮罩電路會輸出〇給下一級的微型 排私為電路5G，所以該輸人的服務要求訊號便無法通過遮罩 電路40到達微型排程器電路5G。因此，下—級的微型排程器 電路50就會服務另外一個輸入，即編號i之輸入部ι〇，同時 也會將其所控制的多工器2G及解多玉器3G重新切換，讓新的 輸入部10的資料可以通過（變成路徑㈣>D21=观）；傳完 後’即迎接下一個資料認可訊號的來臨(變成路徑 G31:>G21：=>G12); #舰丨之輪人㈣對應之鮮電路㈣ 2遮罩功能後，則R21及R22均變成Q，且該微型排程器電 要錢人端5_及B)均為Q，使得該微藝程器電路 之要求輪出端502(即Z.Req.)為〇。 200833002 剩下的服務也會依照前述[步驟1〜步驟3]的流程，資料先 由編號2之輸入部10由路徑D13=>D22=D31，傳完後，資料認 可訊號之路徑為G31=>G22=>G13，然後將此相對應之遮罩電路 40也啟動遮罩功能；最後，進行編號3之輸入部1〇之資料傳 送，資料路徑為D14=>D22=>D31，傳完後，資料認可訊號之路 徑為G31=>G22=>G14 ;因此，在同一個仲裁週期内被公平的服 務0 最後，當在仲裁週期内之所有應被服務的輸入部1〇都被 服務完後，最後-級的微型排程器電路5()之要求輸出端 502(即Z.Req)輪出便會為邏輯〇，此時所有遮罩電路的暫 存部重設部42R會收到這個邏輯〇jf號（路捏 .勝勝MM) ’便會靖職祕，展騎的仲裁週期。 換言之，每當最後-級的微型排程器電路5()之要求輸出端 502(Z.两信號)-旦為邏輯Q，便代表該次的仲裁週期 接著回到-壯的狀態’繼續下—個仲裁週期。 此外，在特殊情形下，如果仲裁週綱辦，某—輪 10未提出要求，例如假設編號為丨的輸人部丨 開始時沒有提出要求，那麼編號^部H)的服週期 便為邏輯〇’此邏輯Q信號會輸人到遮罩魏^破 ⑽’並立即啟動遮罩功能，接著該遮罩=入 之多工器41輸出馬上切換到一出;因 200833002 週期尚未結束前’就算、錢丨之輸人部1G提統務要求，也 會因為遮單功能已經啟動，而無法獲得服務機會。 換5之’只要仲裁週期—開始沒有提出要求的輸入部. 在該仲裁週齡束前’即沒有姆的機會。如此-來便可解決 插隊的問題，也不會影響到輸出的順序。 因此’由於本發明增力口了一個遮罩電路⑽sk虹）來處 =此種情形；在同-個仲__，如果有訊號輸人端持續的 提出要求，_該鮮電路將只允許該職輸人端被服務- 次；該訊號輸入端被服務過後，如果這—個仲裁週期尚未結 束那麼肖個訊號輸入端所再提出的服務要求，就會被遮罩 電路播下；直到該仲裁週期結束，遮罩電路才會再服務該訊號 輸入端。 於遮罩電路的維護下，在同—件裁週期内提出服務要求的 訊號輸入m獲得—次的服務，直細_期結束； 不但如此’仲___，未細___入端， 在耕裁週縣結絲，轉提出服務要求，也會被遮罩電路 所擋下；因此’透過遮罩電路的運作，便可以克服訊號輸入端 持續提出縣㈣況，不會再仏請裁不公相及某輸入端插 隊的情形發生。 ，此為本發明之第二實施 共分成三級；此時，該多 同理，若輸入部1〇之數量為; 例（圖中未示），即]，所以.3， 200833002 工器20與該解多工器30分別是4削=7個，該遮軍電路4〇 則為8個，而該微型排程器電路5〇則是7個；整體之電路不 會變得太複雜。故’單純之數量增加(例如，64，128·..)， 亦在本發明之保護範圍内。 綜上所述，本發明之優點及功效可歸納為： [1] 集中式演算法之公平性。本發明囊括f知兩類仲裁演 算法的優點’經由微型排織電路以及輕電路的搭配，使得 本案不但财分散式演算法的低複雜度，也兼備了集 中式演算法之公平性。 $ [2] 可以避免後到之輸入資料插隊之情形。在同一仲裁週 期内提出服務要求的訊號輸人端，朗此仲裁週麟束，均只 能獲得-次的服務’亦即，透過該遮罩電路的運作，便可以克 服訊號輸人端持續提出要求的情況，不會再出現及某個後到之 几5虎輸入端插隊的情形發生。 [3] 模組化的設計使交換佈設料。本創 之設計’且該遮罩電路触型排程器電路均由簡單的電子元件 組成’因此’即使輸入部之數量增加為8、16、32或更高，交 換電路之佈設仍屬簡易電路。故，化的設計使交換 以上僅是藉由較佳實施解細制本㈣，對於該實施例 所做的任何簡單修改與·，料脫離本發明之精神與範圍。 200833002 由以上詳細說明，可使熟知本項技藝者明瞭本發明的確可 達成前述目的，實已符合專利法之規定，紐出發料利申請。 【圖式簡單說明】 第一 A圖係第一種習知技術之示意圖 第- B圖係第-種習知技術之典型範例之示意圖 第- C圖係第-種習知技術之典型範例之傳遞過程之示意圖 第一 A圖係第二種習知技術之示意圖 第二B圖係第二種習知技術之典型範例之示意圖 第二C圖係第二種習知技術之典型範例之傳遞過程之示意圖 第三圖係本發明之第一實施例之電路架構示意圖 第四圖係本發明之遮罩電路之電路圖 第五圖係本發明之微型排程器電路之電路圖 第六圖係本發明之微型排程器電路之演算法示音圖 第七圖係本發明之第一實施例之動作示意圖 19 200833002 【主要元件符號說明】 10輸入部 21資料輸入端 30解多工器 32回流輸入端 41二對一多工器 411訊號輸入端 413切換選擇端 42R暫存部重設部 42Q暫存器資料輸出埠 431要求端 433閘輸出端 501要求輸入端 503選擇信號輸出端 52反相器 81A、81B、81C、81D、81E 82、92多工器 84、94仲裁器 、D12、D13、D14、D2卜 G2卜 G22、G3卜 Rll、R12、 R4卜 Ul、U2、U3、U4 路徑 20多工器 22資料輸出端 31回流輸出端 40遮罩電路 42暫存部 412訊5虎輸出端 42S暫存部設定埠 42D暫存部資料輪入埠 43NAND 閘 432資料認可端 50微型排程器電路 502要求輸出端 51或邏輯閘 60輸出部 81F、81G、81H、91 輪入端 83、93輸出點 D22、D3hGll、G12、G13、G14、 R13、R14、R2 卜 R22、R3卜 R32、 20Signal) can correctly return to the mask circuit 4 that should be reached to activate the mask function. As shown in the fifth figure, 'if the two required input terminals 5G1 (_A and B) of the micro-schedule circuit 5 are required, then the upper input terminal 501 (also referred to as an input) End) 'The data can be first passed through the multiplexer I, that is, the Z phase is i Mux Sel; if the above input input 50U can also be said to be a input terminal), the following request input 501 (Also can be B loses the end) No mention is made (4), the input of the professional party is 5〇1, and the data can be passed through the multiplexer 2, ie z. _ for work and Mux Sel for 〇; If the following input input terminal 5〇1 is requested and the above input input terminal 5G1 is not available, then the lower input request terminal 5() ι, the material can pass through the multiplexer 2G, that is, ❿ 丨 and 仙 伽^ If the two faces are 5_ and the coffee is not required, then the micro-schedule is powered by (10) (four) down-level, and the Mux Sel is the service of the micro-disc (4) circuit 5G:: Kiss to the lower-level micro-schedule circuit _^ _call 'can be controlled by the micro-schedule circuit 5 _ multi-wei input (four) will also _ 进 进(i.e., _200833002 is level one until the output unit 60; the data flow path is D11=>D21=>D31; and the service request flow path is R11=>R2»R31=>R41. 3] When the output unit 60 receives the transmitted data, it will send back a data identification signal (Grant Signal), and the data approval signal will be transmitted back through the path of G31=>G21=>G11, previously The micro-scheduler circuit 50 has switched the selection path of the demultiplexer 30, so that the Grant Signal can be returned to the mask circuit 40 of the input unit 10 that was originally served correctly (ie, Path G31=>G21=>G11). When the data approval signal reaches the mask circuit 40, the mask circuit 4 starts the mask function, such as the one-to-one multiplexer 41 in the fourth figure. The path will switch to the logical 〇 (ie, Const· 0) output, that is, the mask circuit will output 〇 to the next stage of micro-disposal as circuit 5G, so the input service request signal cannot be reached through the mask circuit 40. Micro-schedule circuit 5G. Therefore, the lower-level micro-distributor 50 will serve another input, namely the input part ι of the number i, and will also switch the multiplexer 2G and the multi-jade 3G controlled by it, so that the data of the new input part 10 can pass (become the path) (4) >D21=View); After the completion of the message, the next data acknowledgement signal is coming (becomes the path G31:>G21:=>G12);#船丨之人 (4) corresponds to the fresh circuit (4) 2 mask After the function, both R21 and R22 become Q, and the micro-distributor is required to have both Q_ and B) Q, so that the micro-instrument circuit requires the round end 502 (ie Z.Req. ) is awkward. 200833002 The remaining services will also follow the above [Step 1 to Step 3] flow. The data is first entered by the input unit 10 of the number 2 by the path D13=>D22=D31. After the transfer, the path of the data approval signal is G31= >G22=>G13, and then the corresponding mask circuit 40 also starts the mask function; finally, the data transmission of the input unit 1 of the number 3 is performed, and the data path is D14=>D22=>D31 After the transmission, the path of the data approval signal is G31=>G22=>G14; therefore, it is fair service in the same arbitration period. Finally, when all the input parts 1 should be served in the arbitration period After the service is completed, the required output 502 (ie, Z.Req) of the final-stage micro-scheduler circuit 5() will be logically 〇, and the temporary storage of all the mask circuits is reset. Department 42R will receive this logic 〇jf number (road pinch. Victory MM) 'will be acquainted with the secret, the ride cycle of the ride. In other words, whenever the required output 502 (Z. two signals) of the last-stage micro-scheduler circuit 5() is a logical Q, it represents the arbitration period of the next and then returns to the -strong state. - an arbitration cycle. In addition, in special circumstances, if the Arbitration Week Office does not request a certain wheel 10, for example, if the input department numbered 丨 is not requested at the beginning, then the service period of the number H) is logical 〇 'This logic Q signal will be input to the mask Wei ^ broken (10)' and immediately start the mask function, then the mask = input multiplexer 41 output immediately switches to one out; because the 200833002 cycle has not ended before 'even, Qian Yizhi’s 1G request for general affairs will also be unable to obtain service opportunities because the cover function has been activated. For the 5th 'as long as the arbitration cycle - the beginning of the request is not made. Before the arbitrage of the squad, there is no chance. In this way, the problem of cutting the queue can be solved without affecting the order of the output. Therefore, 'the present invention enhances the mouth of a mask circuit (10) sk rainbow) = this situation; in the same - zhong __, if there is a signal input end of the request, _ the fresh circuit will only allow The service input is serviced - times; after the signal input is serviced, if the arbitration period is not over, then the service request re-submitted by the signal input will be broadcasted by the mask circuit; until the arbitration At the end of the cycle, the mask circuit will then serve the signal input. Under the maintenance of the mask circuit, the signal input m of the service request is obtained in the same period of the cut-off period to obtain the service of the service, and the end of the period is short; not only the 'zhong___, but not the ___ input, Cultivating Zhouxian County silk, turning to service requirements, will also be blocked by the mask circuit; therefore, 'through the operation of the mask circuit, you can overcome the signal input end to continue to raise the county (four) situation, no longer ask for injustice The situation occurs when a certain input is inserted into the queue. The second implementation of the present invention is divided into three levels; at this time, the multi-simultaneity, if the number of the input unit 1 is; (example not shown), ie], so .3, 200833002 The demultiplexer 30 is 4 cut = 7 respectively, the cover circuit 4 is 8 and the micro scheduler circuit 5 is 7; the overall circuit does not become too complicated. Therefore, the simple increase in the number (for example, 64, 128·..) is also within the protection scope of the present invention. In summary, the advantages and effects of the present invention can be summarized as follows: [1] The fairness of the centralized algorithm. The present invention encompasses the advantages of the two types of arbitration algorithms. The combination of micro-disposing circuits and light circuits makes the case not only low complexity of the distributed algorithm, but also the fairness of the centralized algorithm. $ [2] can avoid the situation when the input data is cut in. In the same arbitration cycle, the signal input terminal of the service request is issued, and the arbitration Zhou Lingshu can only obtain the service - that is, through the operation of the mask circuit, the signal input terminal can be overcome continuously. The requested situation will not occur again and a certain number of 5 tiger input will be inserted into the queue. [3] The modular design allows for the exchange of materials. The design of the invention' and the mask circuit type tracker circuit are composed of simple electronic components. Therefore, even if the number of input parts is increased to 8, 16, 32 or higher, the switching circuit is still a simple circuit. . Therefore, the design of the present invention is made by the preferred embodiment of the present invention, and any simple modifications and improvements made to the embodiment are omitted from the spirit and scope of the present invention. 200833002 From the above detailed description, it will be apparent to those skilled in the art that the present invention can achieve the foregoing objects and is in accordance with the provisions of the Patent Law. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A is a schematic diagram of a first conventional technique. FIG. B is a schematic diagram of a typical example of the first conventional technique. FIG. C is a typical example of the first conventional technique. Schematic diagram of the transfer process The first A diagram is a schematic diagram of the second conventional technique, the second B diagram is a schematic diagram of a typical example of the second conventional technique, and the second C diagram is a transmission process of a typical example of the second conventional technique. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 3 is a circuit diagram of a first embodiment of the present invention. FIG. 4 is a circuit diagram of a mask circuit of the present invention. FIG. 5 is a circuit diagram of a micro-schedule circuit of the present invention. The algorithm of the micro-schedule circuit is shown in the seventh embodiment of the present invention. The operation diagram of the first embodiment of the present invention is shown in the following figure: 200833002 [Description of main component symbols] 10 input section 21 data input terminal 30 demultiplexer 32 reflow input terminal 41 Two-to-one multiplexer 411 signal input terminal 413 switching selection terminal 42R temporary storage portion resetting portion 42Q register data output 431 431 request terminal 433 gate output terminal 501 requires input terminal 503 to select signal output terminal 52 inverter 81A, 81B 81C, 81D, 81E 82, 92 multiplexer 84, 94 arbitrator, D12, D13, D14, D2 Bu G2 Bu G22, G3 Bu Rll, R12, R4 Bu Ul, U2, U3, U4 Path 20 multiplexer 22 Data output terminal 31 reflow output terminal 40 mask circuit 42 temporary storage unit 412 signal 5 tiger output terminal 42S temporary storage portion setting 埠 42D temporary storage portion data wheel 埠 43 NAND gate 432 data approval terminal 50 micro-schedule circuit 502 requires output Terminal 51 or logic gate 60 output portion 81F, 81G, 81H, 91 wheel terminal 83, 93 output point D22, D3hG11, G12, G13, G14, R13, R14, R2, R22, R3, R32, 20