DE69938621D1 - Befehlausgabe in einem Rechner - Google Patents

Befehlausgabe in einem Rechner

Info

Publication number
DE69938621D1
DE69938621D1 DE69938621T DE69938621T DE69938621D1 DE 69938621 D1 DE69938621 D1 DE 69938621D1 DE 69938621 T DE69938621 T DE 69938621T DE 69938621 T DE69938621 T DE 69938621T DE 69938621 D1 DE69938621 D1 DE 69938621D1
Authority
DE
Germany
Prior art keywords
computer
command output
command
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69938621T
Other languages
English (en)
Inventor
Andrew Cofler
Laurent Ducousso
Bruno Fel
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Original Assignee
STMicroelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SA filed Critical STMicroelectronics SA
Application granted granted Critical
Publication of DE69938621D1 publication Critical patent/DE69938621D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3853—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution of compound instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3858—Result writeback, i.e. updating the architectural state or memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
DE69938621T 1999-05-03 1999-05-03 Befehlausgabe in einem Rechner Expired - Lifetime DE69938621D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP99410058A EP1050808B1 (de) 1999-05-03 1999-05-03 Befehlausgabe in einem Rechner

Publications (1)

Publication Number Publication Date
DE69938621D1 true DE69938621D1 (de) 2008-06-12

Family

ID=8242261

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69938621T Expired - Lifetime DE69938621D1 (de) 1999-05-03 1999-05-03 Befehlausgabe in einem Rechner

Country Status (4)

Country Link
US (1) US7281119B1 (de)
EP (1) EP1050808B1 (de)
JP (1) JP2000330790A (de)
DE (1) DE69938621D1 (de)

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US8327115B2 (en) 2006-04-12 2012-12-04 Soft Machines, Inc. Plural matrices of execution units for processing matrices of row dependent instructions in single clock cycle in super or separate mode
EP2527972A3 (de) 2006-11-14 2014-08-06 Soft Machines, Inc. Vorrichtung und Verfahren zum Verarbeiten von komplexen Anweisungsformaten in einer Multi-Thread-Architektur, die verschiedene Kontextschaltungsmodi und Visualisierungsschemen unterstützt
US8006114B2 (en) * 2007-03-09 2011-08-23 Analog Devices, Inc. Software programmable timing architecture
US7984272B2 (en) 2007-06-27 2011-07-19 International Business Machines Corporation Design structure for single hot forward interconnect scheme for delayed execution pipelines
US7769987B2 (en) 2007-06-27 2010-08-03 International Business Machines Corporation Single hot forward interconnect scheme for delayed execution pipelines
WO2009000624A1 (en) * 2007-06-27 2008-12-31 International Business Machines Corporation Forwarding data in a processor
US7877579B2 (en) * 2008-02-19 2011-01-25 International Business Machines Corporation System and method for prioritizing compare instructions
US20090210677A1 (en) * 2008-02-19 2009-08-20 Luick David A System and Method for Optimization Within a Group Priority Issue Schema for a Cascaded Pipeline
US20090210666A1 (en) * 2008-02-19 2009-08-20 Luick David A System and Method for Resolving Issue Conflicts of Load Instructions
US7870368B2 (en) * 2008-02-19 2011-01-11 International Business Machines Corporation System and method for prioritizing branch instructions
US8108654B2 (en) * 2008-02-19 2012-01-31 International Business Machines Corporation System and method for a group priority issue schema for a cascaded pipeline
US20090210672A1 (en) * 2008-02-19 2009-08-20 Luick David A System and Method for Resolving Issue Conflicts of Load Instructions
US7996654B2 (en) * 2008-02-19 2011-08-09 International Business Machines Corporation System and method for optimization within a group priority issue schema for a cascaded pipeline
US7984270B2 (en) * 2008-02-19 2011-07-19 International Business Machines Corporation System and method for prioritizing arithmetic instructions
US7882335B2 (en) * 2008-02-19 2011-02-01 International Business Machines Corporation System and method for the scheduling of load instructions within a group priority issue schema for a cascaded pipeline
US20090210669A1 (en) * 2008-02-19 2009-08-20 Luick David A System and Method for Prioritizing Floating-Point Instructions
US7865700B2 (en) * 2008-02-19 2011-01-04 International Business Machines Corporation System and method for prioritizing store instructions
US8095779B2 (en) * 2008-02-19 2012-01-10 International Business Machines Corporation System and method for optimization within a group priority issue schema for a cascaded pipeline
JP2010160600A (ja) * 2009-01-07 2010-07-22 Yamatake Corp 情報処理装置、スケジューラ、及びスケジューリング方法
JP2010257199A (ja) * 2009-04-24 2010-11-11 Renesas Electronics Corp プロセッサ及びプロセッサにおける命令発行の制御方法
GB2487684B (en) * 2009-11-16 2016-09-14 Ibm Method for scheduling plurality of computing processes including all-to-all (a2a) communication across plurality of nodes (processors) constituting network, p
KR101685247B1 (ko) 2010-09-17 2016-12-09 소프트 머신즈, 인크. 조기 원거리 분기 예측을 위한 섀도우 캐시를 포함하는 단일 사이클 다중 분기 예측
EP2689326B1 (de) 2011-03-25 2022-11-16 Intel Corporation Speicherfragmente zur unterstützung einer codeblockausführung mittels durch partitionierbare engines realisierter virtueller kerne
TWI603198B (zh) 2011-05-20 2017-10-21 英特爾股份有限公司 以複數個引擎作資源與互連結構的分散式分配以支援指令序列的執行
WO2013077876A1 (en) 2011-11-22 2013-05-30 Soft Machines, Inc. A microprocessor accelerated code optimizer
EP2783280B1 (de) 2011-11-22 2019-09-11 Intel Corporation Beschleunigter codeoptimierer für einen mehrmotor-mikroprozessor
US9558003B2 (en) * 2012-11-29 2017-01-31 Samsung Electronics Co., Ltd. Reconfigurable processor for parallel processing and operation method of the reconfigurable processor
WO2014150991A1 (en) 2013-03-15 2014-09-25 Soft Machines, Inc. A method for implementing a reduced size register view data structure in a microprocessor
EP2972845B1 (de) 2013-03-15 2021-07-07 Intel Corporation Verfahren zur ausführung von in blöcken gruppierten befehlen aus mehreren threads
US9811342B2 (en) 2013-03-15 2017-11-07 Intel Corporation Method for performing dual dispatch of blocks and half blocks
US9569216B2 (en) 2013-03-15 2017-02-14 Soft Machines, Inc. Method for populating a source view data structure by using register template snapshots
CN105247484B (zh) 2013-03-15 2021-02-23 英特尔公司 利用本地分布式标志体系架构来仿真访客集中式标志体系架构的方法
US10275255B2 (en) 2013-03-15 2019-04-30 Intel Corporation Method for dependency broadcasting through a source organized source view data structure
US9904625B2 (en) 2013-03-15 2018-02-27 Intel Corporation Methods, systems and apparatus for predicting the way of a set associative cache
US10140138B2 (en) 2013-03-15 2018-11-27 Intel Corporation Methods, systems and apparatus for supporting wide and efficient front-end operation with guest-architecture emulation
WO2014150806A1 (en) 2013-03-15 2014-09-25 Soft Machines, Inc. A method for populating register view data structure by using register template snapshots
KR102179385B1 (ko) * 2013-11-29 2020-11-16 삼성전자주식회사 명령어를 실행하는 방법 및 프로세서, 명령어를 부호화하는 방법 및 장치 및 기록매체

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JP2810068B2 (ja) * 1988-11-11 1998-10-15 株式会社日立製作所 プロセッサシステム、コンピュータシステム及び命令処理方法
CA2016068C (en) * 1989-05-24 2000-04-04 Robert W. Horst Multiple instruction issue computer architecture
JP2911278B2 (ja) * 1990-11-30 1999-06-23 松下電器産業株式会社 プロセッサ
JP2874351B2 (ja) * 1991-01-23 1999-03-24 日本電気株式会社 並列パイプライン命令処理装置
US5408658A (en) * 1991-07-15 1995-04-18 International Business Machines Corporation Self-scheduling parallel computer system and method
EP0551090B1 (de) * 1992-01-06 1999-08-04 Hitachi, Ltd. Rechner mit einer Parallelverarbeitungsfähigkeit
JP3146707B2 (ja) * 1992-01-06 2001-03-19 株式会社日立製作所 並列演算機能を有する計算機
US5416913A (en) * 1992-07-27 1995-05-16 Intel Corporation Method and apparatus for dependency checking in a multi-pipelined microprocessor
JPH0793152A (ja) * 1993-09-20 1995-04-07 Fujitsu Ltd マイクロプロセッサ制御装置
EP1338957A3 (de) * 1993-11-05 2003-10-29 Intergraph Corporation Superskalare Rechnerarchitektur mit Softwareplanung
WO1995022102A1 (en) * 1994-02-08 1995-08-17 Meridian Semiconductor, Inc. Method and apparatus for simultaneously executing instructions in a pipelined microprocessor
US5727177A (en) * 1996-03-29 1998-03-10 Advanced Micro Devices, Inc. Reorder buffer circuit accommodating special instructions operating on odd-width results
JPH09274567A (ja) * 1996-04-08 1997-10-21 Hitachi Ltd プログラムの実行制御方法及びそのためのプロセッサ
JP3745450B2 (ja) * 1996-05-13 2006-02-15 株式会社ルネサステクノロジ 並列処理プロセッサ
US5832205A (en) * 1996-08-20 1998-11-03 Transmeta Corporation Memory controller for a microprocessor for detecting a failure of speculation on the physical nature of a component being addressed
US6170051B1 (en) * 1997-08-01 2001-01-02 Micron Technology, Inc. Apparatus and method for program level parallelism in a VLIW processor
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Also Published As

Publication number Publication date
EP1050808B1 (de) 2008-04-30
JP2000330790A (ja) 2000-11-30
US7281119B1 (en) 2007-10-09
EP1050808A1 (de) 2000-11-08

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Legal Events

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