JP2003186824A - バス使用権優先度調整装置およびシステム - Google Patents

バス使用権優先度調整装置およびシステム

Info

Publication number
JP2003186824A
JP2003186824A JP2001384698A JP2001384698A JP2003186824A JP 2003186824 A JP2003186824 A JP 2003186824A JP 2001384698 A JP2001384698 A JP 2001384698A JP 2001384698 A JP2001384698 A JP 2001384698A JP 2003186824 A JP2003186824 A JP 2003186824A
Authority
JP
Japan
Prior art keywords
bus
interval
slave
master device
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001384698A
Other languages
English (en)
Japanese (ja)
Other versions
JP2003186824A5 (enExample
Inventor
Takashi Fujiwara
隆史 藤原
Atsushi Date
厚 伊達
Noboru Yokoyama
登 横山
Katsunori Kato
勝則 加藤
Tadaaki Maeda
忠昭 前田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP2001384698A priority Critical patent/JP2003186824A/ja
Priority to US10/314,285 priority patent/US6952747B2/en
Priority to CNB021570140A priority patent/CN1271534C/zh
Publication of JP2003186824A publication Critical patent/JP2003186824A/ja
Priority to US11/110,667 priority patent/US7380034B2/en
Publication of JP2003186824A5 publication Critical patent/JP2003186824A5/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/3625—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using a time dependent access
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/364—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
JP2001384698A 2001-12-18 2001-12-18 バス使用権優先度調整装置およびシステム Pending JP2003186824A (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2001384698A JP2003186824A (ja) 2001-12-18 2001-12-18 バス使用権優先度調整装置およびシステム
US10/314,285 US6952747B2 (en) 2001-12-18 2002-12-09 Method of delaying bus request signals to arbitrate for bus use and system therefor
CNB021570140A CN1271534C (zh) 2001-12-18 2002-12-18 总线使用请求的调整方法及其系统
US11/110,667 US7380034B2 (en) 2001-12-18 2005-04-21 Method of arbitration for bus use request and system therefor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001384698A JP2003186824A (ja) 2001-12-18 2001-12-18 バス使用権優先度調整装置およびシステム

Publications (2)

Publication Number Publication Date
JP2003186824A true JP2003186824A (ja) 2003-07-04
JP2003186824A5 JP2003186824A5 (enExample) 2005-07-28

Family

ID=19187747

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001384698A Pending JP2003186824A (ja) 2001-12-18 2001-12-18 バス使用権優先度調整装置およびシステム

Country Status (3)

Country Link
US (2) US6952747B2 (enExample)
JP (1) JP2003186824A (enExample)
CN (1) CN1271534C (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8065458B2 (en) 2006-06-15 2011-11-22 Sony Corporation Arbitration apparatus, method, and computer readable medium with dynamically adjustable priority scheme
JP2018185762A (ja) * 2017-04-27 2018-11-22 キヤノン株式会社 転送装置、転送方法および複合機

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003186824A (ja) * 2001-12-18 2003-07-04 Canon Inc バス使用権優先度調整装置およびシステム
JP4217452B2 (ja) * 2002-09-30 2009-02-04 キヤノン株式会社 プロセッサシステム
JP4181839B2 (ja) * 2002-09-30 2008-11-19 キヤノン株式会社 システムコントローラ
JP2004126646A (ja) 2002-09-30 2004-04-22 Canon Inc バス制御方法
JP2005063358A (ja) * 2003-08-20 2005-03-10 Matsushita Electric Ind Co Ltd 命令供給制御装置および半導体装置
CN100375448C (zh) * 2005-11-04 2008-03-12 北京和利时系统工程股份有限公司 一种避免冗余主站对串行总线链路访问冲突的方法
DE102009027625A1 (de) * 2009-07-10 2011-01-13 Robert Bosch Gmbh Elektrische Schaltung zur Übertragung von Signalen zwischen zwei Mastern und einem oder mehreren Slaves
JP5503365B2 (ja) * 2010-03-25 2014-05-28 キヤノン株式会社 デバイス管理システム、管理装置、デバイス管理方法及びプログラム
US8386682B2 (en) * 2010-06-30 2013-02-26 Intel Corporation Method, apparatus and system for maintaining transaction coherecy in a multiple data bus platform
KR101855399B1 (ko) * 2011-03-24 2018-05-09 삼성전자주식회사 데이터 트래픽을 개선한 ＳｏＣ 및 이의 동작 방법
JP2014016730A (ja) * 2012-07-06 2014-01-30 Canon Inc バス調停装置、バス調停方法、及びコンピュータプログラム
CN106598888B (zh) * 2016-12-22 2019-07-12 广东威创视讯科技股份有限公司 一种采用rs485协议的多板卡通讯系统及方法
US10496577B2 (en) 2017-02-09 2019-12-03 Hewlett Packard Enterprise Development Lp Distribution of master device tasks among bus queues
US11520725B2 (en) * 2020-05-15 2022-12-06 Nxp Usa, Inc. Performance monitor for interconnection network in an integrated circuit

Family Cites Families (19)

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US3820081A (en) * 1972-10-05 1974-06-25 Honeywell Inf Systems Override hardware for main store sequencer
US3821709A (en) * 1972-10-05 1974-06-28 Honeywell Inf Systems Memory storage sequencer
US4759965A (en) * 1985-08-06 1988-07-26 Canon Kabushiki Kaisha Ceramic, preparation thereof and electronic circuit substrate by use thereof
JP2529720B2 (ja) 1988-06-17 1996-09-04 富士通株式会社 ダイレクトメモリアクセス装置
US4972313A (en) * 1989-08-07 1990-11-20 Bull Hn Information Systems Inc. Bus access control for a multi-host system using successively decremented arbitration delay periods to allocate bus access among the hosts
JPH03263159A (ja) 1990-03-13 1991-11-22 Nec Corp バス獲得要求生成方式
JP2986176B2 (ja) * 1990-05-11 1999-12-06 株式会社日立製作所 バス権制御方式およびバスシステム
BR9509778A (pt) * 1994-11-28 1997-09-30 Analogic Corp Sistema de imagem médica para uso em ups
US5572686A (en) * 1995-06-05 1996-11-05 Apple Computer, Inc. Bus arbitration scheme with priority switching and timer
US5862353A (en) * 1997-03-25 1999-01-19 International Business Machines Corporation Systems and methods for dynamically controlling a bus
US6189076B1 (en) * 1997-11-14 2001-02-13 Lucent Technologies, Inc. Shared synchronous memory with a switching circuit controlled by an arbiter and method for glitch free switching of a clock signal
US6275890B1 (en) * 1998-08-19 2001-08-14 International Business Machines Corporation Low latency data path in a cross-bar switch providing dynamically prioritized bus arbitration
JP2000211210A (ja) * 1999-01-25 2000-08-02 Canon Inc 複合機器の制御装置及び方法
US6772254B2 (en) * 2000-06-21 2004-08-03 International Business Machines Corporation Multi-master computer system with overlapped read and write operations and scalable address pipelining
US6745273B1 (en) * 2001-01-12 2004-06-01 Lsi Logic Corporation Automatic deadlock prevention via arbitration switching
JP4916059B2 (ja) 2001-07-31 2012-04-11 キヤノン株式会社 画像処理装置
JP2003186824A (ja) * 2001-12-18 2003-07-04 Canon Inc バス使用権優先度調整装置およびシステム
US6880028B2 (en) * 2002-03-18 2005-04-12 Sun Microsystems, Inc Dynamic request priority arbitration
US20030229743A1 (en) * 2002-06-05 2003-12-11 Brown Andrew C. Methods and structure for improved fairness bus arbitration

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8065458B2 (en) 2006-06-15 2011-11-22 Sony Corporation Arbitration apparatus, method, and computer readable medium with dynamically adjustable priority scheme
JP2018185762A (ja) * 2017-04-27 2018-11-22 キヤノン株式会社 転送装置、転送方法および複合機

Also Published As

Publication number Publication date
US7380034B2 (en) 2008-05-27
US6952747B2 (en) 2005-10-04
CN1427352A (zh) 2003-07-02
US20030115392A1 (en) 2003-06-19
US20050188139A1 (en) 2005-08-25
CN1271534C (zh) 2006-08-23

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