CN1271534C - 总线使用请求的调整方法及其系统 - Google Patents

总线使用请求的调整方法及其系统 Download PDF

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Publication number
CN1271534C
CN1271534C CNB021570140A CN02157014A CN1271534C CN 1271534 C CN1271534 C CN 1271534C CN B021570140 A CNB021570140 A CN B021570140A CN 02157014 A CN02157014 A CN 02157014A CN 1271534 C CN1271534 C CN 1271534C
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CN
China
Prior art keywords
mentioned
request
arbiter
main device
circuit
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
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CNB021570140A
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English (en)
Chinese (zh)
Other versions
CN1427352A (zh
Inventor
藤原隆史
加藤勝則
横山登
伊達厚
前田忠昭
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Canon Inc
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Canon Inc
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Publication date
Application filed by Canon Inc filed Critical Canon Inc
Publication of CN1427352A publication Critical patent/CN1427352A/zh
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Publication of CN1271534C publication Critical patent/CN1271534C/zh
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/3625—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using a time dependent access
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/364—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
CNB021570140A 2001-12-18 2002-12-18 总线使用请求的调整方法及其系统 Expired - Fee Related CN1271534C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2001384698A JP2003186824A (ja) 2001-12-18 2001-12-18 バス使用権優先度調整装置およびシステム
JP384698/2001 2001-12-18

Publications (2)

Publication Number Publication Date
CN1427352A CN1427352A (zh) 2003-07-02
CN1271534C true CN1271534C (zh) 2006-08-23

Family

ID=19187747

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB021570140A Expired - Fee Related CN1271534C (zh) 2001-12-18 2002-12-18 总线使用请求的调整方法及其系统

Country Status (3)

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US (2) US6952747B2 (enExample)
JP (1) JP2003186824A (enExample)
CN (1) CN1271534C (enExample)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003186824A (ja) * 2001-12-18 2003-07-04 Canon Inc バス使用権優先度調整装置およびシステム
JP4181839B2 (ja) * 2002-09-30 2008-11-19 キヤノン株式会社 システムコントローラ
JP2004126646A (ja) 2002-09-30 2004-04-22 Canon Inc バス制御方法
JP4217452B2 (ja) * 2002-09-30 2009-02-04 キヤノン株式会社 プロセッサシステム
JP2005063358A (ja) * 2003-08-20 2005-03-10 Matsushita Electric Ind Co Ltd 命令供給制御装置および半導体装置
CN100375448C (zh) * 2005-11-04 2008-03-12 北京和利时系统工程股份有限公司 一种避免冗余主站对串行总线链路访问冲突的方法
JP2007334641A (ja) 2006-06-15 2007-12-27 Sony Corp 情報処理装置および方法、並びにプログラム
DE102009027625A1 (de) * 2009-07-10 2011-01-13 Robert Bosch Gmbh Elektrische Schaltung zur Übertragung von Signalen zwischen zwei Mastern und einem oder mehreren Slaves
JP5503365B2 (ja) * 2010-03-25 2014-05-28 キヤノン株式会社 デバイス管理システム、管理装置、デバイス管理方法及びプログラム
US8386682B2 (en) * 2010-06-30 2013-02-26 Intel Corporation Method, apparatus and system for maintaining transaction coherecy in a multiple data bus platform
KR101855399B1 (ko) * 2011-03-24 2018-05-09 삼성전자주식회사 데이터 트래픽을 개선한 ＳｏＣ 및 이의 동작 방법
JP2014016730A (ja) * 2012-07-06 2014-01-30 Canon Inc バス調停装置、バス調停方法、及びコンピュータプログラム
CN106598888B (zh) * 2016-12-22 2019-07-12 广东威创视讯科技股份有限公司 一种采用rs485协议的多板卡通讯系统及方法
US10496577B2 (en) 2017-02-09 2019-12-03 Hewlett Packard Enterprise Development Lp Distribution of master device tasks among bus queues
JP6985810B2 (ja) * 2017-04-27 2021-12-22 キヤノン株式会社 転送装置、転送方法および複合機
US11520725B2 (en) * 2020-05-15 2022-12-06 Nxp Usa, Inc. Performance monitor for interconnection network in an integrated circuit

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US3820081A (en) * 1972-10-05 1974-06-25 Honeywell Inf Systems Override hardware for main store sequencer
US3821709A (en) * 1972-10-05 1974-06-28 Honeywell Inf Systems Memory storage sequencer
US4759965A (en) * 1985-08-06 1988-07-26 Canon Kabushiki Kaisha Ceramic, preparation thereof and electronic circuit substrate by use thereof
JP2529720B2 (ja) 1988-06-17 1996-09-04 富士通株式会社 ダイレクトメモリアクセス装置
US4972313A (en) * 1989-08-07 1990-11-20 Bull Hn Information Systems Inc. Bus access control for a multi-host system using successively decremented arbitration delay periods to allocate bus access among the hosts
JPH03263159A (ja) 1990-03-13 1991-11-22 Nec Corp バス獲得要求生成方式
JP2986176B2 (ja) * 1990-05-11 1999-12-06 株式会社日立製作所 バス権制御方式およびバスシステム
WO1996017260A1 (en) * 1994-11-28 1996-06-06 Analogic Corporation Ups for medical imaging system
US5572686A (en) * 1995-06-05 1996-11-05 Apple Computer, Inc. Bus arbitration scheme with priority switching and timer
US5862353A (en) * 1997-03-25 1999-01-19 International Business Machines Corporation Systems and methods for dynamically controlling a bus
US6189076B1 (en) * 1997-11-14 2001-02-13 Lucent Technologies, Inc. Shared synchronous memory with a switching circuit controlled by an arbiter and method for glitch free switching of a clock signal
US6275890B1 (en) * 1998-08-19 2001-08-14 International Business Machines Corporation Low latency data path in a cross-bar switch providing dynamically prioritized bus arbitration
JP2000211210A (ja) * 1999-01-25 2000-08-02 Canon Inc 複合機器の制御装置及び方法
US6772254B2 (en) * 2000-06-21 2004-08-03 International Business Machines Corporation Multi-master computer system with overlapped read and write operations and scalable address pipelining
US6745273B1 (en) * 2001-01-12 2004-06-01 Lsi Logic Corporation Automatic deadlock prevention via arbitration switching
JP4916059B2 (ja) * 2001-07-31 2012-04-11 キヤノン株式会社 画像処理装置
JP2003186824A (ja) * 2001-12-18 2003-07-04 Canon Inc バス使用権優先度調整装置およびシステム
US6880028B2 (en) * 2002-03-18 2005-04-12 Sun Microsystems, Inc Dynamic request priority arbitration
US20030229743A1 (en) * 2002-06-05 2003-12-11 Brown Andrew C. Methods and structure for improved fairness bus arbitration

Also Published As

Publication number Publication date
JP2003186824A (ja) 2003-07-04
US6952747B2 (en) 2005-10-04
US7380034B2 (en) 2008-05-27
US20050188139A1 (en) 2005-08-25
CN1427352A (zh) 2003-07-02
US20030115392A1 (en) 2003-06-19

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C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
C17 Cessation of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20060823

Termination date: 20131218