JP2003123488A - 半導体記憶装置 - Google Patents

半導体記憶装置

Info

Publication number
JP2003123488A
JP2003123488A JP2001314163A JP2001314163A JP2003123488A JP 2003123488 A JP2003123488 A JP 2003123488A JP 2001314163 A JP2001314163 A JP 2001314163A JP 2001314163 A JP2001314163 A JP 2001314163A JP 2003123488 A JP2003123488 A JP 2003123488A
Authority
JP
Japan
Prior art keywords
core
data
write
erase
erasing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001314163A
Other languages
English (en)
Japanese (ja)
Other versions
JP2003123488A5 (enExample
Inventor
Yasuhiko Honda
泰彦 本多
Hideo Kato
秀雄 加藤
Masao Kuriyama
正男 栗山
Sakatoshi Saito
栄俊 斉藤
Norimasa Hara
徳正 原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP2001314163A priority Critical patent/JP2003123488A/ja
Priority to US10/267,693 priority patent/US6717852B2/en
Priority to KR10-2002-0061698A priority patent/KR100518283B1/ko
Priority to DE60218009T priority patent/DE60218009T2/de
Priority to EP02022947A priority patent/EP1308963B1/en
Publication of JP2003123488A publication Critical patent/JP2003123488A/ja
Publication of JP2003123488A5 publication Critical patent/JP2003123488A5/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1042—Read-write modes for single port memories, i.e. having either a random port or a serial port using interleaving techniques, i.e. read-write of one part of the memory while preparing another part
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2216/00—Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
    • G11C2216/12—Reading and writing aspects of erasable programmable read-only memories
    • G11C2216/22—Nonvolatile memory in which reading can be carried out from one memory bank or array whilst a word or sector in another bank or array is being erased or programmed simultaneously

Landscapes

  • Read Only Memory (AREA)
JP2001314163A 2001-10-11 2001-10-11 半導体記憶装置 Pending JP2003123488A (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP2001314163A JP2003123488A (ja) 2001-10-11 2001-10-11 半導体記憶装置
US10/267,693 US6717852B2 (en) 2001-10-11 2002-10-10 Nonvolatile semiconductor memory device capable of concurrently and reliably writing/erasing and reading memory cores
KR10-2002-0061698A KR100518283B1 (ko) 2001-10-11 2002-10-10 반도체 기억 장치
DE60218009T DE60218009T2 (de) 2001-10-11 2002-10-11 Halbleiterspeichervorrichtung
EP02022947A EP1308963B1 (en) 2001-10-11 2002-10-11 Semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001314163A JP2003123488A (ja) 2001-10-11 2001-10-11 半導体記憶装置

Publications (2)

Publication Number Publication Date
JP2003123488A true JP2003123488A (ja) 2003-04-25
JP2003123488A5 JP2003123488A5 (enExample) 2004-10-28

Family

ID=19132521

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001314163A Pending JP2003123488A (ja) 2001-10-11 2001-10-11 半導体記憶装置

Country Status (5)

Country Link
US (1) US6717852B2 (enExample)
EP (1) EP1308963B1 (enExample)
JP (1) JP2003123488A (enExample)
KR (1) KR100518283B1 (enExample)
DE (1) DE60218009T2 (enExample)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009503682A (ja) * 2005-07-26 2009-01-29 マイクロン テクノロジー， インク． 複数アドレス、データ及びコマンドバスを有するメモリデバイス及び方法
JP2011507140A (ja) * 2007-12-21 2011-03-03 モーセッド・テクノロジーズ・インコーポレイテッド 電力削減機能を有する不揮発性半導体メモリデバイス
US9213389B2 (en) 2007-12-21 2015-12-15 Conversant Intellectual Property Management Inc. Non-volatile semiconductor memory device with power-saving feature
JP2018082189A (ja) * 2010-09-13 2018-05-24 株式会社半導体エネルギー研究所 記憶装置

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100527547B1 (ko) * 2004-03-06 2005-11-09 주식회사 하이닉스반도체 소자 정보 기록 회로
WO2008010258A1 (fr) * 2006-07-18 2008-01-24 Spansion Llc Dispositif de stockage non volatil et son procédé de commande d'effacement
JP2009087028A (ja) * 2007-09-28 2009-04-23 Toshiba Corp メモリシステム及びメモリの読出し方法並びにプログラム
US20100286343A1 (en) * 2008-01-08 2010-11-11 Thomas Burghardt Surfaces containing coupling activator compounds and reinforced composites produced therefrom
EP2248130A1 (en) * 2008-02-19 2010-11-10 Rambus Inc. Multi-bank flash memory architecture with assignable resources
JP5100554B2 (ja) 2008-07-30 2012-12-19 株式会社東芝 半導体記憶装置
CN101706788B (zh) * 2009-11-25 2012-11-14 惠州Tcl移动通信有限公司 一种嵌入式文件系统的跨区访问方法
US9779038B2 (en) 2013-01-31 2017-10-03 Apple Inc. Efficient suspend-resume operation in memory devices
US9143070B2 (en) 2013-08-02 2015-09-22 Hamilton Sundstrand Corporation Systems and methods for controlling torsional oscillation in wound field synchronous generator machines
KR101717898B1 (ko) 2015-09-11 2017-03-20 홍성무 직불(直火)구이의 석쇠장치
CN111863095B (zh) * 2019-04-29 2022-07-29 北京兆易创新科技股份有限公司 一种NOR flash存储器擦除的方法和装置
US20220392519A1 (en) * 2022-08-19 2022-12-08 Intel Corporation Full duplex dram for tightly coupled compute die and memory die

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3152535B2 (ja) * 1993-03-18 2001-04-03 富士通株式会社 データ処理装置
US5867430A (en) * 1996-12-20 1999-02-02 Advanced Micro Devices Inc Bank architecture for a non-volatile memory enabling simultaneous reading and writing
US5847998A (en) * 1996-12-20 1998-12-08 Advanced Micro Devices, Inc. Non-volatile memory array that enables simultaneous read and write operations
US5841696A (en) 1997-03-05 1998-11-24 Advanced Micro Devices, Inc. Non-volatile memory enabling simultaneous reading and writing by time multiplexing a decode path
TW407234B (en) * 1997-03-31 2000-10-01 Hitachi Ltd Semiconductor memory device, non-volatile semiconductor memory device and data reading method thereof
JP3200034B2 (ja) * 1998-01-26 2001-08-20 株式会社東芝 不揮発性半導体メモリ装置
JP4047515B2 (ja) 1999-05-10 2008-02-13 株式会社東芝 半導体装置
US6377502B1 (en) 1999-05-10 2002-04-23 Kabushiki Kaisha Toshiba Semiconductor device that enables simultaneous read and write/erase operation
US6111787A (en) 1999-10-19 2000-08-29 Advanced Micro Devices, Inc. Address transistion detect timing architecture for a simultaneous operation flash memory device
US6240040B1 (en) * 2000-03-15 2001-05-29 Advanced Micro Devices, Inc. Multiple bank simultaneous operation for a flash memory

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009503682A (ja) * 2005-07-26 2009-01-29 マイクロン テクノロジー， インク． 複数アドレス、データ及びコマンドバスを有するメモリデバイス及び方法
JP4852692B2 (ja) * 2005-07-26 2012-01-11 ラウンド ロック リサーチ、エルエルシー 複数アドレス、データ及びコマンドバスを有するメモリデバイス及び方法
JP2011507140A (ja) * 2007-12-21 2011-03-03 モーセッド・テクノロジーズ・インコーポレイテッド 電力削減機能を有する不揮発性半導体メモリデバイス
US9213389B2 (en) 2007-12-21 2015-12-15 Conversant Intellectual Property Management Inc. Non-volatile semiconductor memory device with power-saving feature
JP2018082189A (ja) * 2010-09-13 2018-05-24 株式会社半導体エネルギー研究所 記憶装置

Also Published As

Publication number Publication date
DE60218009D1 (de) 2007-03-22
US20030072199A1 (en) 2003-04-17
US6717852B2 (en) 2004-04-06
EP1308963A1 (en) 2003-05-07
EP1308963B1 (en) 2007-02-07
DE60218009T2 (de) 2007-10-25
KR100518283B1 (ko) 2005-10-04
KR20030030945A (ko) 2003-04-18

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