JP2003036674A5 - - Google Patents

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Publication number
JP2003036674A5
JP2003036674A5 JP2002126981A JP2002126981A JP2003036674A5 JP 2003036674 A5 JP2003036674 A5 JP 2003036674A5 JP 2002126981 A JP2002126981 A JP 2002126981A JP 2002126981 A JP2002126981 A JP 2002126981A JP 2003036674 A5 JP2003036674 A5 JP 2003036674A5
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JP
Japan
Prior art keywords
input terminal
buffer
signal
input
logic circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2002126981A
Other languages
English (en)
Japanese (ja)
Other versions
JP4027709B2 (ja
JP2003036674A (ja
Filing date
Publication date
Priority claimed from KR10-2001-0022982A external-priority patent/KR100425446B1/ko
Application filed filed Critical
Publication of JP2003036674A publication Critical patent/JP2003036674A/ja
Publication of JP2003036674A5 publication Critical patent/JP2003036674A5/ja
Application granted granted Critical
Publication of JP4027709B2 publication Critical patent/JP4027709B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

JP2002126981A 2001-04-27 2002-04-26 半導体メモリ装置の入力回路 Expired - Fee Related JP4027709B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR2001-022982 2001-04-27
KR10-2001-0022982A KR100425446B1 (ko) 2001-04-27 2001-04-27 캘리브레이션 될 소정의 클럭신호를 선택하는클럭선택회로를 구비하는 반도체 메모리 장치의 입력회로및 소정의 클럭신호를 선택하는 방법

Publications (3)

Publication Number Publication Date
JP2003036674A JP2003036674A (ja) 2003-02-07
JP2003036674A5 true JP2003036674A5 (enExample) 2005-06-02
JP4027709B2 JP4027709B2 (ja) 2007-12-26

Family

ID=19708808

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002126981A Expired - Fee Related JP4027709B2 (ja) 2001-04-27 2002-04-26 半導体メモリ装置の入力回路

Country Status (3)

Country Link
US (1) US6696862B2 (enExample)
JP (1) JP4027709B2 (enExample)
KR (1) KR100425446B1 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11347396B2 (en) 2007-02-16 2022-05-31 Mosaid Technologies Incorporated Clock mode determination in a memory system

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7406646B2 (en) * 2002-10-01 2008-07-29 Advantest Corporation Multi-strobe apparatus, testing apparatus, and adjusting method
JP4002811B2 (ja) * 2002-10-04 2007-11-07 株式会社アドバンテスト マルチストローブ生成装置、試験装置、及び調整方法
KR100626375B1 (ko) 2003-07-21 2006-09-20 삼성전자주식회사 고주파로 동작하는 반도체 메모리 장치 및 모듈
DE102004013929B3 (de) * 2004-03-22 2005-08-11 Infineon Technologies Ag Verfahren zum Steuern des Einlesens eines Datensignals sowie eine Eingangsschaltung für eine elektronische Schaltung
JP4583088B2 (ja) * 2004-06-29 2010-11-17 株式会社リコー ストローブ信号遅延装置及び同装置を備える半導体装置
KR100567908B1 (ko) 2004-12-30 2006-04-05 주식회사 하이닉스반도체 반도체 소자의 보정 회로 및 그 구동 방법
KR100863010B1 (ko) * 2007-04-11 2008-10-13 주식회사 하이닉스반도체 반도체 집적 회로
DE112007003570T5 (de) * 2007-06-27 2010-08-26 Advantest Corp. Erfassungsgerät und Prüfgerät
KR101252698B1 (ko) * 2009-04-29 2013-04-09 퀄컴 인코포레이티드 클록 게이팅 시스템 및 방법
US9672881B2 (en) * 2014-05-23 2017-06-06 Macronix International Co., Ltd. Memory device with variable strobe interface
US11569805B2 (en) * 2021-03-15 2023-01-31 Mediatek Inc. Minimum intrinsic timing utilization auto alignment on multi-die system

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3695902B2 (ja) * 1997-06-24 2005-09-14 富士通株式会社 半導体記憶装置
JP3270831B2 (ja) * 1998-02-03 2002-04-02 富士通株式会社 半導体装置
TW400635B (en) * 1998-02-03 2000-08-01 Fujitsu Ltd Semiconductor device reconciling different timing signals
US6061292A (en) * 1998-08-21 2000-05-09 Winbond Electronics Corporation Method and circuit for triggering column select line for write operations
US6069829A (en) * 1998-09-29 2000-05-30 Texas Instruments Incorporated Internal clock multiplication for test time reduction
KR100335503B1 (ko) 2000-06-26 2002-05-08 윤종용 서로 다른 지연 특성을 동일하게 하는 신호 전달 회로,신호 전달 방법 및 이를 구비하는 반도체 장치의 데이터래치 회로

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11347396B2 (en) 2007-02-16 2022-05-31 Mosaid Technologies Incorporated Clock mode determination in a memory system
US11669248B2 (en) 2007-02-16 2023-06-06 Mosaid Technologies Incorporated Clock mode determination in a memory system
US11880569B2 (en) 2007-02-16 2024-01-23 Mosaid Technologies Incorporated Clock mode determination in a memory system
US12321600B2 (en) 2007-02-16 2025-06-03 Mosaid Technologies Incorporated Clock mode determination in a memory system

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