JP4027709B2 - 半導体メモリ装置の入力回路 - Google Patents

半導体メモリ装置の入力回路 Download PDF

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Publication number
JP4027709B2
JP4027709B2 JP2002126981A JP2002126981A JP4027709B2 JP 4027709 B2 JP4027709 B2 JP 4027709B2 JP 2002126981 A JP2002126981 A JP 2002126981A JP 2002126981 A JP2002126981 A JP 2002126981A JP 4027709 B2 JP4027709 B2 JP 4027709B2
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JP
Japan
Prior art keywords
signal
clock signal
input
circuit
selection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2002126981A
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English (en)
Japanese (ja)
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JP2003036674A5 (enExample
JP2003036674A (ja
Inventor
崔東俊
鄭大鉉
黄祥俊
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of JP2003036674A publication Critical patent/JP2003036674A/ja
Publication of JP2003036674A5 publication Critical patent/JP2003036674A5/ja
Application granted granted Critical
Publication of JP4027709B2 publication Critical patent/JP4027709B2/ja
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1084—Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/20—Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2254—Calibration

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)
  • Memory System (AREA)
  • Logic Circuits (AREA)
JP2002126981A 2001-04-27 2002-04-26 半導体メモリ装置の入力回路 Expired - Fee Related JP4027709B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR2001-022982 2001-04-27
KR10-2001-0022982A KR100425446B1 (ko) 2001-04-27 2001-04-27 캘리브레이션 될 소정의 클럭신호를 선택하는클럭선택회로를 구비하는 반도체 메모리 장치의 입력회로및 소정의 클럭신호를 선택하는 방법

Publications (3)

Publication Number Publication Date
JP2003036674A JP2003036674A (ja) 2003-02-07
JP2003036674A5 JP2003036674A5 (enExample) 2005-06-02
JP4027709B2 true JP4027709B2 (ja) 2007-12-26

Family

ID=19708808

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002126981A Expired - Fee Related JP4027709B2 (ja) 2001-04-27 2002-04-26 半導体メモリ装置の入力回路

Country Status (3)

Country Link
US (1) US6696862B2 (enExample)
JP (1) JP4027709B2 (enExample)
KR (1) KR100425446B1 (enExample)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7406646B2 (en) * 2002-10-01 2008-07-29 Advantest Corporation Multi-strobe apparatus, testing apparatus, and adjusting method
JP4002811B2 (ja) * 2002-10-04 2007-11-07 株式会社アドバンテスト マルチストローブ生成装置、試験装置、及び調整方法
KR100626375B1 (ko) 2003-07-21 2006-09-20 삼성전자주식회사 고주파로 동작하는 반도체 메모리 장치 및 모듈
DE102004013929B3 (de) * 2004-03-22 2005-08-11 Infineon Technologies Ag Verfahren zum Steuern des Einlesens eines Datensignals sowie eine Eingangsschaltung für eine elektronische Schaltung
JP4583088B2 (ja) * 2004-06-29 2010-11-17 株式会社リコー ストローブ信号遅延装置及び同装置を備える半導体装置
KR100567908B1 (ko) 2004-12-30 2006-04-05 주식회사 하이닉스반도체 반도체 소자의 보정 회로 및 그 구동 방법
CN101617371B (zh) 2007-02-16 2014-03-26 莫塞德技术公司 具有多个外部电源的非易失性半导体存储器
KR100863010B1 (ko) * 2007-04-11 2008-10-13 주식회사 하이닉스반도체 반도체 집적 회로
DE112007003570T5 (de) * 2007-06-27 2010-08-26 Advantest Corp. Erfassungsgerät und Prüfgerät
KR101252698B1 (ko) * 2009-04-29 2013-04-09 퀄컴 인코포레이티드 클록 게이팅 시스템 및 방법
US9672881B2 (en) * 2014-05-23 2017-06-06 Macronix International Co., Ltd. Memory device with variable strobe interface
US11569805B2 (en) * 2021-03-15 2023-01-31 Mediatek Inc. Minimum intrinsic timing utilization auto alignment on multi-die system

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3695902B2 (ja) * 1997-06-24 2005-09-14 富士通株式会社 半導体記憶装置
JP3270831B2 (ja) * 1998-02-03 2002-04-02 富士通株式会社 半導体装置
TW400635B (en) * 1998-02-03 2000-08-01 Fujitsu Ltd Semiconductor device reconciling different timing signals
US6061292A (en) * 1998-08-21 2000-05-09 Winbond Electronics Corporation Method and circuit for triggering column select line for write operations
US6069829A (en) * 1998-09-29 2000-05-30 Texas Instruments Incorporated Internal clock multiplication for test time reduction
KR100335503B1 (ko) 2000-06-26 2002-05-08 윤종용 서로 다른 지연 특성을 동일하게 하는 신호 전달 회로,신호 전달 방법 및 이를 구비하는 반도체 장치의 데이터래치 회로

Also Published As

Publication number Publication date
KR20020083586A (ko) 2002-11-04
US6696862B2 (en) 2004-02-24
US20020158669A1 (en) 2002-10-31
KR100425446B1 (ko) 2004-03-30
JP2003036674A (ja) 2003-02-07

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