KR100425446B1 - 캘리브레이션 될 소정의 클럭신호를 선택하는클럭선택회로를 구비하는 반도체 메모리 장치의 입력회로및 소정의 클럭신호를 선택하는 방법 - Google Patents

캘리브레이션 될 소정의 클럭신호를 선택하는클럭선택회로를 구비하는 반도체 메모리 장치의 입력회로및 소정의 클럭신호를 선택하는 방법 Download PDF

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Publication number
KR100425446B1
KR100425446B1 KR10-2001-0022982A KR20010022982A KR100425446B1 KR 100425446 B1 KR100425446 B1 KR 100425446B1 KR 20010022982 A KR20010022982 A KR 20010022982A KR 100425446 B1 KR100425446 B1 KR 100425446B1
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KR
South Korea
Prior art keywords
signal
clock signal
circuit
input
selection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR10-2001-0022982A
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English (en)
Korean (ko)
Other versions
KR20020083586A (ko
Inventor
최동준
정대현
황상준
Original Assignee
삼성전자주식회사
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Filing date
Publication date
Application filed by 삼성전자주식회사 filed Critical 삼성전자주식회사
Priority to KR10-2001-0022982A priority Critical patent/KR100425446B1/ko
Priority to US10/108,668 priority patent/US6696862B2/en
Priority to JP2002126981A priority patent/JP4027709B2/ja
Publication of KR20020083586A publication Critical patent/KR20020083586A/ko
Application granted granted Critical
Publication of KR100425446B1 publication Critical patent/KR100425446B1/ko
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1084—Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/20—Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2254—Calibration

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)
  • Memory System (AREA)
  • Logic Circuits (AREA)
KR10-2001-0022982A 2001-04-27 2001-04-27 캘리브레이션 될 소정의 클럭신호를 선택하는클럭선택회로를 구비하는 반도체 메모리 장치의 입력회로및 소정의 클럭신호를 선택하는 방법 Expired - Fee Related KR100425446B1 (ko)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR10-2001-0022982A KR100425446B1 (ko) 2001-04-27 2001-04-27 캘리브레이션 될 소정의 클럭신호를 선택하는클럭선택회로를 구비하는 반도체 메모리 장치의 입력회로및 소정의 클럭신호를 선택하는 방법
US10/108,668 US6696862B2 (en) 2001-04-27 2002-03-27 Semiconductor memory device input circuit
JP2002126981A JP4027709B2 (ja) 2001-04-27 2002-04-26 半導体メモリ装置の入力回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR10-2001-0022982A KR100425446B1 (ko) 2001-04-27 2001-04-27 캘리브레이션 될 소정의 클럭신호를 선택하는클럭선택회로를 구비하는 반도체 메모리 장치의 입력회로및 소정의 클럭신호를 선택하는 방법

Publications (2)

Publication Number Publication Date
KR20020083586A KR20020083586A (ko) 2002-11-04
KR100425446B1 true KR100425446B1 (ko) 2004-03-30

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR10-2001-0022982A Expired - Fee Related KR100425446B1 (ko) 2001-04-27 2001-04-27 캘리브레이션 될 소정의 클럭신호를 선택하는클럭선택회로를 구비하는 반도체 메모리 장치의 입력회로및 소정의 클럭신호를 선택하는 방법

Country Status (3)

Country Link
US (1) US6696862B2 (enExample)
JP (1) JP4027709B2 (enExample)
KR (1) KR100425446B1 (enExample)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7406646B2 (en) * 2002-10-01 2008-07-29 Advantest Corporation Multi-strobe apparatus, testing apparatus, and adjusting method
JP4002811B2 (ja) * 2002-10-04 2007-11-07 株式会社アドバンテスト マルチストローブ生成装置、試験装置、及び調整方法
KR100626375B1 (ko) 2003-07-21 2006-09-20 삼성전자주식회사 고주파로 동작하는 반도체 메모리 장치 및 모듈
DE102004013929B3 (de) * 2004-03-22 2005-08-11 Infineon Technologies Ag Verfahren zum Steuern des Einlesens eines Datensignals sowie eine Eingangsschaltung für eine elektronische Schaltung
JP4583088B2 (ja) * 2004-06-29 2010-11-17 株式会社リコー ストローブ信号遅延装置及び同装置を備える半導体装置
KR100567908B1 (ko) 2004-12-30 2006-04-05 주식회사 하이닉스반도체 반도체 소자의 보정 회로 및 그 구동 방법
CN101617371B (zh) 2007-02-16 2014-03-26 莫塞德技术公司 具有多个外部电源的非易失性半导体存储器
KR100863010B1 (ko) * 2007-04-11 2008-10-13 주식회사 하이닉스반도체 반도체 집적 회로
DE112007003570T5 (de) * 2007-06-27 2010-08-26 Advantest Corp. Erfassungsgerät und Prüfgerät
KR101252698B1 (ko) * 2009-04-29 2013-04-09 퀄컴 인코포레이티드 클록 게이팅 시스템 및 방법
US9672881B2 (en) * 2014-05-23 2017-06-06 Macronix International Co., Ltd. Memory device with variable strobe interface
US11569805B2 (en) * 2021-03-15 2023-01-31 Mediatek Inc. Minimum intrinsic timing utilization auto alignment on multi-die system

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990006349A (ko) * 1997-06-24 1999-01-25 세키자와 다다시 반도체 기억 장치
KR19990072385A (ko) * 1998-02-03 1999-09-27 아끼구사 나오유끼 상이한타이밍신호를정합시키는반도체장치
JPH11288590A (ja) * 1998-02-03 1999-10-19 Fujitsu Ltd 半導体装置

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6061292A (en) * 1998-08-21 2000-05-09 Winbond Electronics Corporation Method and circuit for triggering column select line for write operations
US6069829A (en) * 1998-09-29 2000-05-30 Texas Instruments Incorporated Internal clock multiplication for test time reduction
KR100335503B1 (ko) 2000-06-26 2002-05-08 윤종용 서로 다른 지연 특성을 동일하게 하는 신호 전달 회로,신호 전달 방법 및 이를 구비하는 반도체 장치의 데이터래치 회로

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990006349A (ko) * 1997-06-24 1999-01-25 세키자와 다다시 반도체 기억 장치
KR19990072385A (ko) * 1998-02-03 1999-09-27 아끼구사 나오유끼 상이한타이밍신호를정합시키는반도체장치
JPH11288590A (ja) * 1998-02-03 1999-10-19 Fujitsu Ltd 半導体装置

Also Published As

Publication number Publication date
KR20020083586A (ko) 2002-11-04
US6696862B2 (en) 2004-02-24
US20020158669A1 (en) 2002-10-31
JP4027709B2 (ja) 2007-12-26
JP2003036674A (ja) 2003-02-07

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