JP2002544643A5 - - Google Patents

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Publication number
JP2002544643A5
JP2002544643A5 JP2000617455A JP2000617455A JP2002544643A5 JP 2002544643 A5 JP2002544643 A5 JP 2002544643A5 JP 2000617455 A JP2000617455 A JP 2000617455A JP 2000617455 A JP2000617455 A JP 2000617455A JP 2002544643 A5 JP2002544643 A5 JP 2002544643A5
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JP
Japan
Prior art keywords
voltage
applying
memory cells
well
control gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2000617455A
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English (en)
Japanese (ja)
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JP2002544643A (ja
JP3811760B2 (ja
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Publication date
Priority claimed from US09/307,259 external-priority patent/US6188609B1/en
Application filed filed Critical
Publication of JP2002544643A publication Critical patent/JP2002544643A/ja
Publication of JP2002544643A5 publication Critical patent/JP2002544643A5/ja
Application granted granted Critical
Publication of JP3811760B2 publication Critical patent/JP3811760B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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JP2000617455A 1999-05-06 2000-05-05 フラッシュメモリ用途のための傾斜付きまたは段階的ゲートチャネル消去 Expired - Fee Related JP3811760B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/307,259 US6188609B1 (en) 1999-05-06 1999-05-06 Ramped or stepped gate channel erase for flash memory application
US09/307,259 1999-05-06
PCT/US2000/012343 WO2000068952A1 (en) 1999-05-06 2000-05-05 Ramped or stepped gate channel erase for flash memory application

Publications (3)

Publication Number Publication Date
JP2002544643A JP2002544643A (ja) 2002-12-24
JP2002544643A5 true JP2002544643A5 (https=) 2005-11-17
JP3811760B2 JP3811760B2 (ja) 2006-08-23

Family

ID=23188932

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000617455A Expired - Fee Related JP3811760B2 (ja) 1999-05-06 2000-05-05 フラッシュメモリ用途のための傾斜付きまたは段階的ゲートチャネル消去

Country Status (7)

Country Link
US (1) US6188609B1 (https=)
EP (1) EP1175680B1 (https=)
JP (1) JP3811760B2 (https=)
KR (1) KR100578582B1 (https=)
DE (1) DE60001497T2 (https=)
TW (1) TW461095B (https=)
WO (1) WO2000068952A1 (https=)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100308192B1 (ko) * 1999-07-28 2001-11-01 윤종용 플래시 메모리 셀들의 과소거를 방지할 수 있는 플래시 메모리장치 및 그것의 소거 방법
US7366020B2 (en) * 1999-07-28 2008-04-29 Samsung Electronics Co., Ltd. Flash memory device capable of preventing an overerase of flash memory cells and erase method thereof
US6914827B2 (en) * 1999-07-28 2005-07-05 Samsung Electronics Co., Ltd. Flash memory device capable of preventing an over-erase of flash memory cells and erase method thereof
US6381179B1 (en) * 2000-02-24 2002-04-30 Advanced Micro Devices, Inc. Using a negative gate erase to increase the cycling endurance of a non-volatile memory cell with an oxide-nitride-oxide (ONO) structure
DE60140039D1 (de) * 2001-02-05 2009-11-12 St Microelectronics Srl Löschverfahren für einen Flash-Speicher
US6385093B1 (en) * 2001-03-30 2002-05-07 Advanced Micro Devices, Inc. I/O partitioning system and methodology to reduce band-to-band tunneling current during erase
TW511203B (en) * 2001-04-20 2002-11-21 Macronix Int Co Ltd Erase method of flash memory
CN100481268C (zh) * 2001-06-25 2009-04-22 旺宏电子股份有限公司 一种闪存的抹除方法
KR100456596B1 (ko) * 2002-05-08 2004-11-09 삼성전자주식회사 부유트랩형 비휘발성 기억소자의 소거 방법
US6891752B1 (en) * 2002-07-31 2005-05-10 Advanced Micro Devices System and method for erase voltage control during multiple sector erase of a flash memory device
US6628545B1 (en) * 2002-11-26 2003-09-30 Advanced Micro Devices, Inc. Memory circuit for suppressing bit line current leakage
US7073104B1 (en) * 2003-03-10 2006-07-04 Advanced Micro Devices, Inc. Method and system for applying testing voltage signal
TWI247311B (en) * 2004-03-25 2006-01-11 Elite Semiconductor Esmt Circuit and method for preventing nonvolatile memory from over erasure
KR100781041B1 (ko) * 2006-11-06 2007-11-30 주식회사 하이닉스반도체 플래시 메모리 장치 및 그 소거 동작 제어 방법
EP2302635B1 (en) * 2009-09-18 2016-01-13 STMicroelectronics Srl Method for biasing an EEPROM non-volatile memory array and corresponding EEPROM non-volatile memory device
US8345485B2 (en) 2011-02-09 2013-01-01 Freescale Semiconductor, Inc. Erase ramp pulse width control for non-volatile memory
US8937837B2 (en) * 2012-05-08 2015-01-20 Sandisk Technologies Inc. Bit line BL isolation scheme during erase operation for non-volatile storage
US8891308B1 (en) 2013-09-11 2014-11-18 Sandisk Technologies Inc. Dynamic erase voltage step size selection for 3D non-volatile memory
KR102606497B1 (ko) 2016-06-27 2023-11-29 삼성전자주식회사 불휘발성 메모리 장치 및 불휘발성 메모리 장치의 소거 방법
US10559368B1 (en) 2018-08-07 2020-02-11 Sandisk Technologies Llc Non-volatile memory with countermeasures for select gate disturb during program pre-charge

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5642311A (en) * 1995-10-24 1997-06-24 Advanced Micro Devices Overerase correction for flash memory which limits overerase and prevents erase verify errors
US5841165A (en) * 1995-11-21 1998-11-24 Programmable Microelectronics Corporation PMOS flash EEPROM cell with single poly
WO1998010471A1 (en) * 1996-09-05 1998-03-12 Macronix International Co., Ltd. Triple well floating gate memory and operating method with isolated channel program, preprogram and erase processes
WO1998047151A1 (en) 1997-04-11 1998-10-22 Programmable Silicon Solutions Electrically erasable nonvolatile memory
JP3175665B2 (ja) 1997-10-24 2001-06-11 日本電気株式会社 不揮発性半導体記憶装置のデータ消去方法
US5970460A (en) * 1997-12-05 1999-10-19 Lernout & Hauspie Speech Products N.V. Speech recognition and editing system
US5978277A (en) * 1998-04-06 1999-11-02 Aplus Flash Technology, Inc. Bias condition and X-decoder circuit of flash memory array

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