JP5327900B2 - 不揮発性メモリアレイを有する電子デバイスの使用方法 - Google Patents
不揮発性メモリアレイを有する電子デバイスの使用方法 Download PDFInfo
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- JP5327900B2 JP5327900B2 JP2010502190A JP2010502190A JP5327900B2 JP 5327900 B2 JP5327900 B2 JP 5327900B2 JP 2010502190 A JP2010502190 A JP 2010502190A JP 2010502190 A JP2010502190 A JP 2010502190A JP 5327900 B2 JP5327900 B2 JP 5327900B2
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- Prior art keywords
- memory cell
- sector
- source
- memory
- bit line
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/349—Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
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- Read Only Memory (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Description
第1態様の他の実施形態では、第1メモリセルの消去は、第1セクタ内の第2メモリセルの消去禁止の前に、第1セクタ内の全てのメモリセルの消去を含む。他の実施形態では更に、第2メモリセルの消去禁止は、第1メモリセルを含むメモリセルセットを除く第1セクタ内の全てのメモリセルの消去禁止を含む。メモリセルグループはデータI/Oに対応し、メモリセルセットを有する。
Claims (2)
- 不揮発性メモリアレイ(10)を有する電子デバイスを使用する電子デバイス使用方法であって、
第1消去パルス中に同時に前記不揮発性メモリアレイ(10)の第1セクタ(1210)が備える第1メモリセルセット(1211)内の複数の第1メモリセル(311)を消去するステップ(42)であって、前記第1セクタ(1210)は、前記第1メモリセルセット(1211)と第2メモリセルセット(1212)を有することと;
前記第1消去パルス後の第2消去パルス中に、前記第1メモリセルセット(1211)を追加消去するステップ(48)であって、前記第2消去パルス中には、前記第2メモリセルセット(1212)の消去は、禁止されていることと
を備え、
前記第2メモリセルセット(1212)の消去が禁止されていることは、前記第2メモリセルセット(1212)が有する第2メモリセル(312)のソースを、前記第2メモリセル(312)のドレインよりも高い電圧に設定されることである、電子デバイス使用方法。 - 前記不揮発性メモリアレイ(10)はさらに、前記第1セクタ(1210)とは異なる第2セクタ(1220)を有し、
前記第2セクタ(1220)は、第3メモリセル(322)を有する第3メモリセルセット(1222)を有し、
前記第2メモリセルセット(1212)のソースと、前記第3メモリセルセット(1222)のソースとは、互いにソースビット線(352)で電気接続され、
前記第2消去パルス中の、第1メモリセル(311)の制御ゲート(371)と前記第1メモリセル(311)のソース(351)との間の電位差は、第1電位差であり、
前記第2消去パルス中の、前記第2メモリセル(312)の制御ゲート(371)と前記第2メモリセル(312)のソースとの間の電位差は、第2電位差であり、
前記第2消去パルス中の、前記第3メモリセル(322)の制御ゲート(372)と前記第3メモリセル(322)のソースとの間の電位差は、第3電位差であり、
前記第1電位差は、前記第2電位差よりも大きく、
前記第2電位差は、前記第3電位差よりも大きい、
請求項1記載の電子デバイス使用方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/695,722 | 2007-04-03 | ||
US11/695,722 US7668018B2 (en) | 2007-04-03 | 2007-04-03 | Electronic device including a nonvolatile memory array and methods of using the same |
PCT/US2008/057637 WO2008124269A1 (en) | 2007-04-03 | 2008-03-20 | Electronic device including a nonvolatile memory array and methods of using the same |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2010524143A JP2010524143A (ja) | 2010-07-15 |
JP2010524143A5 JP2010524143A5 (ja) | 2011-05-12 |
JP5327900B2 true JP5327900B2 (ja) | 2013-10-30 |
Family
ID=39826769
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2010502190A Expired - Fee Related JP5327900B2 (ja) | 2007-04-03 | 2008-03-20 | 不揮発性メモリアレイを有する電子デバイスの使用方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US7668018B2 (ja) |
JP (1) | JP5327900B2 (ja) |
CN (1) | CN101652855B (ja) |
WO (1) | WO2008124269A1 (ja) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9536614B2 (en) | 2015-04-24 | 2017-01-03 | Nxp Usa, Inc. | Common source architecture for split gate memory |
US10074438B2 (en) * | 2016-06-10 | 2018-09-11 | Cypress Semiconductor Corporation | Methods and devices for reducing program disturb in non-volatile memory cell arrays |
US9997253B1 (en) | 2016-12-08 | 2018-06-12 | Cypress Semiconductor Corporation | Non-volatile memory array with memory gate line and source line scrambling |
Family Cites Families (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3443998B2 (ja) * | 1995-01-23 | 2003-09-08 | ソニー株式会社 | 半導体不揮発性記憶装置 |
US6331724B1 (en) | 1995-11-17 | 2001-12-18 | Nippon Precision Circuits, Inc. | Single transistor E2prom memory device with controlled erasing |
US5748538A (en) | 1996-06-17 | 1998-05-05 | Aplus Integrated Circuits, Inc. | OR-plane memory cell array for flash memory with bit-based write capability, and methods for programming and erasing the memory cell array |
JP4046877B2 (ja) * | 1998-12-14 | 2008-02-13 | 株式会社ルネサステクノロジ | 一括消去型不揮発性メモリおよび携帯電話 |
US6091104A (en) * | 1999-03-24 | 2000-07-18 | Chen; Chiou-Feng | Flash memory cell with self-aligned gates and fabrication process |
JP2000331485A (ja) * | 1999-05-17 | 2000-11-30 | Nec Corp | 不揮発性半導体記憶装置及びその消去方法 |
US6101130A (en) * | 1999-06-29 | 2000-08-08 | Motorola Inc. | Semiconductor device memory cell and method for selectively erasing the same |
KR100383767B1 (ko) * | 1999-12-28 | 2003-05-14 | 주식회사 하이닉스반도체 | 플래쉬 메모리 소자의 소거 방법 |
US6620682B1 (en) | 2001-02-27 | 2003-09-16 | Aplus Flash Technology, Inc. | Set of three level concurrent word line bias conditions for a nor type flash memory array |
US6584034B1 (en) * | 2001-04-23 | 2003-06-24 | Aplus Flash Technology Inc. | Flash memory array structure suitable for multiple simultaneous operations |
US6522585B2 (en) * | 2001-05-25 | 2003-02-18 | Sandisk Corporation | Dual-cell soft programming for virtual-ground memory arrays |
JP2003068086A (ja) * | 2001-08-28 | 2003-03-07 | Mitsubishi Electric Corp | 不揮発性半導体記憶装置 |
US6862223B1 (en) * | 2002-07-05 | 2005-03-01 | Aplus Flash Technology, Inc. | Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout |
JP4073330B2 (ja) * | 2003-02-18 | 2008-04-09 | スパンション エルエルシー | 不揮発性半導体記憶装置 |
JP4220319B2 (ja) * | 2003-07-04 | 2009-02-04 | 株式会社東芝 | 不揮発性半導体記憶装置およびそのサブブロック消去方法 |
US7299314B2 (en) * | 2003-12-31 | 2007-11-20 | Sandisk Corporation | Flash storage system with write/erase abort detection mechanism |
EP1714286B1 (en) * | 2004-02-11 | 2008-12-10 | Nxp B.V. | High voltage driver circuit with fast reading operation |
US7042044B2 (en) * | 2004-02-18 | 2006-05-09 | Koucheng Wu | Nor-type channel-program channel-erase contactless flash memory on SOI |
US7145802B2 (en) | 2004-08-31 | 2006-12-05 | Skymedi Corporation | Programming and manufacturing method for split gate memory cell |
JP2006309829A (ja) * | 2005-04-27 | 2006-11-09 | Nec Electronics Corp | 不揮発性半導体記憶装置及びその制御方法 |
-
2007
- 2007-04-03 US US11/695,722 patent/US7668018B2/en not_active Expired - Fee Related
-
2008
- 2008-03-20 WO PCT/US2008/057637 patent/WO2008124269A1/en active Application Filing
- 2008-03-20 CN CN2008800112993A patent/CN101652855B/zh not_active Expired - Fee Related
- 2008-03-20 JP JP2010502190A patent/JP5327900B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
CN101652855B (zh) | 2013-06-19 |
US7668018B2 (en) | 2010-02-23 |
JP2010524143A (ja) | 2010-07-15 |
WO2008124269A1 (en) | 2008-10-16 |
CN101652855A (zh) | 2010-02-17 |
US20080247255A1 (en) | 2008-10-09 |
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