US7881110B2 - Method of programming nonvolatile memory device - Google Patents

Method of programming nonvolatile memory device Download PDF

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US7881110B2
US7881110B2 US12/165,195 US16519508A US7881110B2 US 7881110 B2 US7881110 B2 US 7881110B2 US 16519508 A US16519508 A US 16519508A US 7881110 B2 US7881110 B2 US 7881110B2
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program
voltage
start voltage
application number
pulse application
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US20090285028A1 (en
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Jin Su Park
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SK Hynix Inc
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Hynix Semiconductor Inc
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Priority to US13/019,189 priority patent/US8254183B2/en
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3404—Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3404—Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
    • G11C16/3409—Circuits or methods to recover overerased nonvolatile memory cells detected during erase verification, usually by means of a "soft" programming step
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/344—Arrangements for verifying correct erasure or for detecting overerased cells
    • G11C16/3445—Circuits or methods to verify correct erasure of nonvolatile memory cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
    • G11C16/3459—Circuits or methods to verify correct programming of nonvolatile memory cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/562—Multilevel memory programming aspects
    • G11C2211/5621—Multilevel programming verification

Definitions

  • the present invention relates to a method of programming nonvolatile memory devices.
  • a nonvolatile memory device is a device that enables electrical program/erase operations, and performs the program and erase operations by changing the threshold voltage of a cell as electrons are moved by a strong electric field applied to a thin oxide layer.
  • the nonvolatile memory device typically includes a memory cell array in which cells for storing data are arranged in matrix form, and a page buffer for writing data into specific cells of the memory cell array or reading data stored in a specific cell.
  • the page buffer includes bit line pairs coupled to specific memory cells and a register for temporarily storing data to be written into the memory cell array or reading data from a specific cell of the memory cell array and temporarily storing the read data. It also includes a sense node for sensing the voltage level of a specific bit line or a specific register, and a bit line select unit for controlling whether the specific bit line and the sense node have been coupled or not.
  • this nonvolatile memory device In a program operation of this nonvolatile memory device, there occurs a phenomenon in which a program speed changes according to the characteristics of cells and in the number of program/erase cycles. Meanwhile, the program operation of a nonvolatile memory device is carried out using an incremental step pulse program (ISPP) method. It is necessary to set a program start voltage in consideration of the program speed of each cell.
  • ISPP incremental step pulse program
  • the present invention relates to a method of programming a nonvolatile memory device, which can set a program start voltage differently according to the program speed of each cell.
  • a method of programming a nonvolatile memory device in accordance with an aspect of the present invention includes performing a program operation on a first page, counting a program pulse application number until the program operation on the first page is completed, comparing the counted program pulse application number and a critical value and resetting a program start voltage based on the comparison result, and performing a program operation on a second page using the reset program start voltage.
  • a method of programming a nonvolatile memory device in accordance with another aspect of the present invention includes performing an erase operation, counting an erase pulse application number until the erase operation is completed, comparing the counted erase pulse application number and a critical value and setting a program start voltage based on the comparison result, and performing a program operation using the set program start voltage.
  • a method of programming a nonvolatile memory device in accordance with still another aspect of the present invention includes performing an erase operation, counting an erase pulse application number until the erase operation is completed, comparing the counted erase pulse application number and a critical value and setting a post program start voltage based on the comparison result, performing a post program operation and a verify operation using the set post program start voltage, and performing a program operation on cells on which the post program operation has been completed.
  • a method of programming a nonvolatile memory device in accordance with further still another aspect of the present invention includes providing a memory cell on which an erase operation has been completed, performing a post program operation on the memory cell, counting a post program pulse application number until the post program operation is completed, comparing the counted post program pulse application number and a critical value and setting a program start voltage based on the comparison result, performing a program operation and a verify operation using the set program start voltage.
  • a method of programming a nonvolatile memory device in accordance with further still another aspect of the present invention includes performing a program operation of a first logical page with respect to a first physical page, counting a program pulse application number until the program operation of the first logical page is completed, comparing the counted program pulse application number and a critical value and resetting a program start voltage based on the comparison result, and performing a program operation of a second logical page with respect to the first physical page using the reset program start voltage.
  • FIG. 1 is a diagram showing a typical ISPP method of a nonvolatile memory device
  • FIG. 2 is a diagram showing a difference in the program speed according to characteristics of cells or the number of program/erase cycles in a typical nonvolatile memory device
  • FIG. 3 is a flowchart illustrating a method of programming a nonvolatile memory device in accordance with an embodiment of the present invention
  • FIG. 4 is a flowchart illustrating a method of programming a nonvolatile memory device in accordance with another embodiment of the present invention.
  • FIG. 5 is a flowchart illustrating a method of programming a nonvolatile memory device in accordance with still another embodiment of the present invention.
  • FIG. 6 is a flowchart illustrating a method of programming a nonvolatile memory device in accordance with further still another embodiment of the present invention.
  • FIG. 1 is a diagram showing a typical ISPP method of a nonvolatile memory device.
  • the ISPP method includes applying a plurality of program pulses to a memory cell to be programmed and performing a verify operation immediately after the application of each program pulse.
  • an (n+1) th program pulse is applied the voltage is increased by a step pulse (Vstep) from the n th program pulse.
  • Vstart start voltage
  • Vstep step voltage
  • the threshold voltage distributions of each cell has a wide unique distribution (Vthi) according to several process conditions, such as a channel width, a channel length, an oxide layer thickness, etc. of each memory cell.
  • Vstep a specific step voltage
  • the number of required program pulses becomes the unique distribution (Vthi)/a step voltage (Vstep). That is, when the step voltage is low, a more dense distribution width can be obtained, but the number of pulses is increased.
  • FIG. 2 is a diagram showing a difference in the program speed according to cell characteristics or the number of program/erase cycles in a typical nonvolatile memory device.
  • the same program voltage is applied in terms of the characteristics of each cell, there is a difference in the threshold voltage. As shown in FIG. 2( a ), cells having relatively high threshold voltages are called fast cells, and cells having relatively low threshold voltages are called slow cells. Although the same program voltage is applied, there is a difference in the program speed.
  • the program speed refers to voltage of a program pulse applied in the state in which programming has been completed.
  • FIG. 2( b ) shows a difference in the threshold voltage distribution according to the number of program/erase cycles.
  • the program speed can be defined as the number of program pulses applied until the program is completed. Therefore, a program start voltage should be set low in consideration of an increase in the program speed.
  • FIG. 3 is a flowchart illustrating a method of programming a nonvolatile memory device in accordance with an embodiment of the present invention.
  • an n th page of data is input.
  • a program operation is typically performed on a page basis.
  • Data to be programmed into the n th page is input to a page buffer, and the level of voltage applied to a sense node SO is changed according to the data. Meanwhile, a program pulse application number value m is reset to 1.
  • the program operation is performed according to a program start voltage.
  • a program voltage is applied to word lines including target program cells according to the ISPP method.
  • a program verify operation is performed for determining whether the target program cells have been programmed to have at least a reference voltage (step 330 )
  • the verify operation is carried out according to the verify operation of a typical nonvolatile memory device. That is, the voltage level of the bit line is changed depending on whether the threshold voltage of the target verify cells has risen higher than the reference voltage. Typically, only when the threshold voltage of the target verify cells has risen higher than the reference voltage, the voltage level of the bit line remains intact, and otherwise the voltage level of the bit line is discharged to a low level.
  • step 340 a determination is made whether all target program cells have been programmed. If, all target program cells have been programmed to have at least the reference voltage as their threshold voltages, the operation proceeds to step 350 . If, there is a cell having a threshold voltage that is lower than the reference voltage, the program voltage is increased by an increment or a step voltage (step 342 ). The program pulse application number value m is increased by 1 (step 344 ). The program operation is performed again (step 320 ).
  • the program start voltage is reset (i.e., recalibrated) according to the program pulse application number m (step 350 ).
  • a program start voltage can be increased by a number corresponding to a difference in the program pulse application number and the critical value. For example, when the program pulse application number is 13 and the critical value is 10, the program start voltage can be increased by 3 times the step voltage.
  • a program start voltage can be decreased by a number corresponding to a difference in the program pulse application number and the critical value. For example, when the program pulse application number is 7 and the critical value is 10, the program start voltage can be decreased by 3 times the step voltage. In other embodiments, the program start voltage may be decreased by a different amount.
  • the program operation is repeated using the recalibrated program start voltage in steps 360 , 362 , 310 , and 320 .
  • step 350 Since the program start voltage has been recalibrated in step 350 , the program operation is performed according to the corresponding voltage.
  • a program voltage pulse application number is counted on a page basis, and a program start voltage is reset (or recalibrated) based on the counted program voltage pulse application number.
  • a program operation is performed on a next page using the recalibrated program start voltage.
  • FIG. 4 is a flowchart illustrating a method of erasing and programming a nonvolatile memory device in accordance with another embodiment of the present invention.
  • a post program start voltage may be set according to an erase pulse application number. It is known that the post program operation is performed in order to narrow the threshold voltage distribution of the entire erased cells after an erase operation is carried out. In other words, a program operation is performed on the erased cells, but performed to control a maximum threshold voltage not to exceed 0V, so that threshold voltage distributions of the entire erased cells are narrowed. Accordingly, the post program operation is performed according to an operation similar to a program operation.
  • an erase operation is performed.
  • the erase operation is performed on a block basis and is carried out according to a typical incremental step pulse erasing (ISPE) method.
  • ISPE incremental step pulse erasing
  • an erase verify operation is performed in step 420 .
  • step 430 It is then determined whether all the target erase cells have been erased in step 430 . If there are any cells that have not been erased, an erase voltage is increased by a step voltage, and the erase operation is repeated in steps 432 , 434 , and 410 . Thus, an erase pulse application number is also increased by 1.
  • a program start voltage or a post program start voltage is set according to an erase pulse application number in step 440 .
  • the program speed is determined to be fast and therefore the program start voltage is lowered.
  • the threshold voltage of a program state There is a tendency for the threshold voltage of a program state to rise as the number of program/erase cycles increases.
  • a program start voltage is lowered by a number corresponding to a difference between the erase pulse application number and the critical value. For example, when the erase pulse application number is 13 and the critical value is 10, the program start voltage is lowered by 3 times the step voltage. In other embodiments, the program start voltage may be lowered by a different amount.
  • the program speed is determined to be slow and therefore the program start voltage is raised.
  • a program start voltage is increased by a number corresponding to a difference between the erase pulse application number and the critical value. For example, when the erase pulse application number is 7 and the critical value is 10, the program start voltage is lowered by 3 times the step voltage. In other embodiments, the program start voltage may be increased by a different amount.
  • the program start voltage remains the same.
  • a post program operation and a verify operation on the post program operation are then performed in step 450 .
  • the post program operation is performed using the set post program start voltage in step 440 .
  • a program operation and a verify operation on the program operation are then performed in step 460 .
  • the program operation is carried out using the set program start voltage in step 440 .
  • the program operation is performed according to the above ISPP method.
  • the program operation may be performed using the embodiment described in FIG. 3 , where the program start voltage is recalibrated after each page of data is programmed.
  • an erase pulse application number is counted, and a program start voltage and a post program start voltage is recalibrated based on the counted erase pulse application number.
  • a program operation or a post program operation is performed using the recalibrated program start voltage or the recalibrated post program start voltage.
  • FIG. 5 is a flowchart illustrating a method of programming a nonvolatile memory device in accordance with still another embodiment of the present invention.
  • An erase operation is completed in step 510 .
  • the erase operation is performed on a block basis and is performed using a typical ISPE method.
  • a post program operation is then performed in step 520 .
  • the post program operation is performed so as to narrow the threshold distribution of the erased cells.
  • a detailed operation of the post program operation is similar to a program operation. That is, the post program operation is carried out according to the ISPP method.
  • a post program start voltage can be a start voltage based on the erase pulse application number according to the embodiment of FIG. 4 .
  • a verify operation is performed on the post program operation in step 530 .
  • the cells are programmed to have 0V or less, it is determined that the post program operation has been completed.
  • step 540 it is then determined whether the post program operation on the erase cells has been completed in step 540 . If, the post program operation is determined to have been completed, a next operation (step 550 ) is performed.
  • a program voltage is increased by a step voltage, and the post program operation is repeated in steps 542 , 544 , and 520 .
  • a post program pulse application number is also increased by 1.
  • the program start voltage is recalibrated according to a post program pulse application number in step 550 .
  • the program speed is determined to be slow and the post program start voltage is increased.
  • a program start voltage is increased by a number corresponding to a difference between the post program pulse application number and the critical value. For example, when the post program pulse application number is 13 and the critical value is 10, the program start voltage is increased by 3 times the step voltage. In other embodiments, the program start voltage may be increased by a different amount.
  • the program speed is determined to be fast and the post program start voltage is decreased.
  • a program start voltage is decreased by a number corresponding to a difference between the post program pulse application number and the critical value. For example, when the post program pulse application number is 7 and the critical value is 10, the program start voltage is decreased by 3 times the step voltage. In other embodiments, the program start voltage may be decreased by a different amount.
  • the post program start voltage remains the same.
  • a program operation and a verify operation on the program operation are then performed in step 560 .
  • the program operation is performed according to the set program start voltage.
  • the program operation is performed according to the above ISPP method.
  • the program operation may be performed by the embodiment described in FIG. 3 , where the program start voltage is recalibrated after each page of data is programmed.
  • a post program pulse application number is counted, and a program start voltage is recalibrated based on the counted post program pulse application number.
  • a program operation is performed using the recalibrated program start voltage.
  • FIG. 6 is a flowchart illustrating a method of programming a nonvolatile memory device in accordance with further still another embodiment of the present invention.
  • the present embodiment relates to programming multi-level cells where a plurality of logical pages are defined within one physical page.
  • An n th logical page of data is input to a specific physical page in step 610 .
  • a program operation is typically performed on a page basis.
  • the N th logical page of data to be programmed into a specific physical page is input to a page buffer, and the voltage level applied to a sense node SO is changed according to the data. Meanwhile, a program pulse application number value m is reset to 1.
  • the program operation is performed according to a program start voltage.
  • a program voltage is applied according to the ISPP method.
  • a program verify operation for determining whether target program cells have been programmed to have a reference voltage or more is then performed in step 630 .
  • the verify operation is performed according to the verify operation of a typical nonvolatile memory device.
  • step 640 It is then determined whether the threshold voltages of all target program cells have been programmed to be at least the reference voltage (step 640 ). If the threshold voltages of the target program cells have all been programmed to be at least the reference voltage, a next operation (step 650 ) is performed. If there is a cell with a threshold voltage that is lower than the reference voltage, the program voltage is increased by a step voltage, and the program operation is repeated in steps 642 , 644 , and 620 . At this time, since the program operation is repeated, a program pulse application number is increased by 1.
  • the program start voltage is recalibrated according to a program pulse application number (step 650 ).
  • the program speed is determined to be slow and the program start voltage is increased.
  • a program start voltage is increased by a number corresponding to a difference between the program pulse application number and the critical value. For example, when the post program pulse application number is 13 and the critical value is 10, the program start voltage is increased by 3 times the step voltage. In other embodiments, the program start voltage may be increased by a different amount.
  • the program speed is determined to be fast, and the program start voltage is decreased.
  • a program start voltage is decreased by a number corresponding to a difference between the program pulse application number and the critical value. For example, when the post program pulse application number is 7 and the critical value is 10, the program start voltage is decreased by 3 times the step voltage. In other embodiments, the program start voltage may be decreased by a different amount.
  • step 660 the program operation is repeated using the recalibrated program start voltage in step 660 , 662 , 610 , and 620 .
  • step 650 Since the program start voltage has been recalibrated in step 650 , the program operation is performed according to a corresponding voltage.
  • a program voltage pulse application number is counted on a logical-page basis, and a program start voltage is recalibrated based on the counted program voltage pulse application number.
  • a program operation is performed on a following page using the recalibrated program start voltage.
  • a program start voltage can be set differently according to a program speed. That is, at the time of a program operation for a page of data, a program speed is measured by counting a program pulse application number and, at the time of a program operation of a following page of data, a program start voltage is recalibrated based on the measured program speed. That is, a program start voltage can be changed according to a program speed. Alternatively, various methods of measuring a program speed may be used. Further, a program speed can be measured on the basis of an erase pulse application number or a post program pulse application number in addition to the program pulse application number. According to the configurations, the programming time can be reduced. Further, distributions of respective cells after a program operation can be maintained uniformly.

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Abstract

The present invention relates to a method of programming a nonvolatile memory device. A method of programming a nonvolatile memory device in accordance with an aspect of the present invention can include performing a program operation on a first page, counting a program pulse application number until the program operation on the first page is completed, comparing the counted program pulse application number and a critical value and resetting a program start voltage based on the comparison result, and performing a program operation on a second page using the reset program start voltage.

Description

CROSS-REFERENCES TO RELATED APPLICATIONS
The present application claims priority to Korean patent application number 10-2008-0048167, filed on May 23, 2008, which is incorporated by reference in its entirety.
BACKGROUND OF THE INVENTION
The present invention relates to a method of programming nonvolatile memory devices.
In recent years, there is an increasing demand for nonvolatile memory devices which can be electrically programmed and erased and does not need to be periodically refreshed.
A nonvolatile memory device is a device that enables electrical program/erase operations, and performs the program and erase operations by changing the threshold voltage of a cell as electrons are moved by a strong electric field applied to a thin oxide layer.
The nonvolatile memory device typically includes a memory cell array in which cells for storing data are arranged in matrix form, and a page buffer for writing data into specific cells of the memory cell array or reading data stored in a specific cell. The page buffer includes bit line pairs coupled to specific memory cells and a register for temporarily storing data to be written into the memory cell array or reading data from a specific cell of the memory cell array and temporarily storing the read data. It also includes a sense node for sensing the voltage level of a specific bit line or a specific register, and a bit line select unit for controlling whether the specific bit line and the sense node have been coupled or not.
In a program operation of this nonvolatile memory device, there occurs a phenomenon in which a program speed changes according to the characteristics of cells and in the number of program/erase cycles. Meanwhile, the program operation of a nonvolatile memory device is carried out using an incremental step pulse program (ISPP) method. It is necessary to set a program start voltage in consideration of the program speed of each cell.
BRIEF SUMMARY OF THE INVENTION
The present invention relates to a method of programming a nonvolatile memory device, which can set a program start voltage differently according to the program speed of each cell.
A method of programming a nonvolatile memory device in accordance with an aspect of the present invention includes performing a program operation on a first page, counting a program pulse application number until the program operation on the first page is completed, comparing the counted program pulse application number and a critical value and resetting a program start voltage based on the comparison result, and performing a program operation on a second page using the reset program start voltage.
A method of programming a nonvolatile memory device in accordance with another aspect of the present invention includes performing an erase operation, counting an erase pulse application number until the erase operation is completed, comparing the counted erase pulse application number and a critical value and setting a program start voltage based on the comparison result, and performing a program operation using the set program start voltage.
A method of programming a nonvolatile memory device in accordance with still another aspect of the present invention includes performing an erase operation, counting an erase pulse application number until the erase operation is completed, comparing the counted erase pulse application number and a critical value and setting a post program start voltage based on the comparison result, performing a post program operation and a verify operation using the set post program start voltage, and performing a program operation on cells on which the post program operation has been completed.
A method of programming a nonvolatile memory device in accordance with further still another aspect of the present invention includes providing a memory cell on which an erase operation has been completed, performing a post program operation on the memory cell, counting a post program pulse application number until the post program operation is completed, comparing the counted post program pulse application number and a critical value and setting a program start voltage based on the comparison result, performing a program operation and a verify operation using the set program start voltage.
A method of programming a nonvolatile memory device in accordance with further still another aspect of the present invention includes performing a program operation of a first logical page with respect to a first physical page, counting a program pulse application number until the program operation of the first logical page is completed, comparing the counted program pulse application number and a critical value and resetting a program start voltage based on the comparison result, and performing a program operation of a second logical page with respect to the first physical page using the reset program start voltage.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a diagram showing a typical ISPP method of a nonvolatile memory device;
FIG. 2 is a diagram showing a difference in the program speed according to characteristics of cells or the number of program/erase cycles in a typical nonvolatile memory device;
FIG. 3 is a flowchart illustrating a method of programming a nonvolatile memory device in accordance with an embodiment of the present invention;
FIG. 4 is a flowchart illustrating a method of programming a nonvolatile memory device in accordance with another embodiment of the present invention;
FIG. 5 is a flowchart illustrating a method of programming a nonvolatile memory device in accordance with still another embodiment of the present invention; and
FIG. 6 is a flowchart illustrating a method of programming a nonvolatile memory device in accordance with further still another embodiment of the present invention.
 DESCRIPTION OF SPECIFIC EMBODIMENT
Specific embodiments according to the present invention will be described with reference to the accompanying drawings. However, the present invention is not limited to the disclosed embodiment, but may be implemented in various ways. The embodiments are provided to complete the disclosure of the present invention and to allow those having ordinary skill in the art to understand the scope of the present invention. The present invention is defined by the category of the claims.
FIG. 1 is a diagram showing a typical ISPP method of a nonvolatile memory device. The ISPP method includes applying a plurality of program pulses to a memory cell to be programmed and performing a verify operation immediately after the application of each program pulse. When an (n+1)th program pulse is applied the voltage is increased by a step pulse (Vstep) from the nth program pulse. If a program voltage is increased from a start voltage (Vstart) by a step voltage (Vstep) and applied as described above, the threshold voltage distribution of respective cells can be narrowed.
Meanwhile, the threshold voltage distributions of each cell has a wide unique distribution (Vthi) according to several process conditions, such as a channel width, a channel length, an oxide layer thickness, etc. of each memory cell. If an ISPP method is performed according to a specific step voltage (Vstep) when the unique distribution (Vthi) is 3V as shown in FIG. 1, the number of required program pulses becomes the unique distribution (Vthi)/a step voltage (Vstep). That is, when the step voltage is low, a more dense distribution width can be obtained, but the number of pulses is increased. It is also necessary to apply a program start voltage in consideration of a difference in the program speed according to the characteristics of each cell or the number of program/erase cycles (or E/W cycling number) as well as this unique distribution characteristic.
FIG. 2 is a diagram showing a difference in the program speed according to cell characteristics or the number of program/erase cycles in a typical nonvolatile memory device.
Although the same program voltage is applied in terms of the characteristics of each cell, there is a difference in the threshold voltage. As shown in FIG. 2( a), cells having relatively high threshold voltages are called fast cells, and cells having relatively low threshold voltages are called slow cells. Although the same program voltage is applied, there is a difference in the program speed. Here, the program speed refers to voltage of a program pulse applied in the state in which programming has been completed.
In this case, a problem arises because more program pulses need to be applied to cells having a slow program speed, i.e., the cells whose threshold voltages change by a smaller amount than others. For example, assuming that a step voltage (Vstep) is 200 mV and a difference in the program speed between cells is 1V, it can be seen that there is a difference in the program time by as many as 5 (1V/200 mV) pulses. In this case, five pulses must be additionally applied to the slow cell.
FIG. 2( b) shows a difference in the threshold voltage distribution according to the number of program/erase cycles. As the number of program/erase cycles increases, charges trapped at a floating gate increases. Although a low program voltage is applied, the threshold voltage rises abruptly. In other words, although the same program pulse is applied, the program speed of a cell having a large number of program/erase cycles becomes fast. The program speed can be defined as the number of program pulses applied until the program is completed. Therefore, a program start voltage should be set low in consideration of an increase in the program speed. For example, in the case in which a difference in the program speed of different cells whose difference in the number of program/erase cycles is 10K is 1V, when a step voltage (Vstep) is 200 mV, it can be seen that there is a difference in the speed as much as 5 (1V/200 mV) pulses. Accordingly, five pulses have to be applied to cells having a small number of program/erase cycles.
As described above, it can be seen that there is a difference in the program speed according to the characteristics of each cell or a difference in the number of program/erase cycles. When there is a difference in the program speed as described above, a program start voltage is set based on the fastest program speed. Accordingly, the time taken for a total program operation increases since more program pulses have to be applied to cells having a slow program speed.
FIG. 3 is a flowchart illustrating a method of programming a nonvolatile memory device in accordance with an embodiment of the present invention. At step 310 an nth page of data is input.
A program operation is typically performed on a page basis. Data to be programmed into the nth page is input to a page buffer, and the level of voltage applied to a sense node SO is changed according to the data. Meanwhile, a program pulse application number value m is reset to 1.
At step 320, the program operation is performed according to a program start voltage. A program voltage is applied to word lines including target program cells according to the ISPP method.
A program verify operation is performed for determining whether the target program cells have been programmed to have at least a reference voltage (step 330) The verify operation is carried out according to the verify operation of a typical nonvolatile memory device. That is, the voltage level of the bit line is changed depending on whether the threshold voltage of the target verify cells has risen higher than the reference voltage. Typically, only when the threshold voltage of the target verify cells has risen higher than the reference voltage, the voltage level of the bit line remains intact, and otherwise the voltage level of the bit line is discharged to a low level.
At step 340, a determination is made whether all target program cells have been programmed. If, all target program cells have been programmed to have at least the reference voltage as their threshold voltages, the operation proceeds to step 350. If, there is a cell having a threshold voltage that is lower than the reference voltage, the program voltage is increased by an increment or a step voltage (step 342). The program pulse application number value m is increased by 1 (step 344). The program operation is performed again (step 320).
On the other hand, all target program cells are determined to have at least the reference voltage as their threshold voltages, the program start voltage is reset (i.e., recalibrated) according to the program pulse application number m (step 350).
If the program pulse application number m when the program operation is completed is greater than a critical value (or reference value), a program speed is determined to be slow and therefore the program start voltage is increased. Here, a program start voltage can be increased by a number corresponding to a difference in the program pulse application number and the critical value. For example, when the program pulse application number is 13 and the critical value is 10, the program start voltage can be increased by 3 times the step voltage.
If the program pulse application number is smaller than the critical value when the program operation is completed (i.e., at step 350), a program speed is determined to be fast and therefore the program start voltage is lowered. Here, a program start voltage can be decreased by a number corresponding to a difference in the program pulse application number and the critical value. For example, when the program pulse application number is 7 and the critical value is 10, the program start voltage can be decreased by 3 times the step voltage. In other embodiments, the program start voltage may be decreased by a different amount.
If the program pulse application number is identical to the critical value when the program operation is completed, the program start voltage remains the same.
Next, if there is another page to be programmed, the program operation is repeated using the recalibrated program start voltage in steps 360, 362, 310, and 320.
Since the program start voltage has been recalibrated in step 350, the program operation is performed according to the corresponding voltage.
As described above, a program voltage pulse application number is counted on a page basis, and a program start voltage is reset (or recalibrated) based on the counted program voltage pulse application number. A program operation is performed on a next page using the recalibrated program start voltage.
FIG. 4 is a flowchart illustrating a method of erasing and programming a nonvolatile memory device in accordance with another embodiment of the present invention. Meanwhile, a post program start voltage may be set according to an erase pulse application number. It is known that the post program operation is performed in order to narrow the threshold voltage distribution of the entire erased cells after an erase operation is carried out. In other words, a program operation is performed on the erased cells, but performed to control a maximum threshold voltage not to exceed 0V, so that threshold voltage distributions of the entire erased cells are narrowed. Accordingly, the post program operation is performed according to an operation similar to a program operation.
In the present invention, a method of setting a post program start voltage according to an erase pulse application number is described as an example.
At step 410 an erase operation is performed. The erase operation is performed on a block basis and is carried out according to a typical incremental step pulse erasing (ISPE) method.
Next, an erase verify operation is performed in step 420. In this operation, it is determined whether the threshold voltage of target erase cells is lower than 0V.
It is then determined whether all the target erase cells have been erased in step 430. If there are any cells that have not been erased, an erase voltage is increased by a step voltage, and the erase operation is repeated in steps 432, 434, and 410. Thus, an erase pulse application number is also increased by 1.
If all the target erase cells have been erased, a program start voltage or a post program start voltage is set according to an erase pulse application number in step 440.
If the erase pulse application number when the erase operation is completed is greater than a critical value, the program speed is determined to be fast and therefore the program start voltage is lowered. There is a tendency for the threshold voltage of a program state to rise as the number of program/erase cycles increases. Here, a program start voltage is lowered by a number corresponding to a difference between the erase pulse application number and the critical value. For example, when the erase pulse application number is 13 and the critical value is 10, the program start voltage is lowered by 3 times the step voltage. In other embodiments, the program start voltage may be lowered by a different amount.
If the erase pulse application number when the erase operation is completed is smaller than a critical value, the program speed is determined to be slow and therefore the program start voltage is raised. Here, a program start voltage is increased by a number corresponding to a difference between the erase pulse application number and the critical value. For example, when the erase pulse application number is 7 and the critical value is 10, the program start voltage is lowered by 3 times the step voltage. In other embodiments, the program start voltage may be increased by a different amount.
If the erase pulse application number when the erase operation is completed is identical to a critical value, the program start voltage remains the same.
A post program operation and a verify operation on the post program operation are then performed in step 450. At this time, the post program operation is performed using the set post program start voltage in step 440.
A program operation and a verify operation on the program operation are then performed in step 460. At this time, the program operation is carried out using the set program start voltage in step 440. Here, the program operation is performed according to the above ISPP method. Alternatively, the program operation may be performed using the embodiment described in FIG. 3, where the program start voltage is recalibrated after each page of data is programmed.
As described above, an erase pulse application number is counted, and a program start voltage and a post program start voltage is recalibrated based on the counted erase pulse application number. A program operation or a post program operation is performed using the recalibrated program start voltage or the recalibrated post program start voltage.
FIG. 5 is a flowchart illustrating a method of programming a nonvolatile memory device in accordance with still another embodiment of the present invention. An erase operation is completed in step 510. The erase operation is performed on a block basis and is performed using a typical ISPE method.
A post program operation is then performed in step 520. The post program operation is performed so as to narrow the threshold distribution of the erased cells. A detailed operation of the post program operation is similar to a program operation. That is, the post program operation is carried out according to the ISPP method. Here, a post program start voltage can be a start voltage based on the erase pulse application number according to the embodiment of FIG. 4.
Next, a verify operation is performed on the post program operation in step 530. Typically, when the cells are programmed to have 0V or less, it is determined that the post program operation has been completed.
At step 540, it is then determined whether the post program operation on the erase cells has been completed in step 540. If, the post program operation is determined to have been completed, a next operation (step 550) is performed.
However, if it is determined that the post program operation has not been completed, a program voltage is increased by a step voltage, and the post program operation is repeated in steps 542, 544, and 520. Thus, a post program pulse application number is also increased by 1.
If the post program operation has been completed, the program start voltage is recalibrated according to a post program pulse application number in step 550.
If the post program pulse application number when the post program operation is completed is greater than a critical value, the program speed is determined to be slow and the post program start voltage is increased. Here, a program start voltage is increased by a number corresponding to a difference between the post program pulse application number and the critical value. For example, when the post program pulse application number is 13 and the critical value is 10, the program start voltage is increased by 3 times the step voltage. In other embodiments, the program start voltage may be increased by a different amount.
If the post program pulse application number when the post program operation is completed is smaller than a critical value, the program speed is determined to be fast and the post program start voltage is decreased. Here, a program start voltage is decreased by a number corresponding to a difference between the post program pulse application number and the critical value. For example, when the post program pulse application number is 7 and the critical value is 10, the program start voltage is decreased by 3 times the step voltage. In other embodiments, the program start voltage may be decreased by a different amount.
If the post program pulse application number when the post program operation is completed is identical to a critical value, the post program start voltage remains the same.
A program operation and a verify operation on the program operation are then performed in step 560. Here, the program operation is performed according to the set program start voltage. The program operation is performed according to the above ISPP method. Alternatively, the program operation may be performed by the embodiment described in FIG. 3, where the program start voltage is recalibrated after each page of data is programmed.
As described above, a post program pulse application number is counted, and a program start voltage is recalibrated based on the counted post program pulse application number. A program operation is performed using the recalibrated program start voltage.
FIG. 6 is a flowchart illustrating a method of programming a nonvolatile memory device in accordance with further still another embodiment of the present invention. The present embodiment relates to programming multi-level cells where a plurality of logical pages are defined within one physical page.
An nth logical page of data is input to a specific physical page in step 610.
A program operation is typically performed on a page basis. The Nth logical page of data to be programmed into a specific physical page is input to a page buffer, and the voltage level applied to a sense node SO is changed according to the data. Meanwhile, a program pulse application number value m is reset to 1.
At step 620, the program operation is performed according to a program start voltage. A program voltage is applied according to the ISPP method.
A program verify operation for determining whether target program cells have been programmed to have a reference voltage or more is then performed in step 630. The verify operation is performed according to the verify operation of a typical nonvolatile memory device.
It is then determined whether the threshold voltages of all target program cells have been programmed to be at least the reference voltage (step 640). If the threshold voltages of the target program cells have all been programmed to be at least the reference voltage, a next operation (step 650) is performed. If there is a cell with a threshold voltage that is lower than the reference voltage, the program voltage is increased by a step voltage, and the program operation is repeated in steps 642, 644, and 620. At this time, since the program operation is repeated, a program pulse application number is increased by 1.
If the threshold voltages of the target program cells have all been programmed to have at least the reference voltage, the program start voltage is recalibrated according to a program pulse application number (step 650).
If the program pulse application number when the program operation is completed is greater than a critical value, the program speed is determined to be slow and the program start voltage is increased. Here, a program start voltage is increased by a number corresponding to a difference between the program pulse application number and the critical value. For example, when the post program pulse application number is 13 and the critical value is 10, the program start voltage is increased by 3 times the step voltage. In other embodiments, the program start voltage may be increased by a different amount.
If the program pulse application number when the program operation is completed is smaller than a critical value, the program speed is determined to be fast, and the program start voltage is decreased. Here, a program start voltage is decreased by a number corresponding to a difference between the program pulse application number and the critical value. For example, when the post program pulse application number is 7 and the critical value is 10, the program start voltage is decreased by 3 times the step voltage. In other embodiments, the program start voltage may be decreased by a different amount.
If the program pulse application number when the program operation is completed is identical to a critical value, the program start voltage remains the same.
Next, if there are any more logical pages that need to be programmed, the program operation is repeated using the recalibrated program start voltage in step 660, 662, 610, and 620.
Since the program start voltage has been recalibrated in step 650, the program operation is performed according to a corresponding voltage.
As described above, a program voltage pulse application number is counted on a logical-page basis, and a program start voltage is recalibrated based on the counted program voltage pulse application number. A program operation is performed on a following page using the recalibrated program start voltage.
In accordance with the above configurations of the present invention, a program start voltage can be set differently according to a program speed. That is, at the time of a program operation for a page of data, a program speed is measured by counting a program pulse application number and, at the time of a program operation of a following page of data, a program start voltage is recalibrated based on the measured program speed. That is, a program start voltage can be changed according to a program speed. Alternatively, various methods of measuring a program speed may be used. Further, a program speed can be measured on the basis of an erase pulse application number or a post program pulse application number in addition to the program pulse application number. According to the configurations, the programming time can be reduced. Further, distributions of respective cells after a program operation can be maintained uniformly.
The embodiments disclosed herein have been proposed to allow a person skilled in the art to easily implement the present invention, and the person skilled in the part may implement the present invention in various ways. Therefore, the scope of the present invention is not limited by or to the embodiments as described above, and should be construed to be defined only by the appended claims and their equivalents.

Claims (8)

1. A method of programming a nonvolatile memory device, the method comprising:
programming a first page of data until the first page of data has been programmed completely, the program voltages including a first program start voltage that is applied to the selected word line as an initial program voltage, each succeeding program voltage applied after the first program start voltage being increased by a given voltage to the previous program voltage; determining the number of times the program voltages has been applied to the selected word line to complete the programming of the first page;
comparing the determined number to a reference value;
defining a second program start voltage for use in programming a second page of data based on the compared result; and
performing the second page of data using the second program start voltage.
2. The method of claim 1, wherein the defining of the second program start voltage comprises:
defining the second program start voltage to be higher than the first program start voltage when the determined number is greater than the reference value;
defining the second program start voltage to be lower than the first program start voltage when the determined number is less than the reference value; and
defining the second program start voltage to be same as the first program start voltage when the determined number is the same as the reference value.
3. The method of claim 2, wherein the second program start voltage is obtained by increasing or decreasing the first program start voltage by a step voltage times the difference between the determined number and the reference value.
4. The method of claim 2, wherein the determined number is a program pulse application number.
5. The method of claim 4, wherein determining the program pulse application number comprises:
performing a program verify operation; and
when there is a target program cell programmed to have a reference voltage or less, increasing the program voltage by a step voltage and increasing the program pulse application number by 1.
6. A method of programming a nonvolatile memory device, the method comprising:
performing a program operation of a first logical page associated with a first physical page;
counting a program pulse application number once the program operation of the first logical page is completed;
comparing the counted program pulse application number and a reference value;
defining a program start voltage based on the compared result; and
performing a program operation of a second logical page with respect to the first physical page using the defined program start voltage.
7. The method of claim 6, wherein the defining of the program start voltage comprises:
when the program pulse application number is greater than the reference value, increasing the program start voltage;
when the program pulse application number is smaller than the reference value, decreasing the program start voltage; and
when the program pulse application number is identical to the reference value, maintaining the program start voltage.
8. The method of claim 6, wherein the counting of the program pulse application number comprises:
performing a program verify operation; and
when there is a target program cell programmed to have a reference voltage or less, increasing a program voltage by a step voltage and increasing the program pulse application number by 1.
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Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100208524A1 (en) * 2009-02-19 2010-08-19 Micron Technology, Inc. Soft landing for desired program threshold voltage
US20110138111A1 (en) * 2009-12-03 2011-06-09 Samsung Electronics Co., Ltd. Flash memory device and method of programming same
US8570802B2 (en) 2011-05-12 2013-10-29 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device capable of speeding up write operation
US9064580B2 (en) 2012-01-06 2015-06-23 Powerchip Technology Corporation Nonvolatile semiconductor memory device and write-in method thereof
US9318191B2 (en) 2012-10-11 2016-04-19 Samsung Electronics Co., Ltd. Programming nonvolatile memory device using program voltage with variable offset between programming state distributions
TWI611402B (en) * 2015-12-31 2018-01-11 旺宏電子股份有限公司 Method for programming memory cells and applications thereof
US10643720B2 (en) 2018-05-23 2020-05-05 Sandisk Technologies Llc Bit line voltage control for damping memory programming
US10818358B2 (en) 2017-09-22 2020-10-27 Toshiba Memory Corporation Memory system including a semiconductor memory having a memory cell and a write circuit configured to write data to the memory cell

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5292052B2 (en) * 2008-10-21 2013-09-18 力晶科技股▲ふん▼有限公司 Nonvolatile semiconductor memory device and writing method thereof
US7839690B2 (en) 2008-12-11 2010-11-23 Sandisk Corporation Adaptive erase and soft programming for memory
JP2011198435A (en) * 2010-03-23 2011-10-06 Toshiba Corp Nonvolatile semiconductor memory device
KR101138101B1 (en) * 2010-05-27 2012-04-24 에스케이하이닉스 주식회사 Program method of a non-volatile memory device
JP5566797B2 (en) * 2010-07-02 2014-08-06 株式会社東芝 Nonvolatile semiconductor memory device
US8351276B2 (en) * 2010-07-13 2013-01-08 Freescale Semiconductor, Inc. Soft program of a non-volatile memory block
JP2012027969A (en) * 2010-07-21 2012-02-09 Toshiba Corp Nonvolatile semiconductor memory device
KR101222063B1 (en) * 2011-02-28 2013-01-15 에스케이하이닉스 주식회사 Non volatile memory device and operating method thereof
JP5364750B2 (en) 2011-03-25 2013-12-11 株式会社東芝 Memory system and control method of nonvolatile memory device
US8537623B2 (en) 2011-07-07 2013-09-17 Micron Technology, Inc. Devices and methods of programming memory cells
KR20130047400A (en) 2011-10-31 2013-05-08 삼성전자주식회사 Nonvolatile memory and controlling method thereof
US8842477B2 (en) * 2012-06-01 2014-09-23 Spansion Llc Method, apparatus, and manufacture for flash memory adaptive algorithm
US8902667B2 (en) * 2012-07-25 2014-12-02 Freescale Semiconductor, Inc. Methods and systems for adjusting NVM cell bias conditions for program/erase operations to reduce performance degradation
US8760923B2 (en) * 2012-08-28 2014-06-24 Freescale Semiconductor, Inc. Non-volatile memory (NVM) that uses soft programming
US8861258B2 (en) 2013-02-21 2014-10-14 Sandisk 3D Llc Set/reset algorithm which detects and repairs weak cells in resistive-switching memory device
CN104575596A (en) * 2013-10-10 2015-04-29 北京兆易创新科技股份有限公司 Decline resistant flash memory and decline resistant method
JP5784788B2 (en) * 2014-04-16 2015-09-24 力晶科技股▲ふん▼有限公司 Nonvolatile semiconductor memory device and writing method thereof
KR102235516B1 (en) 2014-09-30 2021-04-05 삼성전자주식회사 Memory system and operating method having erase control unit
KR20170011644A (en) * 2015-07-23 2017-02-02 에스케이하이닉스 주식회사 Semiconductor memory device and operating method thereof
US9953703B2 (en) 2015-10-16 2018-04-24 Samsung Electronics Co., Ltd. Programming method of non volatile memory device
KR102449196B1 (en) 2016-01-15 2022-09-29 삼성전자주식회사 Nonvolatile memory device and program method of a nonvolatile memory device
CN110556146A (en) * 2018-06-01 2019-12-10 北京兆易创新科技股份有限公司 programming method and device of storage unit, electronic equipment and storage medium
JP7295267B2 (en) 2019-05-22 2023-06-20 長江存儲科技有限責任公司 Method for programming multi-level cell NAND flash memory device and MLC NAND flash memory device
CN110299172A (en) * 2019-07-04 2019-10-01 合肥联诺科技有限公司 A kind of programmed process method shortening FLASH programming time
JP2022040515A (en) * 2020-08-31 2022-03-11 ウィンボンド エレクトロニクス コーポレーション Flash memory and programming method
JP7476061B2 (en) 2020-09-15 2024-04-30 キオクシア株式会社 Semiconductor memory device
KR20220049650A (en) 2020-10-14 2022-04-22 삼성전자주식회사 Memory device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20040058533A (en) 2002-12-27 2004-07-05 주식회사 하이닉스반도체 EPROM program mode entering circuit
KR20070094104A (en) 2006-03-16 2007-09-20 삼성전자주식회사 Phase change memory device supporting program suspend/resume mode and program method thereof
US20090257282A1 (en) * 2006-12-27 2009-10-15 Teruhiko Kamei Non-volatile storage system with initial programming voltage based on trial

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05182480A (en) * 1991-12-28 1993-07-23 Sony Corp Programmable read only memory
JP3737525B2 (en) * 1994-03-11 2006-01-18 株式会社東芝 Semiconductor memory device
JP3184082B2 (en) * 1995-11-24 2001-07-09 日本電気株式会社 Nonvolatile semiconductor memory device
KR0185611B1 (en) * 1995-12-11 1999-04-15 김광호 High voltage level optimization circuit of eeprom and its method
JP3790654B2 (en) * 2000-02-15 2006-06-28 シャープ株式会社 Control method for nonvolatile semiconductor memory
JP2002133887A (en) * 2000-10-31 2002-05-10 Matsushita Electric Ind Co Ltd Non-volatile semiconductor memory
US6549467B2 (en) * 2001-03-09 2003-04-15 Micron Technology, Inc. Non-volatile memory device with erase address register
US6452836B1 (en) * 2001-03-09 2002-09-17 Micron Technology, Inc. Non-volatile memory device with erase cycle register
US6515909B1 (en) * 2001-10-05 2003-02-04 Micron Technology Inc. Flash memory device with a variable erase pulse
KR100550789B1 (en) * 2002-07-18 2006-02-08 주식회사 하이닉스반도체 Circuit for supplying program/erase voltage in a flash memory device
KR100541819B1 (en) * 2003-12-30 2006-01-10 삼성전자주식회사 Non-volatile semiconductor memory device using differential start program voltage and program method therefore
JP2005276428A (en) * 2005-04-11 2005-10-06 Toshiba Corp Nonvolatile semiconductor storage device
US7339834B2 (en) * 2005-06-03 2008-03-04 Sandisk Corporation Starting program voltage shift with cycling of non-volatile memory
JP2008262623A (en) * 2007-04-11 2008-10-30 Toshiba Corp Nonvolatile semiconductor memory device
JP5032290B2 (en) * 2007-12-14 2012-09-26 株式会社東芝 Nonvolatile semiconductor memory device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20040058533A (en) 2002-12-27 2004-07-05 주식회사 하이닉스반도체 EPROM program mode entering circuit
KR20070094104A (en) 2006-03-16 2007-09-20 삼성전자주식회사 Phase change memory device supporting program suspend/resume mode and program method thereof
US20090257282A1 (en) * 2006-12-27 2009-10-15 Teruhiko Kamei Non-volatile storage system with initial programming voltage based on trial

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100208524A1 (en) * 2009-02-19 2010-08-19 Micron Technology, Inc. Soft landing for desired program threshold voltage
US8223551B2 (en) * 2009-02-19 2012-07-17 Micron Technology, Inc. Soft landing for desired program threshold voltage
US8773912B2 (en) 2009-02-19 2014-07-08 Micron Technology, Inc. Soft landing for desired program threshold voltage
US20110138111A1 (en) * 2009-12-03 2011-06-09 Samsung Electronics Co., Ltd. Flash memory device and method of programming same
US8441859B2 (en) 2009-12-03 2013-05-14 Samsung Electronics Co., Ltd. Flash memory device and method of programming same
US8705284B2 (en) 2009-12-03 2014-04-22 Samsung Electronics Co., Ltd. Flash memory device and method of programming same
US8570802B2 (en) 2011-05-12 2013-10-29 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device capable of speeding up write operation
US9064580B2 (en) 2012-01-06 2015-06-23 Powerchip Technology Corporation Nonvolatile semiconductor memory device and write-in method thereof
US9318191B2 (en) 2012-10-11 2016-04-19 Samsung Electronics Co., Ltd. Programming nonvolatile memory device using program voltage with variable offset between programming state distributions
TWI611402B (en) * 2015-12-31 2018-01-11 旺宏電子股份有限公司 Method for programming memory cells and applications thereof
US10818358B2 (en) 2017-09-22 2020-10-27 Toshiba Memory Corporation Memory system including a semiconductor memory having a memory cell and a write circuit configured to write data to the memory cell
US11410729B2 (en) 2017-09-22 2022-08-09 Kioxia Corporation Memory system including a semiconductor memory having a memory cell and a write circuit configured to write data to the memory cell
US11657875B2 (en) 2017-09-22 2023-05-23 Kioxia Corporation Semiconductor memory device configured to output write parameter and memory system including the same
US11869596B2 (en) 2017-09-22 2024-01-09 Kioxia Corporation Memory system including a semiconductor memory having a memory cell and a write circuit configured to write data to the memory cell
US10643720B2 (en) 2018-05-23 2020-05-05 Sandisk Technologies Llc Bit line voltage control for damping memory programming
US11011242B2 (en) 2018-05-23 2021-05-18 Sandisk Technologies Llc Bit line voltage control for damping memory programming

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US20090285028A1 (en) 2009-11-19
US8339864B2 (en) 2012-12-25
US8254183B2 (en) 2012-08-28
JP2009283117A (en) 2009-12-03
KR20090121983A (en) 2009-11-26
JP2013062022A (en) 2013-04-04
CN101587748A (en) 2009-11-25
US20110122704A1 (en) 2011-05-26
KR100953045B1 (en) 2010-04-14
US20110122705A1 (en) 2011-05-26

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