JP2002133887A - Non-volatile semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a non-volatile semiconductor memory in which increasing rewriting operation speed of data for a non-volatile semiconductor memory and reducing power consumption can be realized. SOLUTION: A non-volatile semiconductor memory is provided with a counter 14 counting the number of times of rewriting of data of a memory array 1, a power source control section varies voltage outputted to a decoding means 2 from a voltage generating means 12 on the basis of a count value of the counter 14, the deterioration of a rewriting time due to the repetition of rewriting is prevented and a rewriting time is averaged by varying selection voltage selecting a column direction and a row direction of the memory array.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile semiconductor memory device, and more particularly to a high-speed and low-power data rewriting operation for a non-volatile semiconductor memory.

[0002]

2. Description of the Related Art In a conventional nonvolatile semiconductor memory device, for example, when rewriting data in a flash memory which is one of nonvolatile semiconductor memories,
It requires a power supply of various voltages such as a positive high voltage and a negative high voltage. On the other hand, in recent years, the use of a single power supply has been promoted, and a type of boosting various power supplies for rewriting the data inside the nonvolatile semiconductor memory device has been provided.

The conventional nonvolatile semiconductor memory device will be described below with reference to FIGS. FIG.
FIG. 1 is a block diagram for explaining a configuration of a conventional nonvolatile semiconductor memory device. 11, the conventional nonvolatile semiconductor memory device includes a memory array 1, a decoding unit 2, a data detection unit 3, a memory control unit 4, a voltage generation unit 5, and a power supply control unit 6.

The memory array 1 is a data storage area in which MOS type memory cells having floating gates are arranged in a grid in the row and column directions, a decoding means 2 for selecting at least one memory cell, and a memory. Data detecting means 3 for detecting the state of the cell is connected.

[0005] The memory control unit 4 executes a mode signal, which is a signal indicating an operation mode such as data reading, erasing, or writing, an address designating a memory cell, and an operation mode indicated by the mode signal. The decoding unit 2 and the data detection unit 3 are controlled based on a timing signal indicating the timing.

The power control unit 6 controls a voltage output from the voltage generation means 5 based on the mode signal. The voltage generator 5 is controlled by the power supply controller 6 to generate a voltage inside the nonvolatile semiconductor memory device.
The generated voltage is supplied to the decoding means 2.

Hereinafter, the configuration of the voltage generating means 5 will be described with reference to FIGS. FIG. 12 is a diagram illustrating an example of a positive voltage regulator that forms the voltage generating unit 5, and FIG. 13 is a diagram illustrating an example of a negative voltage regulator that forms the voltage generating unit 5.

As shown in FIG. 12, the positive voltage regulator constituting the voltage generating means 5 is configured such that a positive voltage VPPIN boosted by a booster circuit such as a charge pump is supplied to a transistor M.
1 and the ground via the resistors R1 and R2, and the intermediate node N1
The output of the operational amplifier AMP1 which receives the potential and the reference voltage as inputs is connected to the transistor M1. The output voltage VPP is grounded via a transistor M3 having a positive voltage generation stop signal as a gate input. Further, the output voltage VPP is grounded via a smoothing capacitor CP.

The positive voltage regulator having the configuration shown in FIG. 12 compares the potential of the intermediate node N1 with the positive reference voltage and controls the transistor M1 to reduce the boosted positive voltage VPPIN to optimize the voltage. Output voltage VPP. Further, the transistor M3 is turned on when a positive voltage is not required, and the VPP potential is set to 0V. At this time, a booster circuit such as a charge pump is also stopped, so that charge cannot be supplied, and VPPIN becomes 0V. Note that the smoothing capacity CP
Is provided to alleviate a voltage drop with respect to a sudden output load change.

On the other hand, as shown in FIG. 13, in the negative voltage regulator constituting the voltage generating means 5, a negative voltage VBBIN boosted by a boosting circuit such as a charge pump is grounded via a transistor M2 and resistors R3 and R4. , The operational amplifier A receiving the potential of the intermediate node N2 and the negative reference voltage as inputs
The output of MP2 is connected to transistor M2.
The output voltage VBB is grounded via a transistor M4 having a negative voltage generation stop signal as a gate input. Furthermore,
The output voltage VBB is grounded via the smoothing capacitor CN.

The negative voltage regulator having the configuration shown in FIG. 13 compares the potential of the intermediate node N2 with the negative reference voltage and controls the transistor M2, thereby lowering the boosted positive voltage VBBIN to optimize the voltage. Output voltage VBB. The transistor M4 is turned on when a negative voltage is not required, and the VBB potential is set to 0V. At this time, the booster circuit such as the charge pump is also stopped, so that electric charge cannot be supplied, and VBBIN also becomes 0V. The smoothing capacity CN is
It is provided to alleviate a voltage drop against a sudden output load change.

Next, the operation of the conventional nonvolatile semiconductor memory device will be described. When a mode signal, an address, and a timing signal are input to the conventional nonvolatile semiconductor memory device, the mode signal, the address, and the timing signal are input to the memory management unit 4 and the mode signal is input to the power control unit 6. Is input to

Thereafter, the power control unit 6 receives the mode signal as input, controls the voltage generation unit 5 to generate a voltage required for the operation mode indicated by the mode signal, and supplies the voltage to the decoding unit 2.

The memory control unit 4 receives a mode signal, an address, and a timing signal as input, and controls the decoding unit 2 and the data detecting unit 3 based on the input mode signal, address, and timing signal.

That is, the memory control unit 4 includes the decoding unit 2
During the period specified by the timing signal, the decoding unit 2 is activated, and the voltage generation unit 5 is applied to the memory cell of the memory array 1 specified by the address.
Is applied to select a memory cell of the memory array 1.

The memory control unit 4 controls the data detecting means 3 to activate the data detecting means 3 during a period designated by a timing signal in an operation mode indicated by a mode signal for which data needs to be detected. The state of the memory cell selected by the decoding means 2 is detected and output from the output port.

Next, a data rewriting process performed by a conventional nonvolatile semiconductor memory device will be described.
Data rewriting is performed by erasing and writing data. Hereinafter, the data rewriting process will be described with reference to FIGS. 14 to 16 separately for the data erasing process and the writing process. FIG. 16 shows an example of voltage conditions in each operation mode of the nonvolatile semiconductor memory.

FIG. 14 is a flowchart for explaining an example of processing for erasing data stored in the nonvolatile semiconductor memory. The process of erasing this data is
The operation of injecting electrons into the floating gate of the memory cell to increase the threshold voltage is performed as follows.

In FIG. 14, when the nonvolatile semiconductor memory device receives the mode signal (S101) of the operation mode “erase” shown in FIG. 16 and the address of the memory to be erased, the memory controller 4 And selects the memory cell indicated by the address. Thereafter, to the selected memory cell, an erase pulse of -8 V is applied to the drain, source, and substrate controlled by the power supply control unit 6 and 8 V is applied to the gate (see FIG. 16) (S10
2) Then, electrons are injected from the source or the substrate into the floating gate to increase the threshold voltage of the memory cell.

Next, in the nonvolatile semiconductor memory device, a mode signal (S10) of the operation mode "erase verify" shown in FIG.
In response to 3), the memory control unit 4 determines in step S103
To determine the state of the erased memory cell. That is, the memory control unit 4 controls the decoding unit 2 to select the memory cell that has been erased in step S103, and applies 1 V to the drain controlled by the power supply control unit 6 and the gate to the selected memory cell. 4V, source, substrate 0V
(See FIG. 16) to detect the threshold voltage of the memory cell and compare it with a specified value (S104).

As a result of the comparison, if the threshold value of the memory cell is lower than the specified value, the erase verify fails (hereinafter referred to as "fail"), and the erase pulse is applied again to the same address. Then, an erase pulse is applied to the memory cells at the same address until the threshold value of the memory cells becomes higher than the specified value.

On the other hand, if the threshold value of the memory cell is higher than the specified value, the operation is successful (hereinafter, referred to as pass), and it is determined whether the erased address is the last address (S).
105).

If the erased address is not the last address, the address is changed to the next address, and the data in the memory cell indicated by the next address is erased.
Go to step S101 again. On the other hand, if the erased address is the last address, it is determined that all the areas have been erased, and the process ends.

FIG. 15 is a flowchart for explaining an example of a process of writing data in the nonvolatile semiconductor memory. The process of writing data to the memory is an operation of emitting electrons from the floating gate of the memory cell to lower the threshold voltage, and is performed as follows. In FIG. 15, first, the nonvolatile semiconductor memory device operates in the operation mode “data latch” shown in FIG.
Receiving the mode signal (S201) of the memory controller 4
Controls the decoding means 2 to latch data to be written (S202).

Thereafter, the non-volatile semiconductor memory device determines the mode signal (S2) of the operation mode "write verify" shown in FIG.
03), the memory control unit 4 determines the current state of the memory cell. That is, the memory control unit 4 controls the decoding unit 2, and supplies 1 V to the drain, 2 V to the gate, 2 V to the source,
The threshold voltage of the memory cell is detected by applying 0 V (see FIG. 16) to the substrate, and the threshold voltage is compared with a specified value (S20).
4).

As a result of the comparison, if the threshold value of the memory cell is higher than the specified value, the write verify fails, and the process goes to step S205. On the other hand, if the threshold value of the memory cell is lower than the specified value, a pass is made and step S2
Go to 09.

Next, in order to write data, the nonvolatile semiconductor memory device receives the mode signal (S205) of the operation mode "write" shown in FIG. For memory cells,
Drain 6 V, gate controlled by power supply control unit 6
A write pulse of 8 V, 0 V (see FIG. 16) is applied to the source and the substrate (S206). As a result, electrons are emitted from the floating gate to the drain, and the threshold voltage of the memory cell decreases.

Next, in order to determine the state of the memory cell in which the writing has been performed, the nonvolatile semiconductor memory device shown in FIG.
In response to the mode signal (S207) of the operation mode "write verify" shown in (2), the memory control unit 4 determines the state of the memory cell to which the writing has been performed in step S205. That is, the memory control unit 4 controls the decoding unit 2 and applies 1 V to the drain, 2 V to the gate, and 2 V to the source and the substrate controlled by the power supply control unit 6 for the memory cell to which the write pulse is applied in step S206. The threshold voltage of the memory cell is detected by applying 0 V (see FIG. 16) and is compared with a specified value (S208).

As a result of the comparison, if the threshold value of the memory cell is higher than the specified value, the write-verify fails, and the process goes to step S205 again until the memory at the same address becomes lower than the specified value. A write pulse is applied to the cell.

On the other hand, if the threshold value of the memory cell is lower than the specified value, the pass is made, and it is determined whether or not the address of the written data is the last address (S209). If the address of the written data is not the last address, the address is set to the next address, and the process returns to step S201 to write the data indicated by the next address. On the other hand, if the address of the written data is the last address, it is determined that all the data has been written, and the process ends.

As described above, when rewriting data for erasing and writing data, a specific positive high voltage and negative high voltage set for each operation mode are applied to the nonvolatile semiconductor memory. It is done by doing.

The "non-volatile semiconductor memory device" described in Japanese Patent Application Laid-Open No. 9-35499 is different from the conventional non-volatile semiconductor memory device described above in further including the number of re-erase loops during the erase sequence (see FIG. 14). A counter is provided for counting the number of times of failing in step S106) or the number of rewriting loops in the writing sequence (number of times of failing in step S208 of FIG. 15). Based on the count value of the counter, data erasing and There is one that sets a voltage for writing.

[0033]

Generally, rewriting of data in a nonvolatile semiconductor memory such as a flash memory is performed by hot electron injection or Fowlor-Nordheid.
This is performed using an m tunnel current (hereinafter, referred to as an FN current). However, when data is repeatedly rewritten in the nonvolatile memory, an electron trap is generated in the oxide film, which causes deterioration of injection and emission of electrons and a phenomenon in which FN current becomes difficult to flow. this is,
In particular, this remarkably appears when rewriting is performed using the FN current. Therefore, if the same tunnel voltage is applied when rewriting data in the non-volatile memory, the injection / emission of electrons is deteriorated, resulting in a problem that the rewriting time becomes longer.

FIG. 4 is a diagram showing the relationship between the time required for the data erasing / writing time and the number of times of rewriting. As shown in FIG. It can be seen that the time required for the erasing / writing time is longer.

The "non-volatile semiconductor memory device" described in Japanese Patent Application Laid-Open No. 9-35499 has a number of re-erasing loops (the number of times of fail in step S106 in FIG. 14) during an erasing sequence or a re-erasing loop during a writing sequence. Only the voltage for erasing and writing data is set based on the number of loops of writing (the number of times of fail in step S208 in FIG. 15). The same problem as described above, such as deterioration of injection / emission and prolonged rewriting time, is also encountered.

For example, when a nonvolatile semiconductor memory is used as the main memory for programming, most of the operation modes for the memory are in the read mode. In this read mode, as shown in FIG. 16, since only the positive voltage is used, the negative voltage regulator for generating the negative voltage of the voltage generating means 5 which is not necessary for reading to reduce the power consumption is stopped. Further, when the operation mode is the stop mode, no voltage application is required, so that the operation of the power supply generation unit 5 is completely stopped to reduce power consumption.

On the other hand, as shown in FIG. 14 and FIG. 15, when the operation mode is erasing or writing, the operation mode continuously transitions, so that the positive voltage regulator of the voltage generating means 5 and the The negative voltage regulator is operating.

Therefore, for example, when an operation such as erasing or writing shown in FIG. 14 or FIG. 15 is performed to change the operation mode, the mode signal input to the conventional nonvolatile semiconductor memory device includes: Since there is no particular restriction, there is a possibility that operation modes such as stopping the voltage generation unit 5, reading, and stopping may be set transiently due to a signal skew. In such a case, The voltage generated by the voltage generating means 5 is discharged, and the electric charge stored in the smoothing capacitor is released. Therefore, even after the desired operation mode is set, there is a problem that the power consumption is deteriorated because the voltage needs to be boosted again.

The present invention solves these problems.
It is an object of the present invention to provide a nonvolatile semiconductor memory device capable of realizing high-speed data rewriting operation and low power consumption of the nonvolatile semiconductor memory.

[0040]

According to a first aspect of the present invention, there is provided a nonvolatile semiconductor memory device in which memory cells are arranged in a grid pattern in a row direction and a column direction. An array, a decoding unit for selecting a memory cell of the memory array by applying a voltage, a data detection unit for detecting and outputting a state of the memory cell selected by the decoding unit, the decoding unit, A memory control unit for controlling data detection means; a voltage generation means for generating and supplying different voltages to the decoding means for each operation mode; a power supply control unit for controlling the voltage generation means; And a counter for counting the number of times of rewriting of the data. It is intended to vary the voltage.

According to a second aspect of the present invention, there is provided a nonvolatile semiconductor memory device comprising: a memory array in which memory cells are arranged in a grid in a row direction and a column direction; A data detecting means for detecting and outputting the state of the memory cell selected by the decoding means, a memory control unit for controlling the decoding means and the data detecting means, A decoding unit configured to generate and supply a different voltage for each operation; a power supply control unit that controls the voltage generation unit; and a counter that counts the number of times data in the memory array is rewritten. The control unit controls the timing of the data rewriting timing signal output to the decoding unit based on the count value of the counter. It is intended to change the scan width.

According to a third aspect of the present invention, in the non-volatile semiconductor memory device according to the second aspect, further, the power supply control unit further comprises a power supply control unit which controls the power supply based on a count value of the counter. , For changing the voltage output from the voltage generating means.

According to a fourth aspect of the present invention, in the non-volatile semiconductor memory device according to any one of the first to third aspects, the counter receives a count value from outside. It has an external input port for inputting.

According to a fifth aspect of the present invention, in the non-volatile semiconductor memory device according to any one of the first to fourth aspects, the counter externally outputs a count value. It has an external output port for outputting.

According to a sixth aspect of the present invention, in the nonvolatile semiconductor memory device according to any one of the first to fifth aspects, the memory array includes a plurality of regions. And using at least one of the plurality of areas as a count value storage area for storing a count value of the counter.

According to a seventh aspect of the present invention, in the nonvolatile semiconductor memory device according to the sixth aspect of the present invention, the data detecting means is configured to store data in the count value storage area after power-on. Is detected, and the detected data is stored in the counter.

According to a eighth aspect of the present invention, in the nonvolatile semiconductor memory device according to any one of the first to seventh aspects, the counter counts the number of erases. An erase counter,
The memory control unit and the power supply control unit perform erasing and writing based on the count value of the erasing counter and the count value of the writing counter, respectively. Each is controlled independently.

According to a ninth aspect of the present invention, there is provided the nonvolatile semiconductor memory device according to any one of the first to eighth aspects, wherein the counter is at least the memory array. The memory control unit and the power supply control unit perform control based on a count value of a counter provided for each of the erase units.

According to a tenth aspect of the present invention, there is provided the nonvolatile semiconductor memory device according to any one of the first to eighth aspects, wherein the counter includes at least the memory array. The memory control unit and the power supply control unit perform control based on a count value of a counter provided for each of the write units.

The nonvolatile semiconductor memory device according to claim 11 of the present invention is the nonvolatile semiconductor memory device according to any one of claims 1 to 8, wherein the counter is at least the memory array. Provided for each erase unit and write unit of the memory cell constituting
The memory control unit and the power supply control unit perform control based on a count value of a counter provided for each of the erase unit and the write unit.

According to a twelfth aspect of the present invention, in the non-volatile semiconductor memory device according to any one of the first to eleventh aspects, the memory control unit includes a counter of the counter. When the count value becomes equal to or more than a preset value, control is performed so that data cannot be rewritten.

The nonvolatile semiconductor memory device according to a thirteenth aspect of the present invention is the nonvolatile semiconductor memory device according to any one of the first to twelfth aspects, wherein the memory control unit comprises: A set value excess signal for notifying the outside that the count value has become greater than or less than a preset value is output to the outside of the apparatus.

According to a fourteenth aspect of the present invention, there is provided a nonvolatile semiconductor memory device comprising: a memory array having at least memory cells arranged in a grid in a row direction and a column direction; A decoding means for selecting, and a data detecting means for detecting and outputting the state of the memory cell selected by the decoding means, and in an erase sequence in which an operation mode continuously changes,
This is to minimize the hamming distance between mode signals indicating adjacent operation modes before and after the transition.

According to a fifteenth aspect of the present invention, there is provided a nonvolatile semiconductor memory device comprising: a memory array having at least memory cells arranged in a grid in a row direction and a column direction; A decoding means for selecting, and a data detecting means for detecting and outputting the state of the memory cell selected by the decoding means, and in a write sequence in which the operation modes continuously transition, the adjacent operation modes before and after the transition are changed. The hamming distance between the notified mode signals is minimized.

[0055]

Embodiments of the present invention will be described below with reference to the drawings. (Embodiment 1) FIG. 1 is a block diagram for describing a nonvolatile semiconductor memory device according to Embodiment 1 of the present invention. In FIG. 1, the nonvolatile semiconductor memory device includes a memory array 1, a decoding unit 2, a data detection unit 3, a memory control unit 11, and a voltage generation unit 12.
, A power control unit 13, a counter 14, and a selector 15
Consists of

In the nonvolatile semiconductor memory device according to the first embodiment of the present invention, the same components as those of the conventional nonvolatile semiconductor memory device described with reference to FIG. .

The memory control unit 11 reads data,
Decoding means 2, based on a mode signal which is a signal indicating an operation mode such as erasing or writing, an address designating a memory cell, and a timing signal notifying a timing of executing the operation mode indicated by the mode signal.
In addition to controlling the data detection means 3 and the counter 14, it outputs a set value excess signal indicating that the counter value of the counter 14 has reached a predetermined value to the outside of the nonvolatile semiconductor memory device.

The counter 14 is controlled by the memory control unit 11 and counts the number of times data has been rewritten. The selector 15 is controlled by the memory control unit 11, outputs a count value input from outside the nonvolatile semiconductor memory device to the counter 14,
Output to the outside of the nonvolatile semiconductor memory device.

The power controller 13 controls the voltage generator 12 based on the mode signal and the count value output from the counter 14. The voltage generation unit 12 is controlled by the power supply control unit 13, generates a voltage having a predetermined value, and supplies the generated voltage to the decoding unit 2.

Next, the configuration of the voltage generating means 12 will be described. FIG. 2 is a diagram illustrating an example of a positive voltage regulator that forms the voltage generation unit 12, and FIG. 3 is a diagram illustrating an example of a negative voltage regulator that forms the voltage generation unit 12. FIGS. 2 and 3 showing the configuration of the voltage generating means 15 include a resistor R1 (FIG. 2) and a resistor R3 (FIG. 3).
Is a variable resistor, the resistor R1 is controlled by a positive voltage adjustment signal, and the resistor R3 is controlled by a negative voltage adjustment signal, which is different from the conventional voltage generating means 5 described with reference to FIGS. Here, the description is omitted.

Further, in the case of the positive voltage regulator shown in FIG. 2, the output voltage VPP is increased by increasing the resistance value of the resistor R1, and the output voltage VPP is increased. This is performed by lowering the resistance value to lower the voltage VPP. On the other hand, in the case of the negative voltage regulator shown in FIG. 3, the output voltage VBB decreases by increasing the resistance R3, and the output voltage VBB decreases by decreasing the resistance R3.

Next, the operation of the nonvolatile semiconductor memory device of the present invention will be described. Embodiment 1 of the present invention
In the operation of the non-volatile semiconductor memory device according to the above, the description of the same parts as the above-mentioned conventional non-volatile semiconductor memory device is omitted, and only the differences will be described here. When a mode signal, an address, and a timing signal are input to the conventional nonvolatile semiconductor memory device, the mode signal, the address, and the timing signal are input to the memory control unit 11 and the mode signal is input to the power control unit 13. Is input to

First, the memory control unit 11
4 and the selector 15, and a count value representing the current number of rewrites is input from the input / output port of the selector 15 and stored in the counter 14. Also, the memory control unit 11
Thereafter, every time data is rewritten, the count value of the counter 14 is incremented.

By inputting the count value through the external input port for inputting the count value from the outside in this way, the count value of the counter 14 can be set to an initial value at the time of inspection, or the state at the time of inspection. Can be used to set the initial value to different data other than 0, and by setting the count value of the counter 14 to an arbitrary value, it is possible to adjust a voltage change point described later. .

Next, based on the mode signal and the count value of the counter 14, the power control unit 13 boosts and generates a voltage necessary for the operation mode indicated by the mode signal, and supplies the generated voltage to the decoding means 2. To control the voltage generating means 5.

FIG. 4 is a diagram showing the dependence of the erase / write time on the number of rewrites. As shown in FIG. 4, when the number of rewrites exceeds 1,000, the rewrite time increases. Therefore, the power supply control unit 13
After that, the voltage generated by the voltage generation means 12 is controlled so that the tunnel voltage is increased stepwise (amplitude modulation).

That is, the power control unit 13 controls the voltage generation unit 1
2 is controlled, for example, as shown in FIG. 5, the operation mode is set to 8V until the 999th time when there is not much change in the erasing time as in the example of the word line voltage output from the voltage generating means 12 at the time of erasing. The tunnel voltage is applied stepwise so that the decoding means 2 controlled by the memory control unit 11 applies a voltage of 8.2 V from 1000 times to 9999 times when the deterioration starts, and a voltage of 8.4 V from 10,000 times or more after the deterioration. To increase.

As described above, the number of rewrites is counted by the counter 14.
By controlling the voltage applied to the memory cell based on the number of times of data rewriting, the deterioration of the erasing time and the writing time due to repetition of the rewriting can be prevented, and the rewriting time can be averaged. .

In the above-described example of the control of the voltage generating means 12 by the power supply control unit 13, the description has been given of the case where the word line voltage, that is, the voltage applied to the gate is changed. However, the present invention is not limited to this. The same effect can be obtained as long as the tunnel voltage is increased by partially or entirely changing the potentials of the source, the substrate, and the substrate.

In FIG. 5, the voltage applied to the gate is changed in three stages, but may be changed in two stages or in a plurality of stages of four or more stages. On the other hand, the memory control unit 11 receives a mode signal, an address, and a timing signal as input, and controls the decoding unit 2 and the data detection unit 3 based on the input mode signal, address, and timing signal.

That is, the memory control unit 11 controls the decoding means 2 so that during the period specified by the timing signal,
The decoding unit 2 is activated, and the voltage output from the voltage generation unit 12 is applied to the memory cell of the memory array 1 specified by the address output from the control signal, and the memory cell of the memory array 1 is selected. I do. If the operation performed by the memory control unit 11 at this time is a data rewriting operation for erasing and writing data, the count value of the counter 14 is incremented after the rewriting is completed.

The memory control section 11 controls the data detecting means 3 to activate the data detecting means 3 during a period designated by the timing signal in an operation mode indicated by a mode signal for which data needs to be detected. The state of the memory cell selected by the decoding means 2 is detected and output.

Further, the memory control unit 11
When incrementing the count value of 4, the incremented count value is compared with a preset predetermined value, and when the count value exceeds a preset predetermined value, the count value has exceeded the predetermined value. Is output outside the nonvolatile semiconductor memory device.

For example, the upper limit number of rewrites guaranteed by the nonvolatile semiconductor memory is set to the predetermined value (here, 1
When the count value of the counter 14 reaches 10000 times by repeating rewriting, the memory control unit 11 determines that the upper limit number of times of rewriting of the nonvolatile semiconductor memory has been reached. To generate a set value excess signal, and output the signal from the input / output port to the outside of the device via the selector 15. This makes it possible to detect from the outside that the number of times of rewriting of the nonvolatile semiconductor memory has reached the upper limit number of times. For example, it is possible to perform processing such as prohibiting subsequent rewriting.

Here, the case where the predetermined value set in advance is the upper limit number of times of rewriting has been described.
It is also possible to freely set a numerical value of a node such as 0 or 1000. In addition, the predetermined value to be set in advance is not necessarily one, and a plurality of values can be set. In this case, it is necessary to externally monitor that the set value has been reached. Can be.

In the above description, the memory controller 11 outputs a set value excess signal when the count value of the counter 14 exceeds a predetermined value.
The memory control unit 11 may decrement the count value of the counter 14 and output a set value excess signal when the count value of the counter 14 becomes equal to or less than a predetermined value set in advance.

In the nonvolatile semiconductor memory device according to the first embodiment of the present invention, the memory control unit 11 outputs a set value excess signal to the outside of the device when the value of the counter 14 reaches a predetermined value. However, for example, when the memory control unit 11 determines that the count value of the counter 14 has reached a predetermined value, the memory control unit 11 does not accept an input of a mode signal related to subsequent rewriting, Control may be performed inside the device so that data cannot be rewritten.

Further, the memory control section 11
4 and the selector 15, and the count value held by the counter 14 can be output to the outside of the device from the count value input / output port connected to the selector 15.
As a result, the current number of rewrites can be monitored outside the device, and the state of the memory array 1 can be grasped from outside.

(Second Embodiment) A nonvolatile semiconductor memory device according to a second embodiment of the present invention will be described below. FIG. 6 is a block diagram for describing a nonvolatile semiconductor memory device according to a second embodiment of the present invention. In FIG. 6, a nonvolatile semiconductor memory device includes a memory array 1, a decoding unit 2, and a data detection unit 3.
, A memory controller 21, a voltage generator 12, a power controller 13, a counter 14, and a selector 15.

The nonvolatile semiconductor memory device according to the second embodiment of the present invention is different from the above-described embodiment in that the memory control unit 21 changes the pulse width of the timing signal based on the count value of the counter 14. 1 is different from the nonvolatile semiconductor memory device of FIG. The same components as those of the nonvolatile semiconductor memory device according to the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

The memory control unit 21 of the nonvolatile semiconductor memory device according to the second embodiment of the present invention includes: a mode signal indicating operation modes such as data reading, erasing, and writing; an address specifying a memory cell; The pulse width of the timing signal for operating the decoding means 2 is changed based on the count signal output from the counter 14 and the timing signal for notifying the timing of executing the operation mode indicated by the mode signal. And outputs it to the decoding means 2.

For example, as shown in FIG. 4, when the number of times of rewriting exceeds 1,000, the rewriting time increases.
Control is performed so that the pulse width of the timing signal that determines the period during which the rewrite voltage is applied after 000 times is increased stepwise (pulse width modulation).

FIG. 7 shows an example of a timing signal output from the memory control unit 21 when data is erased. For example, as shown in FIG. 7, the memory control unit 21 has a pulse width of 50 μs until the 999th time when the erasing time does not change much, and 100 μs from the 1000th to the 9999th time when deterioration starts
Of pulse width, 200 for more than 10,000 times
By outputting a timing signal having a pulse width of μs, the erasing time for one pulse is gradually increased.

In other words, when the entire erase time is the same, the number of times of erasing the erase-erase verify cycle can be reduced, so that the overhead such as the erase verify time and the setup time due to the mode transition is reduced.

As described above, the number of rewrites is counted by the counter 14.
By controlling the pulse width of the timing signal based on the number of times of data rewriting, it is possible to prevent the erasing time and the writing time from deteriorating due to repeated rewriting and to average the rewriting time.

(Embodiment 3) Hereinafter, a nonvolatile semiconductor memory device according to Embodiment 3 of the present invention will be described. FIG. 8 is a block diagram for describing a nonvolatile semiconductor memory device according to a third embodiment of the present invention. 8, a nonvolatile semiconductor memory device includes a memory array 1, a decoding unit 2, and a data detecting unit 3.
, A memory controller 21, a voltage generator 12, a power controller 13, a counter 31, and a selector 15.

The nonvolatile semiconductor memory device according to the third embodiment of the present invention includes an erase counter 31a for counting the erase count by counter 31 and a write counter 31b for counting the write count. , And the power supply control unit 13 are configured to
Erase and write are independently controlled based on the count value of a and the count value of the write counter 31b. The same components as those of the nonvolatile semiconductor memory device according to the above-described second embodiment are denoted by the same reference numerals, and description thereof will be omitted.

The counter 31 is capable of independently counting the number of times of erasing and the number of times of writing, respectively.
And a write counter 31b.

Therefore, when erasing data, power supply control unit 13 controls the voltage output from voltage generation means 12 based on the erase count value stored in erase counter 31a, or Control unit 2
1 controls the pulse width of the pulse signal output to the decoding means 2 based on the erase count value stored in the erase counter 31a.

When the data erasure is completed, the memory control section 21 controls the erasure counter 31a and increments the count value of the erasure counter 31a.

On the other hand, in the case of writing data, similarly, the power supply control unit 13 sets the write number counter 31b.
The memory control unit 21 controls the voltage output from the voltage generation unit 12 based on the write count value stored in the memory unit 21 or outputs the voltage to the decoding unit 2 based on the write count value stored in the write number counter 31b. The pulse width of the pulse signal to be controlled is controlled.

When the data writing is completed, the memory control unit 21 controls the writing number counter 31b and increments the count value of the writing number counter 31b.

As described above, by independently managing the number of times of data erasing and the number of times of writing, the number of times of erasing and the number of times of writing are reduced due to the fact that only data erasing is performed and writing is not performed. Even in the case where is different from each other, since the number of times of erasing and the number of times of writing can be accurately grasped, optimal control by the power supply control unit and the memory control unit can be independently performed in erasing and writing.

Further, in the nonvolatile semiconductor memory device according to the third embodiment of the present invention, a description has been given of a device in which either the voltage control by power supply control unit 13 or the control of the pulse width by memory control unit 21 is performed. Both controls may be performed simultaneously, and the same effect can be obtained.

(Embodiment 4) A nonvolatile semiconductor memory device according to Embodiment 4 of the present invention will be described below. FIG. 9 is a block diagram for describing a nonvolatile semiconductor memory device according to a fourth embodiment of the present invention. In FIG. 9, a nonvolatile semiconductor memory device includes a memory array 1, a decoding unit 2, and a data detection unit 3.
, A memory control unit 21, a voltage generation unit 12, a power supply control unit 13, a counter 41, and a selector 15.

In the nonvolatile semiconductor memory device according to the fourth embodiment of the present invention, the counter 41 is set for each erase unit of a memory cell where data is erased or for each write unit of a memory cell where data is erased. Things. The same components as those of the nonvolatile semiconductor memory device according to the above-described second embodiment are denoted by the same reference numerals, and description thereof will be omitted.

The counter 41 is provided with a plurality of counters for each erase unit of a memory cell that can be erased at a time and for each write unit of a memory cell that can be written at a time. Counting can be performed for each unit and for each writing unit.

Next, the operation will be described. When erasing data, the power control unit 13 sends a mode signal,
First, the power control unit 13 detects a mode signal and a counter corresponding to the erase unit specified by the address from the counter 41, and based on the count value of the counter, Control the output voltage.

Further, instead of controlling the voltage as described above, the memory control unit 21 detects the counter corresponding to the input mode signal and the erase unit specified by the address, and determines the count value of the counter. Based on this, the pulse width of the pulse signal output to the decoding means 2 may be controlled.

When the data erasure is completed, the memory controller 21 increments the count value of the counter corresponding to the erasure unit specified by the address. On the other hand, when writing data, similarly, a mode signal and an address are input to the power supply control unit 13, and first, the power supply control unit 13 writes the data specified by the mode signal and the address from the counter 41. A counter corresponding to the unit is detected, and the voltage output from the voltage generating means 12 is controlled based on the count value of the counter.

Also, here, instead of controlling the voltage as described above, the memory control unit 21 detects the input mode signal and the counter corresponding to the write unit specified by the address, and counts the counter. The pulse width of the pulse signal output to the decoding means 2 may be controlled based on the value. When the data writing is completed, the memory control unit 21 increments the count value of the counter corresponding to the writing unit specified by the address.

As described above, by providing a counter for each erase unit that can be erased at a time or for each write unit that can be written at a time, the number of erases and the number of writes differ for each erase unit and each write unit. Even in this case, since the number of times of erasing and the number of times of writing can be accurately grasped, optimal control by the power supply control unit and the memory control unit can be performed for each erasing unit and each writing unit. .

Here, the case where a counter is provided for each erasing unit that can be erased at a time and for each writing unit that can be written at a time has been described. However, the present invention is not limited to this. It is also possible to arrange one counter or one counter for a plurality of write unit blocks.
Similar effects can be obtained.

In the non-volatile semiconductor memory device according to the fourth embodiment of the present invention, description has been made of a device which performs either voltage control by power supply control unit 13 or control of pulse width by memory control unit 21. Both controls may be performed simultaneously, and the same effect can be obtained.

(Fifth Embodiment) Hereinafter, a nonvolatile semiconductor memory device according to a fifth embodiment of the present invention will be described. FIG. 10 is a block diagram illustrating a nonvolatile semiconductor memory device according to a fifth embodiment of the present invention. 10, a nonvolatile semiconductor memory device includes a memory array 51, a decoding unit 2, a data detection unit 3, a memory control unit 21, a voltage generation unit 12, a power supply control unit 13, a counter 14, a selector 15

In the nonvolatile semiconductor memory device according to the fifth embodiment of the present invention, the memory array 51 is divided into a first memory array 51a and a second memory array 51b. , The second memory array 51b is used as a count value storage area for storing the count value held by the counter 14. The same components as those of the nonvolatile semiconductor memory device according to the above-described second embodiment are denoted by the same reference numerals, and description thereof will be omitted. The memory array 51 includes a first memory array 51 a and a second memory array 5.
1b.

Next, the operation will be described. The memory control unit 21 controls the decoding unit 2 when the power of the device is turned off, and stores the count value of the counter 14 in the second memory cell array 51b used as a count value storage area. After the power is turned on, first, the memory control unit 21
Controls the data detection means 3 and controls the second memory array 5
The count value stored in 1b is detected and output to the counter 14.

The counter 14 stores the count value output from the data detecting means 3. Accordingly, when the power is turned off when the counter 14 is a volatile register, the count value of the counter 14 is lost. However, the count value is separately stored in the memory array 51 which is a nonvolatile memory. Even when the power is turned off, the count value does not disappear, and after the power is turned on, the count value stored in the memory array 51 is read, so that the count value of the counter 14 can be reset. .

In the memory array 51 of the nonvolatile semiconductor memory device according to the fifth embodiment, the memory array 5
1 is divided into two, but the present invention is not limited to this. The memory array 51 is divided into a plurality of areas, and at least one of the plurality of areas has a counter 1
A similar effect can be obtained as long as the count value of 4 is stored.

In the nonvolatile semiconductor memory device according to the fifth embodiment, the case where the count value of the counter 14 is stored in the second memory array 51b when the power is turned off has been described, but every time data is rewritten. Alternatively, the count value of the counter 14 may be stored in the second memory array 51b, and the same effect can be obtained.

(Embodiment 6) A nonvolatile semiconductor memory device according to Embodiment 6 of the present invention will be described below. In the nonvolatile semiconductor memory device according to the sixth embodiment of the present invention, the input mode signal is such that the hamming distance between adjacent modes before and after transition in an erase sequence or a write sequence is one.

For example, when operating in the erase sequence shown in FIG. 14, erasure and erase verify are repeatedly performed. At this time, since the Hamming distance between adjacent modes before and after the transition is always set to 1 in the mode signal input to the nonvolatile semiconductor memory device, for example, the erasing mode signal is “010” as shown in FIG. The erase verify mode signal is set to “011”. As a result, since the two mode signals have a Hamming distance of 1, even if the operation is repeated, the mode signal changes only by one bit of the LSB. The other operation modes are not set transiently, and it is possible to prevent the charge stored in the smoothing capacitor from being released by boosting.

Similarly, for example, when operating in the write sequence shown in FIG.
Write and write verify are repeated. At this time, since the mode signal input to the nonvolatile semiconductor memory device always sets the Hamming distance between adjacent modes before and after the transition to 1, for example, the write mode signal is “100” as shown in FIG. , The write verify mode signal is “101”, and the data latch mode signal is “1”.
As a result, as shown in FIG. 15, since the write verify is performed before and after the transition for both the data latch and the write, the hamming distance of the mode signal of each transition mode is 1. During the write, write-verify, and data-latch sequences, other operation modes, such as stop, are not set transiently, and the charge accumulated in the smoothing capacitor is not released. In addition, the power consumption can be prevented from deteriorating.

[0114]

As described above, according to the nonvolatile semiconductor memory device of the first aspect of the present invention, the memory array in which the memory cells are arranged in a grid in the row direction and the column direction, and the memory Decoding means for selecting a memory cell of the array by applying a voltage, data detection means for detecting and outputting the state of the memory cell selected by the decoding means, and controlling the decoding means and the data detection means A memory control unit that generates and supplies different voltages to the decoding unit for each operation mode, a power supply control unit that controls the voltage generation unit, and counts the number of times data in the memory array is rewritten. The power supply control unit changes a voltage output from the voltage generation unit based on a count value of the counter. By controlling as to prevent rewriting time degradation due to repeated rewriting, thereby averaging the rewrite time.

Further, according to the nonvolatile semiconductor memory device of the second aspect of the present invention, a memory array in which memory cells are arranged in a grid in the row direction and the column direction, and a memory cell of the memory array Decoding means for selecting by applying a voltage, data detecting means for detecting and outputting the state of the memory cell selected by the decoding means, and a memory control unit for controlling the decoding means and the data detecting means. A voltage generating means for generating and supplying different voltages to the decoding means for each operation mode;
A power control unit that controls the voltage generation unit; and a counter that counts the number of times data in the memory array is rewritten. The memory control unit outputs data to the decoding unit based on a count value of the counter. By controlling to change the pulse width of the rewriting timing signal, overheads such as erase verify time, write verify time, and setup time due to mode transition are reduced, and deterioration of the rewrite time due to repeated rewriting is prevented. , The erasing time can be averaged.

According to the nonvolatile semiconductor memory device of the third aspect of the present invention, in the nonvolatile semiconductor memory device of the second aspect, the power supply control unit may further include a counter value of the counter. By controlling the voltage output from the voltage generation means to change based on this, it is possible to prevent the rewriting time from deteriorating due to repeated rewriting and average the rewriting time.

According to a fourth aspect of the present invention, in the non-volatile semiconductor memory device according to any one of the first to third aspects, the counter is configured to count externally. By providing an external input port for inputting a value, the count value of the counter can be
The initial value can be set at the time of inspection, the initial value can be set to different data other than 0 depending on the state at the time of inspection, and the voltage can be set by setting the count value of the counter to an arbitrary value. Can also be adjusted.

According to the nonvolatile semiconductor memory device of the present invention, in the nonvolatile semiconductor memory device according to any one of the first to fourth aspects, the counter counts to the outside. By providing an external output port for outputting a value, the current number of times of rewriting can be monitored externally, and the state of the flash memory can be grasped.

Further, according to the nonvolatile semiconductor memory device according to claim 6 of the present invention, claim 1 to claim 5
The nonvolatile semiconductor memory device according to any one of the above,
The memory array has a plurality of areas, and at least one of the plurality of areas is used as a count value storage area that stores a count value of the counter.
If the counter is a volatile register, turning off the power causes the counter value to be lost, but the power is turned off because the counter value is stored in the non-volatile memory array. Even in the case where the error occurs, the count value of the counter does not disappear.

According to a seventh aspect of the present invention, in the nonvolatile semiconductor memory device according to the sixth aspect, the data detecting means is configured to control the count value storage area after power is turned on. Detect data for
By storing the detected data in the counter, when the counter is a volatile register, when the power is turned off, the count value of the counter is lost,
The count value of the counter can be reset by reading the count value from the memory array which is a nonvolatile memory in which the count value of the counter is stored.

Further, according to the nonvolatile semiconductor memory device according to the eighth aspect of the present invention, the first to seventh aspects are as follows.
The nonvolatile semiconductor memory device according to any one of the above,
The counter includes an erase counter for counting the number of erases, and a write counter for counting the number of writes. The memory control unit and the power supply control unit are configured to count the erase counter, By independently controlling erasing and writing based on each count value of the counter, even if the number of erasing and writing of data is different, the number of erasing and writing can be accurately grasped. Therefore, it is possible to perform optimal control by the power supply control unit and the memory control unit while independently erasing and writing data.

According to the nonvolatile semiconductor memory device of the ninth aspect of the present invention, in the nonvolatile semiconductor memory device according to any one of the first to eighth aspects, at least the counter comprises The memory control unit and the power supply control unit are provided for each erase unit of a memory cell included in a memory array, and the memory control unit and the power supply control unit perform control based on a count value of a counter provided for each of the erase units, so that Even if the number of erasures for each unit is different, the number of erasures for each erasure unit can be accurately grasped, so that optimal control by the power supply control unit and the memory control unit is performed for each erasure unit. It can be carried out.

According to the nonvolatile semiconductor memory device of the present invention, there is provided a nonvolatile semiconductor memory device comprising:
The nonvolatile semiconductor memory device according to any one of the above,
The counter is provided at least for each write unit of a memory cell constituting the memory array, and the memory control unit and the power supply control unit control based on a count value of a counter provided for each write unit. By performing the above, even if the number of times of writing for each writing unit is different, the number of times of writing for each writing unit can be accurately grasped. Optimal control by the control unit can be performed.

According to the nonvolatile memory device of the present invention, in the nonvolatile semiconductor memory device according to any one of claims 1 to 8, the counter is provided at least in the memory. Provided for each erase unit and write unit of the memory cells constituting the array,
The memory control unit and the power supply control unit perform control based on the count value of a counter provided for each of the erase unit and the write unit, so that the number of times of writing for each erase unit and each write unit is different. Even in such a case, since the number of erases and the number of writes for each erase unit and each write unit can be accurately grasped, the power control unit and the memory control unit for each erase unit and each write unit Optimal control can be performed.

According to the nonvolatile semiconductor memory device of the present invention, there is provided a nonvolatile semiconductor memory device comprising:
2. The nonvolatile semiconductor memory device according to claim 1, wherein the memory control unit performs control so that data cannot be rewritten when the count value of the counter is equal to or greater than a preset value. Thus, for example, when the upper limit number of rewrites guaranteed by the nonvolatile semiconductor memory is set to the predetermined value, it is possible to prevent the rewrite from being performed beyond the upper limit number of rewrites of the nonvolatile semiconductor memory.

According to a nonvolatile semiconductor memory device of the present invention, there is provided a nonvolatile semiconductor memory device comprising:
3. In the nonvolatile semiconductor memory device according to any one of the items 2, the memory control unit sends to the outside of the device a set value excess signal notifying to the outside that the count value of the counter has reached or exceeded a preset value. By outputting, for example, when the upper limit number of rewrites guaranteed by the nonvolatile semiconductor memory is set to the predetermined value, it is possible to detect from the outside that the upper limit number of rewrites of the nonvolatile semiconductor memory has been reached.

According to a nonvolatile semiconductor memory device of the present invention, at least a memory array in which memory cells are arranged in a grid pattern in a row direction and a column direction, and a memory of the memory array. A decoding means for selecting a cell; and a data detecting means for detecting and outputting a state of the memory cell selected by the decoding means, and adjacent operations before and after the transition in an erase sequence in which the operation mode continuously transitions. By minimizing the Hamming distance between the mode signals that inform the mode, the charge that has been boosted and accumulated in the smoothing capacitor will not be set transiently to another mode such as stop during the erase sequence. And no deterioration of power consumption can be prevented.

According to the nonvolatile semiconductor memory device of the present invention, at least a memory array in which memory cells are arranged in a grid pattern in a row direction and a column direction, and a memory of the memory array. A decoding means for selecting a cell; and a data detection means for detecting and outputting the state of the memory cell selected by the decoding means, and in a write sequence in which the operation mode continuously transitions, adjacent operations before and after the transition. By minimizing the Hamming distance between the mode signals that inform the mode, during the write sequence, other modes such as stop were not set transiently, but were boosted and accumulated in the smoothing capacitor. It is possible to prevent the power consumption from deteriorating without discharging electric charges.

[Brief description of the drawings]

FIG. 1 is a block diagram for describing a nonvolatile semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing an example of a positive voltage regulator constituting a voltage generating means of the present invention.

FIG. 3 is a diagram showing an example of a negative voltage regulator that constitutes the voltage generation means of the present invention.

FIG. 4 is a diagram showing the dependence of the erase / write time on the number of rewrites.

FIG. 5 is a diagram illustrating an example of a word line voltage output from a voltage generation unit.

FIG. 6 is a block diagram for describing a nonvolatile semiconductor memory device according to a second embodiment of the present invention.

FIG. 7 is a diagram illustrating an example of a timing signal output from a memory control unit.

FIG. 8 is a block diagram for describing a nonvolatile semiconductor memory device according to a third embodiment of the present invention.

FIG. 9 is a block diagram for describing a nonvolatile semiconductor memory device according to a fourth embodiment of the present invention.

FIG. 10 is a block diagram illustrating a nonvolatile semiconductor memory device according to a fifth embodiment of the present invention.

FIG. 11 is a block diagram for explaining a conventional nonvolatile semiconductor memory device.

FIG. 12 is a diagram showing an example of a positive voltage regulator constituting a conventional voltage generating means.

FIG. 13 is a diagram showing an example of a negative voltage regulator constituting a conventional voltage generating means.

FIG. 14 is a flowchart illustrating an example of a process of erasing data stored in a nonvolatile semiconductor memory.

FIG. 15 is a flowchart illustrating an example of a process of writing data to a nonvolatile semiconductor memory.

FIG. 16 is a diagram showing an example of voltage conditions in each operation mode of the nonvolatile semiconductor memory.

FIG. 17 is a diagram showing the correspondence between operation modes and mode signals.

[Explanation of symbols]

 1, 51 memory array 2 decoding means 3 data detection means 4, 11, 21 memory control unit 5, 12, voltage generation means 6, 13 power supply control unit 14, 31, 41 counter 15 selector AMP1, AMP2 operational amplifier R1, R2, R3, R4 Variable resistor CP, CN Smoothing capacitance M1, M2, M3, M4 Transistor

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G11C 17/00 612Z 636A 636B (72) Inventor Ikuo Fuchigami 1006 Odakadoma, Kadoma City, Osaka Matsushita Electric Industrial Co., Ltd. (72) Inventor Tomio Kimura 1006 Kadoma, Kazuma, Osaka Pref. Matsushita Electric Industrial Co., Ltd. (72) Inventor Ken Kawai 1006 Odama, Kadoma, Kadoma, Osaka Matsushita Electric Industrial Co., Ltd.F-term (reference) 5B025 AA03 AB01 AC01 AD02 AD04 AD08 AD09 AD15 AE05 AE06

Claims (15)

[Claims] 1. A memory array in which memory cells are arranged in a grid pattern in a row direction and a column direction; decoding means for selecting a memory cell of the memory array by applying a voltage; and selecting by the decoding means. Data detecting means for detecting and outputting the state of the selected memory cell, a memory control unit for controlling the decoding means and the data detecting means, and generating and supplying different voltages to the decoding means for each operation mode A voltage generation unit; a power supply control unit that controls the voltage generation unit; and a counter that counts the number of times data is rewritten in the memory array. A non-volatile semiconductor memory device, wherein a voltage output from a generation unit is changed. 2. A memory array in which memory cells are arranged in a grid pattern in a row direction and a column direction; decoding means for selecting a memory cell of the memory array by applying a voltage; and selecting by the decoding means. Data detecting means for detecting and outputting the state of the selected memory cell, a memory control unit for controlling the decoding means and the data detecting means, and generating and supplying different voltages to the decoding means for each operation mode A voltage generation unit; a power supply control unit that controls the voltage generation unit; and a counter that counts the number of times data is rewritten in the memory array. The memory control unit performs the decoding based on a count value of the counter. A pulse width of a data rewriting timing signal to be output to the means. Body memory device. 3. The non-volatile semiconductor memory device according to claim 2, wherein said power supply control section changes a voltage output from said voltage generation means based on a count value of said counter. Nonvolatile semiconductor memory device. 4. The nonvolatile semiconductor memory device according to claim 1, wherein said counter includes an external input port for inputting a count value from outside. Memory device. 5. The nonvolatile semiconductor memory device according to claim 1, wherein said counter includes an external output port for outputting a count value to an external device. Memory device. 6. The nonvolatile semiconductor memory device according to claim 1, wherein said memory array has a plurality of regions, and at least one of said plurality of regions is provided with said counter. A non-volatile semiconductor memory device, which is used as a count value storage area for storing the count value. 7. The nonvolatile semiconductor memory device according to claim 6, wherein said data detecting means detects data in said count value storage area after power-on, and stores the detected data in said counter. A nonvolatile semiconductor memory device characterized by the above-mentioned. 8. The nonvolatile semiconductor memory device according to claim 1, wherein said counter includes an erase counter for counting the number of erases, and a write counter for counting the number of write operations. The memory control unit and the power supply control unit independently control erasing and writing based on the count value of the erase counter and the count value of the write counter, respectively. Non-volatile semiconductor memory device. 9. The nonvolatile semiconductor memory device according to claim 1, wherein said counter is provided at least for each erase unit of a memory cell constituting said memory array. And a power supply control unit that performs control based on a count value of a counter provided for each of the erase units. 10. The nonvolatile semiconductor memory device according to claim 1, wherein said counter is provided at least for each write unit of a memory cell constituting said memory array. And a power supply control unit that performs control based on a count value of a counter provided for each of the write units. 11. The nonvolatile semiconductor memory device according to claim 1, wherein said counter is provided at least for each of an erase unit and a write unit of a memory cell constituting said memory array. A nonvolatile semiconductor memory device, wherein the memory control unit and the power supply control unit perform control based on a count value of a counter provided for each of the erase unit and the write unit. 12. The non-volatile semiconductor memory device according to claim 1, wherein the memory control unit is configured to execute the operation when the count value of the counter is equal to or more than a preset value. A non-volatile semiconductor memory device that controls so that data cannot be rewritten. 13. The non-volatile semiconductor memory device according to claim 1, wherein the memory control unit indicates that the count value of the counter has reached or exceeded a preset value. A non-volatile semiconductor memory device, which outputs a set value excess signal to be notified outside to the outside of the device. 14. A memory array having at least memory cells arranged in a grid in a row direction and a column direction; decoding means for selecting a memory cell of the memory array; and a memory cell selected by the decoding means. Data detecting means for detecting and outputting a state, wherein a hamming distance between mode signals indicating adjacent operation modes before and after the transition is minimized in an erase sequence in which the operation mode transitions continuously. Nonvolatile semiconductor memory device. 15. A memory array comprising at least memory cells arranged in a grid in a row direction and a column direction; decoding means for selecting a memory cell of the memory array; and a memory cell selected by the decoding means. Data detection means for detecting and outputting a state, wherein in a write sequence in which the operation modes continuously transition, the Hamming distance between mode signals indicating adjacent operation modes before and after the transition is minimized. Nonvolatile semiconductor memory device.