KR20110065759A - Method of operating a non volatile memory device - Google Patents

Method of operating a non volatile memory device Download PDF

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Publication number
KR20110065759A
KR20110065759A KR1020090122399A KR20090122399A KR20110065759A KR 20110065759 A KR20110065759 A KR 20110065759A KR 1020090122399 A KR1020090122399 A KR 1020090122399A KR 20090122399 A KR20090122399 A KR 20090122399A KR 20110065759 A KR20110065759 A KR 20110065759A
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KR
South Korea
Prior art keywords
erase
fail bit
memory block
voltage
start voltage
Prior art date
Application number
KR1020090122399A
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Korean (ko)
Inventor
박용대
Original Assignee
주식회사 하이닉스반도체
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Priority to KR1020090122399A priority Critical patent/KR20110065759A/en
Publication of KR20110065759A publication Critical patent/KR20110065759A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/30—Power supply circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/344—Arrangements for verifying correct erasure or for detecting overerased cells
    • G11C16/3445—Circuits or methods to verify correct erasure of nonvolatile memory cells

Abstract

A method of operating a nonvolatile memory device according to an exemplary embodiment of the present disclosure may include providing a nonvolatile memory device including a plurality of memory blocks: inputting an erase command; Applying an erase voltage from a first erase start voltage of an increment step pulse erase (ISPE) scheme to the selected memory block to erase and verify the selected memory block; Counting fail bits generated in the verifying step and storing counted fail bit information together with memory block information; Calculating a fail bit of an entire memory block using the stored fail bit information when all of the plurality of memory blocks are programmed and erased at least once; and failing and setting a fail bit of the entire memory block. Comparing and changing or maintaining the first erase start voltage for the erase operation according to the result.

Description

Method of operating a non volatile memory device

The present invention relates to a method of operating a nonvolatile memory device.

Among the memory devices, the nonvolatile memory device does not erase stored data even when power supply is interrupted. A typical nonvolatile memory device is a flash memory device. Flash memory devices can be classified into NOR flash memory devices and NAND flash memory devices according to the structure of the memory cell array. The gate of the flash memory cell has a structure including a tunnel insulating film, a floating gate, a dielectric film, and a control gate.

Memory cells of the nonvolatile memory device are programmed using F-N tunneling. When a high voltage is applied to the control gate of the memory cell during the program operation, electrons are accumulated in the floating gate. In the read operation, the threshold voltage of the memory cell, which varies according to the amount of electrons accumulated in the floating gate, is detected, and the stored data is determined according to the detected threshold voltage level.

The nonvolatile memory cell is an electric program / eraseable device that performs program and erase operations by changing a threshold voltage of a cell while electrons are moved by a strong electric field applied to a thin oxide film.

A nonvolatile memory device typically includes a memory cell array in which cells in which data is stored is formed in a matrix form, and a page buffer for writing a memory to a specific cell of the memory cell array or reading a memory stored in the specific cell. The page buffer may include a pair of bit lines connected to a specific memory cell, a register for temporarily storing data to be written to the memory cell array, or a register for reading and temporarily storing data of a specific cell from the memory cell array, a voltage of a specific bit line or a specific register. It includes a sensing node for sensing a level, a bit line selection unit for controlling the connection of the specific bit line and the sensing node.

Such a nonvolatile memory device has a characteristic in that electrons are trapped in a memory cell as the number of program / erase operations increases, thereby increasing a threshold voltage. According to this characteristic, as the number of program / erase times increases, a higher erase voltage is required even during the erase operation, and the number of fail bits increases.

Accordingly, a technical problem of the present invention is to control the erase voltage using the number of fail bits generated in the erase operation of the nonvolatile memory device, thereby preventing the erase operation time from being longer depending on the number of program / erase cycles. It is to provide a method of operating a memory device.

Method of operating a nonvolatile memory device according to a feature of the present invention,

A nonvolatile memory device including a plurality of memory blocks is provided, comprising: inputting an erase command; Applying an erase voltage from a first erase start voltage of an increment step pulse erase (ISPE) scheme to the selected memory block to erase and verify the selected memory block; Counting fail bits generated in the verifying step and storing counted fail bit information together with memory block information; Calculating a fail bit of an entire memory block using the stored fail bit information when all of the plurality of memory blocks are programmed and erased at least once; and failing and setting a fail bit of the entire memory block. Comparing and changing or maintaining the first erase start voltage for the erase operation according to the result.

Method of operating a nonvolatile memory device according to another embodiment of the present invention,

A method of erasing a selected memory block in a nonvolatile memory device including a plurality of memory blocks, wherein the erase operation is performed by applying an erase voltage having a first erase start voltage level to the selected memory block as an erase pulse is applied. A first erase and verify step of performing erase verification; If it is determined that the erase verification is a fail, it is determined whether the number of erase pulses applied to the present is smaller than the set maximum pulse application number, and as a result of the determination, the number of erase pulses applied so far is smaller than the maximum pulse application count. A second erase and verify step of applying a new erase pulse and increasing an erase voltage by a set step voltage to perform erase and verify on the selected memory block; If verification fails in the second erasing and verifying step, repeating the second erasing and verifying step until an erase verification passes or the number of erase pulses is equal to the set maximum pulse application times. ; If the number of erase pulses is equal to the set maximum pulse number of times during the second erase and verify step, the bit determined as a fail in the previous erase verify is counted, and the counted fail bit information is counted. Storing with memory block information; Calculating a fail bit of an entire memory block using the stored fail bit information when all of the plurality of memory blocks are programmed and erased at least once; and failing and setting a fail bit of the entire memory block. Comparing and changing or maintaining the first erase start voltage level for the erase operation according to the result.

When the fail bit of the entire memory block is larger than the set fail bit, the erase start voltage is changed to a second erase start voltage level that is increased by a voltage level that is set by the first erase start voltage level.

As described above, in the method of operating the nonvolatile memory device according to the present invention, the erase operation time is lengthened by determining the number of program / erase times and controlling the erase voltage according to the number of fail bits generated in the erase operation of the memory block. And erase erase of a memory block.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. It is provided to inform you.

1 illustrates a nonvolatile memory device according to an embodiment of the present invention.

Referring to FIG. 1, the nonvolatile memory device 100 may include a memory cell array 110, a page buffer unit 120, a data input / output unit 130, an X decoder 140, a voltage providing unit 150, and a controller ( 160).

The memory cell array 110 includes a plurality of memory blocks BK. Each memory block BK includes a plurality of memory cells, and the memory cells are connected to a bit line BL and a word line WL.

Each memory block BK includes first to thirty-second word lines WL0 to WL31.

The nonvolatile memory device 100 performs a program in units of pages when performing a program, and operates in units of a memory block BK in an erase operation.

The page buffer unit 120 includes page buffers connected to one or more bit lines. Each page buffer includes one or more latch circuits, and latches data for a program or reads and stores data stored in a memory cell.

In an embodiment of the present invention, one of the memory blocks BK is designated as a fail bit counter block FBK. The fail bit counter block FBK stores fail number information during an erase operation of another memory block. It is also possible to further include a separate storage means for storing the fail number information.

The data input / output unit 130 performs data input / output to the page buffer unit 120 according to the control signal of the controller 160.

The X decoder 140 connects word lines of the memory cell array 110 to a global word line GWL provided with an operating voltage.

The voltage provider 150 generates operating voltages including a program voltage, a pass voltage, and a read voltage based on a control signal input from the controller 160 and provides the generated voltages to the global word line GWL.

The controller 160 outputs control signals for controlling the operation of the nonvolatile memory device 100. In particular, the controller 160 selects a memory block using a ware leveling method that allows the same number of programs / erases to be applied to the memory blocks.

When the number of programs / erases of the memory blocks BK is maintained to be substantially the same according to the wear leveling method, the degree of deterioration becomes similar since all the memory blocks BK are subjected to the same stress. Therefore, the level of the operating voltage to be provided for program and erase can be controlled in the same way.

When the erase operation is performed, the controller 160 applies an erase voltage according to an increment step pulse erase (ISPE) scheme. That is, the erase voltage is increased by the step voltage from the erase start voltage in response to the erase pulse applied for the erase operation.

In the erase operation, if a fail bit is generated to the extent that ECC correction is possible, the controller 160 ends the erase operation without performing further erase. The number of generated fail bits is counted and stored in the fail bit counter block FBK.

When the erase operation is performed one or more times on all the memory blocks by the wear leveling method, the controller 160 uses the fail bit information stored in the fail bit counter block FBK to generate the fail bits generated in all the memory blocks BK. The number is checked and the voltage level of the erase start voltage is changed according to the identified total number of fail bits.

2A illustrates an erase voltage applied according to a general ISPE scheme.

In FIG. 2A, the erase voltage Verase is applied from the erase start voltage Vstart and is increased by the step voltage Vth as the erase pulse is applied. The erase pulse is applied up to N times. If an erase pulse is applied up to N times and the erase is not performed, the memory block is failed.

As described above with reference to FIG. 1, the controller 160 counts fail bits during the erase operation. When the counted fail bits are less than or equal to the set number, the controller 160 determines that the erase has passed and terminates the erase operation.

The erase operation is performed in units of memory blocks. When the program and erase are repeated and the number of times of program / erase is increased, the threshold voltages of the memory cells are increased to generate a large number of fail bits as shown in FIG. 2B.

2B illustrates threshold voltage distributions of erase cells that change as the number of programs / erases increases.

Referring to FIG. 2B, the first threshold voltage distribution 210 represents a case where a program / erase count is one time, and the second threshold voltage distribution 220 represents a case where a program / erase count is 1K times.

As shown in FIG. 2B, as the number of programs / erases increases, the width of the threshold voltage distribution of the memory cells in the erased state becomes wider, and the probability of failing due to the erase voltage Verase under the same condition as in FIG. 2A increases.

In an embodiment of the present invention, in order to solve this problem, the erase start voltage of the erase voltage Verase is changed by using fail bit information of the memory blocks BK.

3A and 3B illustrate erase voltage and threshold voltage distributions for explaining the case of changing the erase start voltage.

Referring to FIG. 3A, examples of the first to third erase voltages Verase1 to Verase3 are shown. The first erase voltage Verase1 has an erase start voltage of 17V, the second erase voltage Verase2 has an erase start voltage of 18V, and the third erase voltage Verase3 has an erase start voltage of 19V. In addition, the first to third erase voltages Verase1 to Verase3 are set to apply up to four erase pulses.

When the number of programs / erases of the memory block BK is 1K or less, the erase operation is performed using the first erase voltage Verase1.

When the number of programs / erases of the memory block BK is 1K or more and 10K or less, the erase is performed by using the second erase voltage Verase2.

The third erase voltage Verase3 is used when the number of programs / erases of the memory block BK is 10K or more.

As described above, when the erase start voltage is changed according to the number of times of program / erase, threshold voltage distributions of the memory cells are changed as shown in FIG. 3B.

That is, the first threshold voltage distribution 210 is a threshold voltage distribution having a narrow width of -1V or less as in FIG. 2B. However, when the number of program / erase times is 1K, the third threshold voltage distribution 300 having the same width as the second threshold voltage distribution 220 and having the threshold voltage distribution moved below −1 V is formed.

That is, although it is difficult to narrow the width of the threshold voltage distribution, the threshold voltage distribution of the memory cell is changed to -1V or less so that the fail bit may not be generated.

To this end, a method of changing the erase voltage is as follows.

4 is a flowchart illustrating an erase operation according to an exemplary embodiment of the present invention.

Referring to FIG. 4, when an erase command for the memory block BK is input (S401), the controller 160 checks and sets the erase start voltage that is currently set, and sets the erase pulse application count to '0'. Initialize

If an erase pulse is applied, erase and verify are performed (S405).

Erasing and verifying is the same operation as erasing and verifying a typical memory block. Then, it is checked whether the verification has passed (S407). In this case, as described above, the controller 160 determines that the verification passes when a fail bit occurs below a predetermined number.

If the verification does not pass, it is checked whether the erase pulse has been applied N times (S409). If the erase pulse has not been applied up to N times, the erase pulse is increased by one, and the erase voltage is increased by the step voltage (S411). Then erase and verify is performed again (S405).

The N number may be defined differently according to the memory device, and in the embodiment of the present invention, it can be assumed as four times.

On the other hand, if the erase verification passes, or if the erase pulse has been applied up to N times, the fail bit is counted, and the counted fail bit number information is stored in the fail bit count block FBK. The fail bit number information is divided and stored for each memory block. That is, if the erase pulse is applied up to four times assumed in the embodiment of the present invention, only the number of fail bits is stored in the fail bit count block FBK without increasing the erase voltage.

If the erase pass is performed with three erase pulses applied without performing erase verification up to four times, the number of fail bits is '0', and '0' is failed as the fail bit number information for the corresponding memory block. It is stored in the bit count block FBK.

Meanwhile, the controller 160 checks whether the program / erase has been performed at least once for all the memory blocks BK of the memory cell array 110 (S415). This is because the fail bit generated in the entire memory block can be identified only when the entire memory block is erased. The reason for using the fail bit generated in all memory blocks is that the wear leveling method controls the same number of program / erase times for all memory blocks.

If the erase is not completed at least once for the entire memory block, the controller waits for a new erase command to be input to another memory block (S419) and performs an erase and verify operation (S405 to S413).

On the other hand, if the erase is completed at least once for the entire memory block, the fail bit counter block FBK stores the fail bit number information in the entire memory block.

Accordingly, the controller 160 calculates the total fail bit Tf by loading the stored fail bit number (S417), and compares the total fail bit Tf with the preset fail bit K.

The preset fail bit K is, for example, the number of fail bits that can be generated after 1K program / erase is performed. In FIG. 4, the fail bit K is set to one, but a plurality of fail bits may be set depending on the number of times of program / erase.

On the other hand, when the entire fail bit Tf becomes larger than the set fail bit K, the erase start voltage is changed (S423). For example, the erase start voltage is set by increasing the voltage by 1V as shown in FIG. 3A.

However, if the entire fail bit Tf is not greater than the set fail bit K, the current erase start voltage is maintained as it is (S425).

If a new erase command is input later (S427), the erase operation is performed using the set erase start voltage. In addition, after at least one erase operation is completed for the entire memory block, as the erase is performed in the memory block, the total number of fail bits Tf is updated, and the updated total fail bits Tf are set to the fail bit K. The erase start voltage is controlled in comparison with.

As described above, the threshold voltage shift of the memory cell is predicted using the fail bit in the entire memory blocks BK, and the erase start voltage is increased to eliminate unnecessary erase operations. That is, as shown in FIG. 3A, while the erase start voltage is increased from the first to second erase voltages Verase1 to Verase3, the erase operation with respect to the previous erase voltage is unnecessary. Therefore, it is possible to prevent the erase time due to the unnecessary erase operation from lengthening. In addition, the fail bit of the erased memory cells is reduced, thereby ensuring reliability of subsequent program operations.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those of ordinary skill in the art that various embodiments are possible within the scope of the technical idea of the present invention.

1 illustrates a nonvolatile memory device according to an embodiment of the present invention.

2A illustrates an erase voltage applied according to a general ISPE scheme.

2B illustrates threshold voltage distributions of erase cells that change as the number of programs / erases increases.

3A and 3B illustrate erase voltage and threshold voltage distributions for explaining the case of changing the erase start voltage.

4 is a flowchart illustrating an erase operation according to an exemplary embodiment of the present invention.

Claims (11)

A nonvolatile memory device including a plurality of memory blocks is provided. Inputting an erase command; Applying an erase voltage from a first erase start voltage of an increment step pulse erase (ISPE) scheme to the selected memory block to erase and verify the selected memory block; Counting fail bits generated in the verifying step and storing counted fail bit information together with memory block information; Calculating a fail bit of the entire memory block by using the stored fail bit information when all of the plurality of memory blocks are programmed and erased at least once; and Comparing the fail bit of the entire memory block with a set fail bit, and changing or maintaining the first erase start voltage for the erase operation according to the result; Method of operating a nonvolatile memory device comprising a. The method of claim 1, And when the program and the erase have not been performed at least once in all of the plurality of memory blocks, an erase operation is performed by applying the first erase start voltage set as a default. The method of claim 1, Storing the counted fail information, Select one of the plurality of memory blocks and store the fail bit information in the selected memory block, wherein each fail bit information is stored together with information of a corresponding memory block; Way. The method of claim 1, If the fail bit of the entire memory block is larger than a set fail bit, changing the erase start voltage to a second erase start voltage that is increased by a voltage set to be greater than the first erase start voltage. . The method of claim 4, wherein When the first erase start voltage changes, the erase operation is performed by applying an erase voltage from the changed second erase start voltage when an erase command is input. The method of claim 1, When performing the erase and verification, if the counted fail bit is less than k (k is a natural number), it is determined that the erase pass. A method of erasing a selected memory block in a nonvolatile memory device including a plurality of memory blocks, A first erase and verify step of applying an erase voltage having a first erase start voltage level to the selected memory block as an erase pulse is applied to perform an erase operation, and performing erase verification; If it is determined that the erase verification is a fail, it is determined whether the number of erase pulses applied to the present is smaller than the set maximum pulse application number, and as a result of the determination, the number of erase pulses applied so far is smaller than the maximum pulse application count. A second erase and verify step of applying a new erase pulse and increasing an erase voltage by a set step voltage to perform erase and verify on the selected memory block; If verification fails in the second erasing and verifying step, repeating the second erasing and verifying step until an erase verification passes or the number of erase pulses is equal to the set maximum pulse application times. ; If the number of erase pulses is equal to the set maximum pulse number of times during the second erase and verify step, the bit determined as a fail in the previous erase verify is counted, and the counted fail bit information is counted. Storing with memory block information; Calculating a fail bit of all memory blocks by using the stored fail bit information when all of the plurality of memory blocks are programmed and erased at least once; and Comparing a fail bit of the entire memory block with a set fail bit, and changing or maintaining the first erase start voltage level for the erase operation according to the result; Method of operating a nonvolatile memory device comprising a. The method of claim 7, wherein While repeatedly performing the second erase and verify steps, if erase verification passes when the number of erase pulses is less than the set maximum pulse number, the fail bit of the corresponding memory block is stored as '0'. Method of operation of volatile memory device. The method of claim 7, wherein When correction of an error of k bits or less is possible in the nonvolatile memory device, it is determined as a pass for erasure verification in which a k bit or less fail bit is generated, and the counted fail bit is stored as fail bit information of the corresponding memory block. A method of operating a nonvolatile memory device, characterized in that. The method of claim 7, wherein When the fail bit of the entire memory block is greater than a set fail bit, changing the erase start voltage to a second erase start voltage level that is increased by a voltage level that is higher than the first erase start voltage level. Method of operation. The method of claim 10, When the first erase start voltage changes, the erase operation is performed by applying an erase voltage from the changed second erase start voltage when an erase command is input.
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Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102270506A (en) * 2011-06-28 2011-12-07 上海宏力半导体制造有限公司 Programming/erasing method of flash memory
CN103854701A (en) * 2012-12-03 2014-06-11 爱思开海力士有限公司 Method for erasing charge trap devices
US8929149B2 (en) 2012-08-08 2015-01-06 SK Hynix Inc. Semiconductor memory device and method of operating the same
US9019773B2 (en) 2012-11-01 2015-04-28 Samsung Electronics Co., Ltd. Nonvolatile memory device and method of operating the same
KR20160011068A (en) * 2014-07-21 2016-01-29 삼성전자주식회사 Semiconductor memory device and memory system including the same
US9704596B1 (en) 2016-01-13 2017-07-11 Samsung Electronics Co., Ltd. Method of detecting erase fail word-line in non-volatile memory device
KR20190143078A (en) 2018-06-20 2019-12-30 (주)에이피텍 LED module inspection and packing system
US10957411B2 (en) 2018-09-12 2021-03-23 SK Hynix Inc. Apparatus and method for managing valid data in memory system

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102270506A (en) * 2011-06-28 2011-12-07 上海宏力半导体制造有限公司 Programming/erasing method of flash memory
CN102270506B (en) * 2011-06-28 2016-12-28 上海华虹宏力半导体制造有限公司 A kind of program/erase method of flash memory
US8929149B2 (en) 2012-08-08 2015-01-06 SK Hynix Inc. Semiconductor memory device and method of operating the same
US9019773B2 (en) 2012-11-01 2015-04-28 Samsung Electronics Co., Ltd. Nonvolatile memory device and method of operating the same
CN103854701A (en) * 2012-12-03 2014-06-11 爱思开海力士有限公司 Method for erasing charge trap devices
KR20140072366A (en) * 2012-12-03 2014-06-13 에스케이하이닉스 주식회사 Erasing method for charge trap device
CN103854701B (en) * 2012-12-03 2019-08-06 爱思开海力士有限公司 The method for deleting of charge trap device
KR20160011068A (en) * 2014-07-21 2016-01-29 삼성전자주식회사 Semiconductor memory device and memory system including the same
US9704596B1 (en) 2016-01-13 2017-07-11 Samsung Electronics Co., Ltd. Method of detecting erase fail word-line in non-volatile memory device
KR20190143078A (en) 2018-06-20 2019-12-30 (주)에이피텍 LED module inspection and packing system
US10957411B2 (en) 2018-09-12 2021-03-23 SK Hynix Inc. Apparatus and method for managing valid data in memory system

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