JP2002520872A - ポリシリコン用ドーピング無依存式自己清浄エッチング処理 - Google Patents

ポリシリコン用ドーピング無依存式自己清浄エッチング処理

Info

Publication number
JP2002520872A
JP2002520872A JP2000560302A JP2000560302A JP2002520872A JP 2002520872 A JP2002520872 A JP 2002520872A JP 2000560302 A JP2000560302 A JP 2000560302A JP 2000560302 A JP2000560302 A JP 2000560302A JP 2002520872 A JP2002520872 A JP 2002520872A
Authority
JP
Japan
Prior art keywords
gas
etching
processing chamber
substrate
volume flow
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000560302A
Other languages
English (en)
Japanese (ja)
Other versions
JP2002520872A5 (enExample
Inventor
パドマパーニ ナラン
ジェフリー シン
スティーブン ユーエン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Applied Materials Inc
Original Assignee
Applied Materials Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Applied Materials Inc filed Critical Applied Materials Inc
Publication of JP2002520872A publication Critical patent/JP2002520872A/ja
Publication of JP2002520872A5 publication Critical patent/JP2002520872A5/ja
Pending legal-status Critical Current

Links

Classifications

    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B33/00—After-treatment of single crystals or homogeneous polycrystalline material with defined structure
    • C30B33/08—Etching
    • C30B33/12—Etching in gas atmosphere or plasma
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • H01L21/02071—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a delineation, e.g. RIE, of conductive layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/905—Cleaning of reaction chamber

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Drying Of Semiconductors (AREA)
JP2000560302A 1998-07-16 1999-06-30 ポリシリコン用ドーピング無依存式自己清浄エッチング処理 Pending JP2002520872A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/116,621 1998-07-16
US09/116,621 US6322714B1 (en) 1997-11-12 1998-07-16 Process for etching silicon-containing material on substrates
PCT/US1999/014922 WO2000004213A1 (en) 1998-07-16 1999-06-30 Doping-independent self-cleaning etch process for polysilicon

Publications (2)

Publication Number Publication Date
JP2002520872A true JP2002520872A (ja) 2002-07-09
JP2002520872A5 JP2002520872A5 (enExample) 2006-08-10

Family

ID=22368266

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000560302A Pending JP2002520872A (ja) 1998-07-16 1999-06-30 ポリシリコン用ドーピング無依存式自己清浄エッチング処理

Country Status (6)

Country Link
US (1) US6322714B1 (enExample)
EP (1) EP1109955A1 (enExample)
JP (1) JP2002520872A (enExample)
KR (1) KR100738699B1 (enExample)
TW (1) TW449822B (enExample)
WO (1) WO2000004213A1 (enExample)

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KR100842675B1 (ko) * 2006-12-27 2008-06-30 동부일렉트로닉스 주식회사 트랜지스터의 폴리 게이트에 대한 식각 방법
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KR20100069392A (ko) * 2008-12-16 2010-06-24 삼성전자주식회사 증착, 식각 혹은 클리닝 공정에서 증착, 식각 혹은 클리닝 종료 시점을 결정하기 위하여 수정 결정 미소저울을 이용하는 반도체 소자의 제조장치 및 이를 이용한 제조방법
US20110297088A1 (en) * 2010-06-04 2011-12-08 Texas Instruments Incorporated Thin edge carrier ring
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Also Published As

Publication number Publication date
TW449822B (en) 2001-08-11
KR100738699B1 (ko) 2007-07-12
EP1109955A1 (en) 2001-06-27
WO2000004213A1 (en) 2000-01-27
US6322714B1 (en) 2001-11-27
KR20010053548A (ko) 2001-06-25

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