JP2002261193A - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法

Info

Publication number
JP2002261193A
JP2002261193A JP2001061600A JP2001061600A JP2002261193A JP 2002261193 A JP2002261193 A JP 2002261193A JP 2001061600 A JP2001061600 A JP 2001061600A JP 2001061600 A JP2001061600 A JP 2001061600A JP 2002261193 A JP2002261193 A JP 2002261193A
Authority
JP
Japan
Prior art keywords
lead frame
chip
lead
concave portion
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001061600A
Other languages
English (en)
Japanese (ja)
Other versions
JP2002261193A5 (enExample
Inventor
Yoshihiko Shimanuki
好彦 嶋貫
Masayuki Suzuki
雅之 鈴木
Shigetoshi Kurihara
繁敏 栗原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Renesas Semiconductor Package and Test Solutions Co Ltd
Original Assignee
Hitachi Ltd
Hitachi Yonezawa Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi Yonezawa Electronics Co Ltd filed Critical Hitachi Ltd
Priority to JP2001061600A priority Critical patent/JP2002261193A/ja
Publication of JP2002261193A publication Critical patent/JP2002261193A/ja
Publication of JP2002261193A5 publication Critical patent/JP2002261193A5/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
JP2001061600A 2001-03-06 2001-03-06 半導体装置の製造方法 Pending JP2002261193A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001061600A JP2002261193A (ja) 2001-03-06 2001-03-06 半導体装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001061600A JP2002261193A (ja) 2001-03-06 2001-03-06 半導体装置の製造方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2010086837A Division JP2010177692A (ja) 2010-04-05 2010-04-05 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
JP2002261193A true JP2002261193A (ja) 2002-09-13
JP2002261193A5 JP2002261193A5 (enExample) 2008-04-17

Family

ID=18920869

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001061600A Pending JP2002261193A (ja) 2001-03-06 2001-03-06 半導体装置の製造方法

Country Status (1)

Country Link
JP (1) JP2002261193A (enExample)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007258590A (ja) * 2006-03-24 2007-10-04 Disco Abrasive Syst Ltd パッケージ基板の分割方法
JP2008182175A (ja) * 2006-12-27 2008-08-07 Denso Corp モールドパッケージの製造方法
JP2009158835A (ja) * 2007-12-27 2009-07-16 Oki Semiconductor Co Ltd 半導体装置の製造方法。
JP2009259927A (ja) * 2008-04-15 2009-11-05 New Japan Radio Co Ltd リードフレームの設計方法
WO2015111623A1 (ja) * 2014-01-22 2015-07-30 大日本印刷株式会社 リードフレームおよびその製造方法、ならびに半導体装置およびその製造方法
WO2020087584A1 (zh) * 2018-10-30 2020-05-07 惠科股份有限公司 引脚组件及显示装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5769246A (en) * 1980-10-18 1982-04-27 Sumitomo Metal Ind Ltd Eddy current type method for judging abnormal quality of material
JPH0982833A (ja) * 1995-09-20 1997-03-28 Fujitsu Ltd 半導体装置の入出力電極形成方法と半導体装置
JP2000133658A (ja) * 1998-10-27 2000-05-12 Matsushita Electric Ind Co Ltd 電子部品の製造方法
JP2000286377A (ja) * 1999-03-30 2000-10-13 Sanyo Electric Co Ltd 半導体装置
JP2001077279A (ja) * 1999-09-01 2001-03-23 Matsushita Electronics Industry Corp リードフレームとそれを用いた樹脂封止型半導体装置の製造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5769246A (en) * 1980-10-18 1982-04-27 Sumitomo Metal Ind Ltd Eddy current type method for judging abnormal quality of material
JPH0982833A (ja) * 1995-09-20 1997-03-28 Fujitsu Ltd 半導体装置の入出力電極形成方法と半導体装置
JP2000133658A (ja) * 1998-10-27 2000-05-12 Matsushita Electric Ind Co Ltd 電子部品の製造方法
JP2000286377A (ja) * 1999-03-30 2000-10-13 Sanyo Electric Co Ltd 半導体装置
JP2001077279A (ja) * 1999-09-01 2001-03-23 Matsushita Electronics Industry Corp リードフレームとそれを用いた樹脂封止型半導体装置の製造方法

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007258590A (ja) * 2006-03-24 2007-10-04 Disco Abrasive Syst Ltd パッケージ基板の分割方法
JP2008182175A (ja) * 2006-12-27 2008-08-07 Denso Corp モールドパッケージの製造方法
JP2009158835A (ja) * 2007-12-27 2009-07-16 Oki Semiconductor Co Ltd 半導体装置の製造方法。
JP2009259927A (ja) * 2008-04-15 2009-11-05 New Japan Radio Co Ltd リードフレームの設計方法
WO2015111623A1 (ja) * 2014-01-22 2015-07-30 大日本印刷株式会社 リードフレームおよびその製造方法、ならびに半導体装置およびその製造方法
WO2020087584A1 (zh) * 2018-10-30 2020-05-07 惠科股份有限公司 引脚组件及显示装置

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